1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the ARM target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 79;
11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 mutable MatcherState State;
16 typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19 static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 const int64_t *getMatchTable() const override;
25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29, State(0),
30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33#ifdef GET_GLOBALISEL_IMPL
34// Bits for subtarget features that participate in instruction matching.
35enum SubtargetFeatureBits : uint8_t {
36 Feature_NoHonorSignDependentRoundingBit = 70,
37 Feature_HasV4TBit = 6,
38 Feature_NoV4TBit = 7,
39 Feature_HasV5TBit = 13,
40 Feature_NoV5TBit = 64,
41 Feature_HasV5TEBit = 11,
42 Feature_HasV6Bit = 0,
43 Feature_NoV6Bit = 9,
44 Feature_HasV6MBit = 29,
45 Feature_HasV8MBaselineBit = 34,
46 Feature_HasV8_1MMainlineBit = 40,
47 Feature_HasMVEIntBit = 62,
48 Feature_HasMVEFloatBit = 63,
49 Feature_HasCDEBit = 78,
50 Feature_HasFPRegsBit = 41,
51 Feature_HasFPRegs16Bit = 42,
52 Feature_HasNoFPRegs16Bit = 69,
53 Feature_HasFPRegs64Bit = 51,
54 Feature_HasV6T2Bit = 8,
55 Feature_HasV6KBit = 19,
56 Feature_HasV7Bit = 3,
57 Feature_HasV8Bit = 15,
58 Feature_PreV8Bit = 20,
59 Feature_HasV8_1aBit = 72,
60 Feature_HasV8_3aBit = 73,
61 Feature_NoVFPBit = 23,
62 Feature_HasVFP2Bit = 22,
63 Feature_HasVFP3Bit = 52,
64 Feature_HasVFP4Bit = 49,
65 Feature_HasDPVFPBit = 43,
66 Feature_HasFPARMv8Bit = 46,
67 Feature_HasNEONBit = 53,
68 Feature_HasCryptoBit = 54,
69 Feature_HasDotProdBit = 55,
70 Feature_HasCRCBit = 14,
71 Feature_HasLOBBit = 39,
72 Feature_HasFP16Bit = 60,
73 Feature_HasFullFP16Bit = 45,
74 Feature_HasBF16Bit = 61,
75 Feature_HasMatMulInt8Bit = 56,
76 Feature_HasDivideInThumbBit = 36,
77 Feature_HasDivideInARMBit = 12,
78 Feature_HasDSPBit = 35,
79 Feature_HasDBBit = 16,
80 Feature_HasV7ClrexBit = 18,
81 Feature_HasAcquireReleaseBit = 17,
82 Feature_HasMPBit = 2,
83 Feature_Has8MSecExtBit = 30,
84 Feature_HasZCZBit = 57,
85 Feature_UseNEONForFPBit = 76,
86 Feature_DontUseNEONForFPBit = 44,
87 Feature_IsThumbBit = 27,
88 Feature_IsThumb1OnlyBit = 28,
89 Feature_IsThumb2Bit = 33,
90 Feature_IsNotMClassBit = 37,
91 Feature_IsARMBit = 1,
92 Feature_IsWindowsBit = 31,
93 Feature_IsNotWindowsBit = 32,
94 Feature_IsReadTPHardBit = 67,
95 Feature_IsReadTPSoftBit = 21,
96 Feature_UseNaClTrapBit = 4,
97 Feature_DontUseNaClTrapBit = 5,
98 Feature_UseMovtBit = 38,
99 Feature_DontUseMovtBit = 24,
100 Feature_UseMovtInPicBit = 25,
101 Feature_DontUseMovtInPicBit = 26,
102 Feature_UseFPVMLxBit = 48,
103 Feature_SLSBLRMitigationBit = 66,
104 Feature_NoSLSBLRMitigationBit = 65,
105 Feature_UseMulOpsBit = 10,
106 Feature_UseFusedMACBit = 50,
107 Feature_HasFastVGETLNi32Bit = 58,
108 Feature_HasSlowVGETLNi32Bit = 74,
109 Feature_HasFastVDUP32Bit = 59,
110 Feature_HasSlowVDUP32Bit = 75,
111 Feature_UseVMOVSRBit = 47,
112 Feature_DontUseVMOVSRBit = 77,
113 Feature_IsLEBit = 68,
114 Feature_IsBEBit = 71,
115};
116
117PredicateBitset ARMInstructionSelector::
118computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
119 PredicateBitset Features;
120 if (!TM.Options.HonorSignDependentRoundingFPMath())
121 Features.set(Feature_NoHonorSignDependentRoundingBit);
122 if (Subtarget->hasV4TOps())
123 Features.set(Feature_HasV4TBit);
124 if (!Subtarget->hasV4TOps())
125 Features.set(Feature_NoV4TBit);
126 if (Subtarget->hasV5TOps())
127 Features.set(Feature_HasV5TBit);
128 if (!Subtarget->hasV5TOps())
129 Features.set(Feature_NoV5TBit);
130 if (Subtarget->hasV5TEOps())
131 Features.set(Feature_HasV5TEBit);
132 if (Subtarget->hasV6Ops())
133 Features.set(Feature_HasV6Bit);
134 if (!Subtarget->hasV6Ops())
135 Features.set(Feature_NoV6Bit);
136 if (Subtarget->hasV6MOps())
137 Features.set(Feature_HasV6MBit);
138 if (Subtarget->hasV8MBaselineOps())
139 Features.set(Feature_HasV8MBaselineBit);
140 if (Subtarget->hasV8_1MMainlineOps())
141 Features.set(Feature_HasV8_1MMainlineBit);
142 if (Subtarget->hasMVEIntegerOps())
143 Features.set(Feature_HasMVEIntBit);
144 if (Subtarget->hasMVEFloatOps())
145 Features.set(Feature_HasMVEFloatBit);
146 if (Subtarget->hasCDEOps())
147 Features.set(Feature_HasCDEBit);
148 if (Subtarget->hasFPRegs())
149 Features.set(Feature_HasFPRegsBit);
150 if (Subtarget->hasFPRegs16())
151 Features.set(Feature_HasFPRegs16Bit);
152 if (!Subtarget->hasFPRegs16())
153 Features.set(Feature_HasNoFPRegs16Bit);
154 if (Subtarget->hasFPRegs64())
155 Features.set(Feature_HasFPRegs64Bit);
156 if (Subtarget->hasV6T2Ops())
157 Features.set(Feature_HasV6T2Bit);
158 if (Subtarget->hasV6KOps())
159 Features.set(Feature_HasV6KBit);
160 if (Subtarget->hasV7Ops())
161 Features.set(Feature_HasV7Bit);
162 if (Subtarget->hasV8Ops())
163 Features.set(Feature_HasV8Bit);
164 if (!Subtarget->hasV8Ops())
165 Features.set(Feature_PreV8Bit);
166 if (Subtarget->hasV8_1aOps())
167 Features.set(Feature_HasV8_1aBit);
168 if (Subtarget->hasV8_3aOps())
169 Features.set(Feature_HasV8_3aBit);
170 if (!Subtarget->hasVFP2Base())
171 Features.set(Feature_NoVFPBit);
172 if (Subtarget->hasVFP2Base())
173 Features.set(Feature_HasVFP2Bit);
174 if (Subtarget->hasVFP3Base())
175 Features.set(Feature_HasVFP3Bit);
176 if (Subtarget->hasVFP4Base())
177 Features.set(Feature_HasVFP4Bit);
178 if (Subtarget->hasFP64())
179 Features.set(Feature_HasDPVFPBit);
180 if (Subtarget->hasFPARMv8Base())
181 Features.set(Feature_HasFPARMv8Bit);
182 if (Subtarget->hasNEON())
183 Features.set(Feature_HasNEONBit);
184 if (Subtarget->hasCrypto())
185 Features.set(Feature_HasCryptoBit);
186 if (Subtarget->hasDotProd())
187 Features.set(Feature_HasDotProdBit);
188 if (Subtarget->hasCRC())
189 Features.set(Feature_HasCRCBit);
190 if (Subtarget->hasLOB())
191 Features.set(Feature_HasLOBBit);
192 if (Subtarget->hasFP16())
193 Features.set(Feature_HasFP16Bit);
194 if (Subtarget->hasFullFP16())
195 Features.set(Feature_HasFullFP16Bit);
196 if (Subtarget->hasBF16())
197 Features.set(Feature_HasBF16Bit);
198 if (Subtarget->hasMatMulInt8())
199 Features.set(Feature_HasMatMulInt8Bit);
200 if (Subtarget->hasDivideInThumbMode())
201 Features.set(Feature_HasDivideInThumbBit);
202 if (Subtarget->hasDivideInARMMode())
203 Features.set(Feature_HasDivideInARMBit);
204 if (Subtarget->hasDSP())
205 Features.set(Feature_HasDSPBit);
206 if (Subtarget->hasDataBarrier())
207 Features.set(Feature_HasDBBit);
208 if (Subtarget->hasV7Clrex())
209 Features.set(Feature_HasV7ClrexBit);
210 if (Subtarget->hasAcquireRelease())
211 Features.set(Feature_HasAcquireReleaseBit);
212 if (Subtarget->hasMPExtension())
213 Features.set(Feature_HasMPBit);
214 if (Subtarget->has8MSecExt())
215 Features.set(Feature_Has8MSecExtBit);
216 if (Subtarget->hasZeroCycleZeroing())
217 Features.set(Feature_HasZCZBit);
218 if (Subtarget->useNEONForSinglePrecisionFP())
219 Features.set(Feature_UseNEONForFPBit);
220 if (!Subtarget->useNEONForSinglePrecisionFP())
221 Features.set(Feature_DontUseNEONForFPBit);
222 if (Subtarget->isThumb())
223 Features.set(Feature_IsThumbBit);
224 if (Subtarget->isThumb1Only())
225 Features.set(Feature_IsThumb1OnlyBit);
226 if (Subtarget->isThumb2())
227 Features.set(Feature_IsThumb2Bit);
228 if (!Subtarget->isMClass())
229 Features.set(Feature_IsNotMClassBit);
230 if (!Subtarget->isThumb())
231 Features.set(Feature_IsARMBit);
232 if (Subtarget->isTargetWindows())
233 Features.set(Feature_IsWindowsBit);
234 if (!Subtarget->isTargetWindows())
235 Features.set(Feature_IsNotWindowsBit);
236 if (Subtarget->isReadTPHard())
237 Features.set(Feature_IsReadTPHardBit);
238 if (!Subtarget->isReadTPHard())
239 Features.set(Feature_IsReadTPSoftBit);
240 if (Subtarget->useNaClTrap())
241 Features.set(Feature_UseNaClTrapBit);
242 if (!Subtarget->useNaClTrap())
243 Features.set(Feature_DontUseNaClTrapBit);
244 if (Subtarget->useMulOps())
245 Features.set(Feature_UseMulOpsBit);
246 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx())
247 Features.set(Feature_UseFusedMACBit);
248 if (!Subtarget->hasSlowVGETLNi32())
249 Features.set(Feature_HasFastVGETLNi32Bit);
250 if (Subtarget->hasSlowVGETLNi32())
251 Features.set(Feature_HasSlowVGETLNi32Bit);
252 if (!Subtarget->hasSlowVDUP32())
253 Features.set(Feature_HasFastVDUP32Bit);
254 if (Subtarget->hasSlowVDUP32())
255 Features.set(Feature_HasSlowVDUP32Bit);
256 if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
257 Features.set(Feature_UseVMOVSRBit);
258 if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
259 Features.set(Feature_DontUseVMOVSRBit);
260 return Features;
261}
262
263void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
264 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
265}
266PredicateBitset ARMInstructionSelector::
267computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
268 PredicateBitset Features;
269 if (Subtarget->useMovt())
270 Features.set(Feature_UseMovtBit);
271 if (!Subtarget->useMovt())
272 Features.set(Feature_DontUseMovtBit);
273 if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
274 Features.set(Feature_UseMovtInPicBit);
275 if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
276 Features.set(Feature_DontUseMovtInPicBit);
277 if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
278 Features.set(Feature_UseFPVMLxBit);
279 if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
280 Features.set(Feature_SLSBLRMitigationBit);
281 if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
282 Features.set(Feature_NoSLSBLRMitigationBit);
283 if (MF->getDataLayout().isLittleEndian())
284 Features.set(Feature_IsLEBit);
285 if (MF->getDataLayout().isBigEndian())
286 Features.set(Feature_IsBEBit);
287 return Features;
288}
289
290// LLT Objects.
291enum {
292 GILLT_s16,
293 GILLT_s32,
294 GILLT_s64,
295 GILLT_v2s32,
296 GILLT_v2s64,
297 GILLT_v4s1,
298 GILLT_v4s16,
299 GILLT_v4s32,
300 GILLT_v4s64,
301 GILLT_v8s1,
302 GILLT_v8s8,
303 GILLT_v8s16,
304 GILLT_v8s64,
305 GILLT_v16s1,
306 GILLT_v16s8,
307};
308const static size_t NumTypeObjects = 15;
309const static LLT TypeObjects[] = {
310 LLT::scalar(16),
311 LLT::scalar(32),
312 LLT::scalar(64),
313 LLT::vector(2, 32),
314 LLT::vector(2, 64),
315 LLT::vector(4, 1),
316 LLT::vector(4, 16),
317 LLT::vector(4, 32),
318 LLT::vector(4, 64),
319 LLT::vector(8, 1),
320 LLT::vector(8, 8),
321 LLT::vector(8, 16),
322 LLT::vector(8, 64),
323 LLT::vector(16, 1),
324 LLT::vector(16, 8),
325};
326
327// Feature bitsets.
328enum {
329 GIFBS_Invalid,
330 GIFBS_HasDotProd,
331 GIFBS_HasFP16,
332 GIFBS_HasFPARMv8,
333 GIFBS_HasFPRegs,
334 GIFBS_HasFullFP16,
335 GIFBS_HasMVEFloat,
336 GIFBS_HasMVEInt,
337 GIFBS_HasMatMulInt8,
338 GIFBS_HasNEON,
339 GIFBS_HasVFP2,
340 GIFBS_HasVFP3,
341 GIFBS_HasVFP4,
342 GIFBS_IsARM,
343 GIFBS_IsThumb,
344 GIFBS_IsThumb2,
345 GIFBS_NoHonorSignDependentRounding,
346 GIFBS_DontUseNEONForFP_HasVFP2,
347 GIFBS_DontUseVMOVSR_HasNEON,
348 GIFBS_Has8MSecExt_IsThumb,
349 GIFBS_HasBF16_HasNEON,
350 GIFBS_HasCrypto_HasV8,
351 GIFBS_HasDB_IsARM,
352 GIFBS_HasDB_IsThumb,
353 GIFBS_HasDPVFP_HasFPARMv8,
354 GIFBS_HasDPVFP_HasVFP2,
355 GIFBS_HasDPVFP_HasVFP3,
356 GIFBS_HasDPVFP_HasVFP4,
357 GIFBS_HasDPVFP_NoHonorSignDependentRounding,
358 GIFBS_HasDSP_IsThumb2,
359 GIFBS_HasDivideInARM_IsARM,
360 GIFBS_HasFP16_HasNEON,
361 GIFBS_HasFPRegs_UseVMOVSR,
362 GIFBS_HasFullFP16_HasNEON,
363 GIFBS_HasMVEInt_HasV8_1MMainline,
364 GIFBS_HasMVEInt_IsBE,
365 GIFBS_HasMVEInt_IsLE,
366 GIFBS_HasNEON_HasV8,
367 GIFBS_HasNEON_HasV8_1a,
368 GIFBS_HasNEON_HasV8_3a,
369 GIFBS_HasNEON_HasVFP4,
370 GIFBS_HasNEON_IsBE,
371 GIFBS_HasNEON_IsLE,
372 GIFBS_HasNEON_UseNEONForFP,
373 GIFBS_HasV5T_IsARM,
374 GIFBS_HasV5TE_IsARM,
375 GIFBS_HasV6_IsARM,
376 GIFBS_HasV6K_IsARM,
377 GIFBS_HasV6M_IsThumb,
378 GIFBS_HasV6T2_IsARM,
379 GIFBS_HasV7_IsARM,
380 GIFBS_HasV7Clrex_IsThumb,
381 GIFBS_HasV8MBaseline_IsThumb,
382 GIFBS_IsARM_NoV6,
383 GIFBS_IsARM_PreV8,
384 GIFBS_IsThumb_IsThumb1Only,
385 GIFBS_IsThumb_IsWindows,
386 GIFBS_IsThumb_UseMovt,
387 GIFBS_IsThumb2_PreV8,
388 GIFBS_IsThumb2_UseMulOps,
389 GIFBS_HasCRC_HasV8_IsARM,
390 GIFBS_HasCRC_HasV8_IsThumb2,
391 GIFBS_HasDSP_IsThumb2_UseMulOps,
392 GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
393 GIFBS_HasFullFP16_HasNEON_HasV8,
394 GIFBS_HasFullFP16_HasNEON_HasV8_3a,
395 GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
396 GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
397 GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
398 GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
399 GIFBS_HasV5TE_IsARM_UseMulOps,
400 GIFBS_HasV6_IsARM_UseMulOps,
401 GIFBS_HasV6_IsThumb_IsThumb1Only,
402 GIFBS_HasV6T2_IsARM_UseMulOps,
403 GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
404 GIFBS_IsARM_NoV6_UseMulOps,
405};
406const static PredicateBitset FeatureBitsets[] {
407 {}, // GIFBS_Invalid
408 {Feature_HasDotProdBit, },
409 {Feature_HasFP16Bit, },
410 {Feature_HasFPARMv8Bit, },
411 {Feature_HasFPRegsBit, },
412 {Feature_HasFullFP16Bit, },
413 {Feature_HasMVEFloatBit, },
414 {Feature_HasMVEIntBit, },
415 {Feature_HasMatMulInt8Bit, },
416 {Feature_HasNEONBit, },
417 {Feature_HasVFP2Bit, },
418 {Feature_HasVFP3Bit, },
419 {Feature_HasVFP4Bit, },
420 {Feature_IsARMBit, },
421 {Feature_IsThumbBit, },
422 {Feature_IsThumb2Bit, },
423 {Feature_NoHonorSignDependentRoundingBit, },
424 {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
425 {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
426 {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
427 {Feature_HasBF16Bit, Feature_HasNEONBit, },
428 {Feature_HasCryptoBit, Feature_HasV8Bit, },
429 {Feature_HasDBBit, Feature_IsARMBit, },
430 {Feature_HasDBBit, Feature_IsThumbBit, },
431 {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
432 {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
433 {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
434 {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
435 {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
436 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
437 {Feature_HasDivideInARMBit, Feature_IsARMBit, },
438 {Feature_HasFP16Bit, Feature_HasNEONBit, },
439 {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
440 {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
441 {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
442 {Feature_HasMVEIntBit, Feature_IsBEBit, },
443 {Feature_HasMVEIntBit, Feature_IsLEBit, },
444 {Feature_HasNEONBit, Feature_HasV8Bit, },
445 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
446 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
447 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
448 {Feature_HasNEONBit, Feature_IsBEBit, },
449 {Feature_HasNEONBit, Feature_IsLEBit, },
450 {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
451 {Feature_HasV5TBit, Feature_IsARMBit, },
452 {Feature_HasV5TEBit, Feature_IsARMBit, },
453 {Feature_HasV6Bit, Feature_IsARMBit, },
454 {Feature_HasV6KBit, Feature_IsARMBit, },
455 {Feature_HasV6MBit, Feature_IsThumbBit, },
456 {Feature_HasV6T2Bit, Feature_IsARMBit, },
457 {Feature_HasV7Bit, Feature_IsARMBit, },
458 {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
459 {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
460 {Feature_IsARMBit, Feature_NoV6Bit, },
461 {Feature_IsARMBit, Feature_PreV8Bit, },
462 {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
463 {Feature_IsThumbBit, Feature_IsWindowsBit, },
464 {Feature_IsThumbBit, Feature_UseMovtBit, },
465 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
466 {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
467 {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
468 {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
469 {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
470 {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
471 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
472 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
473 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
474 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
475 {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
476 {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
477 {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
478 {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
479 {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
480 {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
481 {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
482 {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
483};
484
485// ComplexPattern predicates.
486enum {
487 GICP_Invalid,
488};
489// See constructor for table contents
490
491// PatFrag predicates.
492enum {
493 GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
494 GIPFP_I64_Predicate_VectorIndex32,
495 GIPFP_I64_Predicate_VectorIndex64,
496 GIPFP_I64_Predicate_VectorIndex8,
497 GIPFP_I64_Predicate_asr_imm,
498 GIPFP_I64_Predicate_imm0_15,
499 GIPFP_I64_Predicate_imm0_239,
500 GIPFP_I64_Predicate_imm0_255,
501 GIPFP_I64_Predicate_imm0_31,
502 GIPFP_I64_Predicate_imm0_32,
503 GIPFP_I64_Predicate_imm0_4095,
504 GIPFP_I64_Predicate_imm0_63,
505 GIPFP_I64_Predicate_imm0_65535,
506 GIPFP_I64_Predicate_imm0_65535_neg,
507 GIPFP_I64_Predicate_imm0_7,
508 GIPFP_I64_Predicate_imm16,
509 GIPFP_I64_Predicate_imm16_31,
510 GIPFP_I64_Predicate_imm1_15,
511 GIPFP_I64_Predicate_imm1_16,
512 GIPFP_I64_Predicate_imm1_31,
513 GIPFP_I64_Predicate_imm1_7,
514 GIPFP_I64_Predicate_imm24b,
515 GIPFP_I64_Predicate_imm256_510,
516 GIPFP_I64_Predicate_imm32,
517 GIPFP_I64_Predicate_imm8,
518 GIPFP_I64_Predicate_imm8_255,
519 GIPFP_I64_Predicate_imm8_or_16,
520 GIPFP_I64_Predicate_imm_11b,
521 GIPFP_I64_Predicate_imm_12b,
522 GIPFP_I64_Predicate_imm_13b,
523 GIPFP_I64_Predicate_imm_3b,
524 GIPFP_I64_Predicate_imm_4b,
525 GIPFP_I64_Predicate_imm_6b,
526 GIPFP_I64_Predicate_imm_7b,
527 GIPFP_I64_Predicate_imm_9b,
528 GIPFP_I64_Predicate_imm_even,
529 GIPFP_I64_Predicate_imm_odd,
530 GIPFP_I64_Predicate_long_shift,
531 GIPFP_I64_Predicate_mod_imm,
532 GIPFP_I64_Predicate_pkh_asr_amt,
533 GIPFP_I64_Predicate_pkh_lsl_amt,
534 GIPFP_I64_Predicate_shr_imm16,
535 GIPFP_I64_Predicate_shr_imm32,
536 GIPFP_I64_Predicate_shr_imm64,
537 GIPFP_I64_Predicate_shr_imm8,
538 GIPFP_I64_Predicate_t2_so_imm,
539 GIPFP_I64_Predicate_t2_so_imm_neg,
540};
541bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
542 switch (PredicateID) {
543 case GIPFP_I64_Predicate_VectorIndex16: {
544
545 return ((uint64_t)Imm) < 4;
546
547 llvm_unreachable("ImmediateCode should have returned");
548 return false;
549 }
550 case GIPFP_I64_Predicate_VectorIndex32: {
551
552 return ((uint64_t)Imm) < 2;
553
554 llvm_unreachable("ImmediateCode should have returned");
555 return false;
556 }
557 case GIPFP_I64_Predicate_VectorIndex64: {
558
559 return ((uint64_t)Imm) < 1;
560
561 llvm_unreachable("ImmediateCode should have returned");
562 return false;
563 }
564 case GIPFP_I64_Predicate_VectorIndex8: {
565
566 return ((uint64_t)Imm) < 8;
567
568 llvm_unreachable("ImmediateCode should have returned");
569 return false;
570 }
571 case GIPFP_I64_Predicate_asr_imm: {
572 return Imm > 0 && Imm <= 32;
573 llvm_unreachable("ImmediateCode should have returned");
574 return false;
575 }
576 case GIPFP_I64_Predicate_imm0_15: {
577
578 return Imm >= 0 && Imm < 16;
579
580 llvm_unreachable("ImmediateCode should have returned");
581 return false;
582 }
583 case GIPFP_I64_Predicate_imm0_239: {
584 return Imm >= 0 && Imm < 240;
585 llvm_unreachable("ImmediateCode should have returned");
586 return false;
587 }
588 case GIPFP_I64_Predicate_imm0_255: {
589 return Imm >= 0 && Imm < 256;
590 llvm_unreachable("ImmediateCode should have returned");
591 return false;
592 }
593 case GIPFP_I64_Predicate_imm0_31: {
594
595 return Imm >= 0 && Imm < 32;
596
597 llvm_unreachable("ImmediateCode should have returned");
598 return false;
599 }
600 case GIPFP_I64_Predicate_imm0_32: {
601
602 return Imm >= 0 && Imm < 33;
603
604 llvm_unreachable("ImmediateCode should have returned");
605 return false;
606 }
607 case GIPFP_I64_Predicate_imm0_4095: {
608
609 return Imm >= 0 && Imm < 4096;
610
611 llvm_unreachable("ImmediateCode should have returned");
612 return false;
613 }
614 case GIPFP_I64_Predicate_imm0_63: {
615
616 return Imm >= 0 && Imm < 64;
617
618 llvm_unreachable("ImmediateCode should have returned");
619 return false;
620 }
621 case GIPFP_I64_Predicate_imm0_65535: {
622
623 return Imm >= 0 && Imm < 65536;
624
625 llvm_unreachable("ImmediateCode should have returned");
626 return false;
627 }
628 case GIPFP_I64_Predicate_imm0_65535_neg: {
629
630 return -Imm >= 0 && -Imm < 65536;
631
632 llvm_unreachable("ImmediateCode should have returned");
633 return false;
634 }
635 case GIPFP_I64_Predicate_imm0_7: {
636
637 return Imm >= 0 && Imm < 8;
638
639 llvm_unreachable("ImmediateCode should have returned");
640 return false;
641 }
642 case GIPFP_I64_Predicate_imm16: {
643 return Imm == 16;
644 llvm_unreachable("ImmediateCode should have returned");
645 return false;
646 }
647 case GIPFP_I64_Predicate_imm16_31: {
648
649 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
650
651 llvm_unreachable("ImmediateCode should have returned");
652 return false;
653 }
654 case GIPFP_I64_Predicate_imm1_15: {
655 return Imm > 0 && Imm < 16;
656 llvm_unreachable("ImmediateCode should have returned");
657 return false;
658 }
659 case GIPFP_I64_Predicate_imm1_16: {
660
661 return Imm > 0 && Imm <= 16;
662
663 llvm_unreachable("ImmediateCode should have returned");
664 return false;
665 }
666 case GIPFP_I64_Predicate_imm1_31: {
667 return Imm > 0 && Imm < 32;
668 llvm_unreachable("ImmediateCode should have returned");
669 return false;
670 }
671 case GIPFP_I64_Predicate_imm1_7: {
672 return Imm > 0 && Imm < 8;
673 llvm_unreachable("ImmediateCode should have returned");
674 return false;
675 }
676 case GIPFP_I64_Predicate_imm24b: {
677
678 return Imm >= 0 && Imm <= 0xffffff;
679
680 llvm_unreachable("ImmediateCode should have returned");
681 return false;
682 }
683 case GIPFP_I64_Predicate_imm256_510: {
684
685 return Imm >= 256 && Imm < 511;
686
687 llvm_unreachable("ImmediateCode should have returned");
688 return false;
689 }
690 case GIPFP_I64_Predicate_imm32: {
691 return Imm == 32;
692 llvm_unreachable("ImmediateCode should have returned");
693 return false;
694 }
695 case GIPFP_I64_Predicate_imm8: {
696 return Imm == 8;
697 llvm_unreachable("ImmediateCode should have returned");
698 return false;
699 }
700 case GIPFP_I64_Predicate_imm8_255: {
701
702 return Imm >= 8 && Imm < 256;
703
704 llvm_unreachable("ImmediateCode should have returned");
705 return false;
706 }
707 case GIPFP_I64_Predicate_imm8_or_16: {
708 return Imm == 8 || Imm == 16;
709 llvm_unreachable("ImmediateCode should have returned");
710 return false;
711 }
712 case GIPFP_I64_Predicate_imm_11b: {
713 { return Imm >= 0 && Imm < (1 << 11); }
714 llvm_unreachable("ImmediateCode should have returned");
715 return false;
716 }
717 case GIPFP_I64_Predicate_imm_12b: {
718 { return Imm >= 0 && Imm < (1 << 12); }
719 llvm_unreachable("ImmediateCode should have returned");
720 return false;
721 }
722 case GIPFP_I64_Predicate_imm_13b: {
723 { return Imm >= 0 && Imm < (1 << 13); }
724 llvm_unreachable("ImmediateCode should have returned");
725 return false;
726 }
727 case GIPFP_I64_Predicate_imm_3b: {
728 { return Imm >= 0 && Imm < (1 << 3); }
729 llvm_unreachable("ImmediateCode should have returned");
730 return false;
731 }
732 case GIPFP_I64_Predicate_imm_4b: {
733 { return Imm >= 0 && Imm < (1 << 4); }
734 llvm_unreachable("ImmediateCode should have returned");
735 return false;
736 }
737 case GIPFP_I64_Predicate_imm_6b: {
738 { return Imm >= 0 && Imm < (1 << 6); }
739 llvm_unreachable("ImmediateCode should have returned");
740 return false;
741 }
742 case GIPFP_I64_Predicate_imm_7b: {
743 { return Imm >= 0 && Imm < (1 << 7); }
744 llvm_unreachable("ImmediateCode should have returned");
745 return false;
746 }
747 case GIPFP_I64_Predicate_imm_9b: {
748 { return Imm >= 0 && Imm < (1 << 9); }
749 llvm_unreachable("ImmediateCode should have returned");
750 return false;
751 }
752 case GIPFP_I64_Predicate_imm_even: {
753 return (Imm & 1) == 0;
754 llvm_unreachable("ImmediateCode should have returned");
755 return false;
756 }
757 case GIPFP_I64_Predicate_imm_odd: {
758 return (Imm & 1) == 1;
759 llvm_unreachable("ImmediateCode should have returned");
760 return false;
761 }
762 case GIPFP_I64_Predicate_long_shift: {
763 return Imm > 0 && Imm <= 32;
764 llvm_unreachable("ImmediateCode should have returned");
765 return false;
766 }
767 case GIPFP_I64_Predicate_mod_imm: {
768
769 return ARM_AM::getSOImmVal(Imm) != -1;
770
771 llvm_unreachable("ImmediateCode should have returned");
772 return false;
773 }
774 case GIPFP_I64_Predicate_pkh_asr_amt: {
775 return Imm > 0 && Imm <= 32;
776 llvm_unreachable("ImmediateCode should have returned");
777 return false;
778 }
779 case GIPFP_I64_Predicate_pkh_lsl_amt: {
780 return Imm >= 0 && Imm < 32;
781 llvm_unreachable("ImmediateCode should have returned");
782 return false;
783 }
784 case GIPFP_I64_Predicate_shr_imm16: {
785 return Imm > 0 && Imm <= 16;
786 llvm_unreachable("ImmediateCode should have returned");
787 return false;
788 }
789 case GIPFP_I64_Predicate_shr_imm32: {
790 return Imm > 0 && Imm <= 32;
791 llvm_unreachable("ImmediateCode should have returned");
792 return false;
793 }
794 case GIPFP_I64_Predicate_shr_imm64: {
795 return Imm > 0 && Imm <= 64;
796 llvm_unreachable("ImmediateCode should have returned");
797 return false;
798 }
799 case GIPFP_I64_Predicate_shr_imm8: {
800 return Imm > 0 && Imm <= 8;
801 llvm_unreachable("ImmediateCode should have returned");
802 return false;
803 }
804 case GIPFP_I64_Predicate_t2_so_imm: {
805
806 return ARM_AM::getT2SOImmVal(Imm) != -1;
807
808 llvm_unreachable("ImmediateCode should have returned");
809 return false;
810 }
811 case GIPFP_I64_Predicate_t2_so_imm_neg: {
812
813 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
814
815 llvm_unreachable("ImmediateCode should have returned");
816 return false;
817 }
818 }
819 llvm_unreachable("Unknown predicate");
820 return false;
821}
822bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
823 llvm_unreachable("Unknown predicate");
824 return false;
825}
826// PatFrag predicates.
827enum {
828 GIPFP_APInt_Predicate_arm_i32imm = GIPFP_APInt_Invalid + 1,
829};
830bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
831 switch (PredicateID) {
832 case GIPFP_APInt_Predicate_arm_i32imm: {
833
834 if (Subtarget->useMovt())
835 return true;
836 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
837 return true;
838 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
839
840 llvm_unreachable("ImmediateCode should have returned");
841 return false;
842 }
843 }
844 llvm_unreachable("Unknown predicate");
845 return false;
846}
847// PatFrag predicates.
848enum {
849 GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
850 GIPFP_MI_Predicate_vfp_f32imm,
851 GIPFP_MI_Predicate_vfp_f64imm,
852};
853bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const {
854 const MachineFunction &MF = *MI.getParent()->getParent();
855 const MachineRegisterInfo &MRI = MF.getRegInfo();
856 (void)MRI;
857 switch (PredicateID) {
858 case GIPFP_MI_Predicate_bf_inv_mask_imm: {
859
860 // There's better methods of implementing this check. IntImmLeaf<> would be
861 // equivalent and have less boilerplate but we need a test for C++
862 // predicates and this one causes new rules to be imported into GlobalISel
863 // without requiring additional features first.
864 const auto &MO = MI.getOperand(1);
865 if (!MO.isCImm())
866 return false;
867 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
868
869 llvm_unreachable("GISelPredicateCode should have returned");
870 return false;
871 }
872 case GIPFP_MI_Predicate_vfp_f32imm: {
873
874 const auto &MO = MI.getOperand(1);
875 if (!MO.isFPImm())
876 return false;
877 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
878
879 llvm_unreachable("GISelPredicateCode should have returned");
880 return false;
881 }
882 case GIPFP_MI_Predicate_vfp_f64imm: {
883
884 const auto &MO = MI.getOperand(1);
885 if (!MO.isFPImm())
886 return false;
887 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
888
889 llvm_unreachable("GISelPredicateCode should have returned");
890 return false;
891 }
892 }
893 llvm_unreachable("Unknown predicate");
894 return false;
895}
896
897ARMInstructionSelector::ComplexMatcherMemFn
898ARMInstructionSelector::ComplexPredicateFns[] = {
899 nullptr, // GICP_Invalid
900};
901
902// Custom renderers.
903enum {
904 GICR_Invalid,
905 GICR_renderVFPF32Imm,
906 GICR_renderVFPF64Imm,
907};
908ARMInstructionSelector::CustomRendererFn
909ARMInstructionSelector::CustomRenderers[] = {
910 nullptr, // GICR_Invalid
911 &ARMInstructionSelector::renderVFPF32Imm, // gi_vfp_f32imm
912 &ARMInstructionSelector::renderVFPF64Imm, // gi_vfp_f64imm
913};
914
915bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
916 MachineFunction &MF = *I.getParent()->getParent();
917 MachineRegisterInfo &MRI = MF.getRegInfo();
918 const PredicateBitset AvailableFeatures = getAvailableFeatures();
919 NewMIVector OutMIs;
920 State.MIs.clear();
921 State.MIs.push_back(&I);
922
923 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
924 return true;
925 }
926
927 return false;
928}
929
930const int64_t *ARMInstructionSelector::getMatchTable() const {
931 constexpr static int64_t MatchTable0[] = {
932 GIM_SwitchOpcode, /*MI*/0, /*[*/39, 196, /*)*//*default:*//*Label 59*/ 124272,
933 /*TargetOpcode::G_ADD*//*Label 0*/ 162,
934 /*TargetOpcode::G_SUB*//*Label 1*/ 8357,
935 /*TargetOpcode::G_MUL*//*Label 2*/ 11385,
936 /*TargetOpcode::G_SDIV*//*Label 3*/ 12217,
937 /*TargetOpcode::G_UDIV*//*Label 4*/ 12319, 0, 0,
938 /*TargetOpcode::G_AND*//*Label 5*/ 12421,
939 /*TargetOpcode::G_OR*//*Label 6*/ 14764,
940 /*TargetOpcode::G_XOR*//*Label 7*/ 19587, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
941 /*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 20688, 0, 0,
942 /*TargetOpcode::G_BITCAST*//*Label 9*/ 21082, 0,
943 /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 31847,
944 /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 32094, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
945 /*TargetOpcode::G_INTRINSIC*//*Label 12*/ 32293,
946 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 13*/ 91094,
947 /*TargetOpcode::G_ANYEXT*//*Label 14*/ 99539,
948 /*TargetOpcode::G_TRUNC*//*Label 15*/ 99674,
949 /*TargetOpcode::G_CONSTANT*//*Label 16*/ 99809,
950 /*TargetOpcode::G_FCONSTANT*//*Label 17*/ 100006, 0, 0,
951 /*TargetOpcode::G_SEXT*//*Label 18*/ 100085, 0,
952 /*TargetOpcode::G_ZEXT*//*Label 19*/ 100220,
953 /*TargetOpcode::G_SHL*//*Label 20*/ 100742,
954 /*TargetOpcode::G_LSHR*//*Label 21*/ 100851,
955 /*TargetOpcode::G_ASHR*//*Label 22*/ 100911, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
956 /*TargetOpcode::G_SMULH*//*Label 23*/ 101129,
957 /*TargetOpcode::G_UADDSAT*//*Label 24*/ 101231,
958 /*TargetOpcode::G_SADDSAT*//*Label 25*/ 101847,
959 /*TargetOpcode::G_USUBSAT*//*Label 26*/ 103691,
960 /*TargetOpcode::G_SSUBSAT*//*Label 27*/ 104307, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
961 /*TargetOpcode::G_FADD*//*Label 28*/ 105579,
962 /*TargetOpcode::G_FSUB*//*Label 29*/ 107716,
963 /*TargetOpcode::G_FMUL*//*Label 30*/ 109265,
964 /*TargetOpcode::G_FMA*//*Label 31*/ 110194, 0,
965 /*TargetOpcode::G_FDIV*//*Label 32*/ 111894, 0, 0, 0, 0, 0, 0, 0, 0,
966 /*TargetOpcode::G_FNEG*//*Label 33*/ 112060,
967 /*TargetOpcode::G_FPEXT*//*Label 34*/ 113377,
968 /*TargetOpcode::G_FPTRUNC*//*Label 35*/ 113537,
969 /*TargetOpcode::G_FPTOSI*//*Label 36*/ 113701,
970 /*TargetOpcode::G_FPTOUI*//*Label 37*/ 114923,
971 /*TargetOpcode::G_SITOFP*//*Label 38*/ 116145,
972 /*TargetOpcode::G_UITOFP*//*Label 39*/ 116718,
973 /*TargetOpcode::G_FABS*//*Label 40*/ 117291, 0, 0,
974 /*TargetOpcode::G_FMINNUM*//*Label 41*/ 117882,
975 /*TargetOpcode::G_FMAXNUM*//*Label 42*/ 118385, 0, 0, 0, 0, 0, 0,
976 /*TargetOpcode::G_SMIN*//*Label 43*/ 118888,
977 /*TargetOpcode::G_SMAX*//*Label 44*/ 119399,
978 /*TargetOpcode::G_UMIN*//*Label 45*/ 119910,
979 /*TargetOpcode::G_UMAX*//*Label 46*/ 120763,
980 /*TargetOpcode::G_ABS*//*Label 47*/ 121616,
981 /*TargetOpcode::G_BR*//*Label 48*/ 122045, 0, 0,
982 /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 49*/ 122109, 0, 0, 0,
983 /*TargetOpcode::G_CTLZ*//*Label 50*/ 122190, 0,
984 /*TargetOpcode::G_CTPOP*//*Label 51*/ 122685,
985 /*TargetOpcode::G_BSWAP*//*Label 52*/ 122777,
986 /*TargetOpcode::G_BITREVERSE*//*Label 53*/ 123016,
987 /*TargetOpcode::G_FCEIL*//*Label 54*/ 123367, 0, 0,
988 /*TargetOpcode::G_FSQRT*//*Label 55*/ 123566,
989 /*TargetOpcode::G_FFLOOR*//*Label 56*/ 123696,
990 /*TargetOpcode::G_FRINT*//*Label 57*/ 123895,
991 /*TargetOpcode::G_FNEARBYINT*//*Label 58*/ 124142,
992 // Label 0: @162
993 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 69*/ 8356,
994 /*GILLT_s32*//*Label 60*/ 182,
995 /*GILLT_s64*//*Label 61*/ 2165,
996 /*GILLT_v2s32*//*Label 62*/ 2217,
997 /*GILLT_v2s64*//*Label 63*/ 2684, 0,
998 /*GILLT_v4s16*//*Label 64*/ 3712,
999 /*GILLT_v4s32*//*Label 65*/ 4179, 0, 0,
1000 /*GILLT_v8s8*//*Label 66*/ 5760,
1001 /*GILLT_v8s16*//*Label 67*/ 6227, 0, 0,
1002 /*GILLT_v16s8*//*Label 68*/ 7808,
1003 // Label 60: @182
1004 GIM_Try, /*On fail goto*//*Label 70*/ 2164,
1005 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1006 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1007 GIM_Try, /*On fail goto*//*Label 71*/ 259, // Rule ID 5543 //
1008 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1011 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1012 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1013 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1014 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1015 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1017 GIM_CheckIsSafeToFold, /*InsnID*/1,
1018 // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
1020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1023 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1024 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1025 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1026 GIR_EraseFromParent, /*InsnID*/0,
1027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1028 // GIR_Coverage, 5543,
1029 GIR_Done,
1030 // Label 71: @259
1031 GIM_Try, /*On fail goto*//*Label 72*/ 326, // Rule ID 5544 //
1032 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1034 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1035 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1036 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1037 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1038 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1039 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1041 GIM_CheckIsSafeToFold, /*InsnID*/1,
1042 // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
1044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1047 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1048 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1049 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1050 GIR_EraseFromParent, /*InsnID*/0,
1051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1052 // GIR_Coverage, 5544,
1053 GIR_Done,
1054 // Label 72: @326
1055 GIM_Try, /*On fail goto*//*Label 73*/ 393, // Rule ID 5578 //
1056 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1058 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1059 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1060 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1061 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1062 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1063 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1065 GIM_CheckIsSafeToFold, /*InsnID*/1,
1066 // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
1068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1071 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1072 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1073 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1074 GIR_EraseFromParent, /*InsnID*/0,
1075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1076 // GIR_Coverage, 5578,
1077 GIR_Done,
1078 // Label 73: @393
1079 GIM_Try, /*On fail goto*//*Label 74*/ 460, // Rule ID 5579 //
1080 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1082 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1083 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1084 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1085 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1086 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1087 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1089 GIM_CheckIsSafeToFold, /*InsnID*/1,
1090 // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1095 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1096 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1097 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1098 GIR_EraseFromParent, /*InsnID*/0,
1099 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1100 // GIR_Coverage, 5579,
1101 GIR_Done,
1102 // Label 74: @460
1103 GIM_Try, /*On fail goto*//*Label 75*/ 527, // Rule ID 1999 //
1104 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1107 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1108 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1109 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1110 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1111 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1112 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1113 GIM_CheckIsSafeToFold, /*InsnID*/1,
1114 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
1116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1119 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1120 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1121 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1122 GIR_EraseFromParent, /*InsnID*/0,
1123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1124 // GIR_Coverage, 1999,
1125 GIR_Done,
1126 // Label 75: @527
1127 GIM_Try, /*On fail goto*//*Label 76*/ 594, // Rule ID 2000 //
1128 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
1129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1131 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1132 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1133 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1134 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1135 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1136 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1137 GIM_CheckIsSafeToFold, /*InsnID*/1,
1138 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
1140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1143 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1144 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1145 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1146 GIR_EraseFromParent, /*InsnID*/0,
1147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1148 // GIR_Coverage, 2000,
1149 GIR_Done,
1150 // Label 76: @594
1151 GIM_Try, /*On fail goto*//*Label 77*/ 661, // Rule ID 2217 //
1152 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1155 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1156 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1157 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1158 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1159 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1160 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
1161 GIM_CheckIsSafeToFold, /*InsnID*/1,
1162 // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
1164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1167 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1168 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1169 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1170 GIR_EraseFromParent, /*InsnID*/0,
1171 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1172 // GIR_Coverage, 2217,
1173 GIR_Done,
1174 // Label 77: @661
1175 GIM_Try, /*On fail goto*//*Label 78*/ 728, // Rule ID 2218 //
1176 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
1177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1179 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1180 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
1181 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1182 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1183 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1184 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
1185 GIM_CheckIsSafeToFold, /*InsnID*/1,
1186 // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
1188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1191 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
1192 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1193 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1194 GIR_EraseFromParent, /*InsnID*/0,
1195 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1196 // GIR_Coverage, 2218,
1197 GIR_Done,
1198 // Label 78: @728
1199 GIM_Try, /*On fail goto*//*Label 79*/ 838, // Rule ID 5322 //
1200 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1202 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1203 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1204 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1205 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1206 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1207 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1208 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1209 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1210 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1211 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1212 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1213 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1214 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1215 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1216 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1217 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1219 GIM_CheckIsSafeToFold, /*InsnID*/1,
1220 GIM_CheckIsSafeToFold, /*InsnID*/2,
1221 GIM_CheckIsSafeToFold, /*InsnID*/3,
1222 // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1228 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1229 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1230 GIR_EraseFromParent, /*InsnID*/0,
1231 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1232 // GIR_Coverage, 5322,
1233 GIR_Done,
1234 // Label 79: @838
1235 GIM_Try, /*On fail goto*//*Label 80*/ 948, // Rule ID 5359 //
1236 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1238 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1239 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1240 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1241 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1242 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1243 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1244 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1245 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1246 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1247 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1248 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1249 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1250 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1251 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1252 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1253 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1255 GIM_CheckIsSafeToFold, /*InsnID*/1,
1256 GIM_CheckIsSafeToFold, /*InsnID*/2,
1257 GIM_CheckIsSafeToFold, /*InsnID*/3,
1258 // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1264 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1265 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1266 GIR_EraseFromParent, /*InsnID*/0,
1267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1268 // GIR_Coverage, 5359,
1269 GIR_Done,
1270 // Label 80: @948
1271 GIM_Try, /*On fail goto*//*Label 81*/ 1058, // Rule ID 192 //
1272 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1275 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1276 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1277 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1278 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1279 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1280 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1281 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1282 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1283 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1284 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1285 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1286 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1287 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1288 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1289 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1290 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1291 GIM_CheckIsSafeToFold, /*InsnID*/1,
1292 GIM_CheckIsSafeToFold, /*InsnID*/2,
1293 GIM_CheckIsSafeToFold, /*InsnID*/3,
1294 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1300 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1301 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1302 GIR_EraseFromParent, /*InsnID*/0,
1303 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1304 // GIR_Coverage, 192,
1305 GIR_Done,
1306 // Label 81: @1058
1307 GIM_Try, /*On fail goto*//*Label 82*/ 1168, // Rule ID 528 //
1308 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1311 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1312 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1313 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1314 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1315 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1316 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1317 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1318 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1319 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1320 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1321 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1322 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1323 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1324 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1325 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1326 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1327 GIM_CheckIsSafeToFold, /*InsnID*/1,
1328 GIM_CheckIsSafeToFold, /*InsnID*/2,
1329 GIM_CheckIsSafeToFold, /*InsnID*/3,
1330 // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1336 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1337 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1338 GIR_EraseFromParent, /*InsnID*/0,
1339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1340 // GIR_Coverage, 528,
1341 GIR_Done,
1342 // Label 82: @1168
1343 GIM_Try, /*On fail goto*//*Label 83*/ 1222, // Rule ID 72 //
1344 GIM_CheckFeatures, GIFBS_IsARM,
1345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1347 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1348 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1349 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1350 // MIs[1] Operand 1
1351 // No operand predicates
1352 GIM_CheckIsSafeToFold, /*InsnID*/1,
1353 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1357 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1358 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1359 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1360 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1361 GIR_EraseFromParent, /*InsnID*/0,
1362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1363 // GIR_Coverage, 72,
1364 GIR_Done,
1365 // Label 83: @1222
1366 GIM_Try, /*On fail goto*//*Label 84*/ 1276, // Rule ID 414 //
1367 GIM_CheckFeatures, GIFBS_IsThumb2,
1368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1370 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1371 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1372 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1373 // MIs[1] Operand 1
1374 // No operand predicates
1375 GIM_CheckIsSafeToFold, /*InsnID*/1,
1376 // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1380 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1381 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1382 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1383 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1384 GIR_EraseFromParent, /*InsnID*/0,
1385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1386 // GIR_Coverage, 414,
1387 GIR_Done,
1388 // Label 84: @1276
1389 GIM_Try, /*On fail goto*//*Label 85*/ 1326, // Rule ID 415 //
1390 GIM_CheckFeatures, GIFBS_IsThumb2,
1391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1393 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1394 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1395 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1396 // MIs[1] Operand 1
1397 // No operand predicates
1398 GIM_CheckIsSafeToFold, /*InsnID*/1,
1399 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1403 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1404 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1405 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1406 GIR_EraseFromParent, /*InsnID*/0,
1407 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1408 // GIR_Coverage, 415,
1409 GIR_Done,
1410 // Label 85: @1326
1411 GIM_Try, /*On fail goto*//*Label 86*/ 1398, // Rule ID 171 //
1412 GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1415 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1416 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1417 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1418 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1419 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1421 GIM_CheckIsSafeToFold, /*InsnID*/1,
1422 // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1423 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1428 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1429 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1430 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1431 GIR_EraseFromParent, /*InsnID*/0,
1432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1433 // GIR_Coverage, 171,
1434 GIR_Done,
1435 // Label 86: @1398
1436 GIM_Try, /*On fail goto*//*Label 87*/ 1470, // Rule ID 172 //
1437 GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1439 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1440 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1441 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1442 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1443 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1444 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1446 GIM_CheckIsSafeToFold, /*InsnID*/1,
1447 // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1453 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1454 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1455 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1456 GIR_EraseFromParent, /*InsnID*/0,
1457 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1458 // GIR_Coverage, 172,
1459 GIR_Done,
1460 // Label 87: @1470
1461 GIM_Try, /*On fail goto*//*Label 88*/ 1538, // Rule ID 510 //
1462 GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1464 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1465 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1466 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1467 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1468 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1469 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1471 GIM_CheckIsSafeToFold, /*InsnID*/1,
1472 // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1478 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1479 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1480 GIR_EraseFromParent, /*InsnID*/0,
1481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1482 // GIR_Coverage, 510,
1483 GIR_Done,
1484 // Label 88: @1538
1485 GIM_Try, /*On fail goto*//*Label 89*/ 1606, // Rule ID 180 //
1486 GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1488 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1489 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1490 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1491 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1492 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1493 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1495 GIM_CheckIsSafeToFold, /*InsnID*/1,
1496 // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1502 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1503 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1504 GIR_EraseFromParent, /*InsnID*/0,
1505 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1506 // GIR_Coverage, 180,
1507 GIR_Done,
1508 // Label 89: @1606
1509 GIM_Try, /*On fail goto*//*Label 90*/ 1674, // Rule ID 516 //
1510 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1512 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1513 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1514 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1515 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1516 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1517 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1519 GIM_CheckIsSafeToFold, /*InsnID*/1,
1520 // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1526 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1527 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1528 GIR_EraseFromParent, /*InsnID*/0,
1529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1530 // GIR_Coverage, 516,
1531 GIR_Done,
1532 // Label 90: @1674
1533 GIM_Try, /*On fail goto*//*Label 91*/ 1746, // Rule ID 5316 //
1534 GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1537 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1538 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1539 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1540 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1541 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1542 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1543 GIM_CheckIsSafeToFold, /*InsnID*/1,
1544 // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1550 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1551 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1552 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1553 GIR_EraseFromParent, /*InsnID*/0,
1554 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1555 // GIR_Coverage, 5316,
1556 GIR_Done,
1557 // Label 91: @1746
1558 GIM_Try, /*On fail goto*//*Label 92*/ 1818, // Rule ID 5317 //
1559 GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1562 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1563 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1564 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1565 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1566 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1567 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1568 GIM_CheckIsSafeToFold, /*InsnID*/1,
1569 // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1575 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1576 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1577 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1578 GIR_EraseFromParent, /*InsnID*/0,
1579 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1580 // GIR_Coverage, 5317,
1581 GIR_Done,
1582 // Label 92: @1818
1583 GIM_Try, /*On fail goto*//*Label 93*/ 1886, // Rule ID 5354 //
1584 GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1587 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1588 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1589 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1590 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1591 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1592 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1593 GIM_CheckIsSafeToFold, /*InsnID*/1,
1594 // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1600 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1601 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1602 GIR_EraseFromParent, /*InsnID*/0,
1603 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1604 // GIR_Coverage, 5354,
1605 GIR_Done,
1606 // Label 93: @1886
1607 GIM_Try, /*On fail goto*//*Label 94*/ 1954, // Rule ID 5318 //
1608 GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1611 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1612 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1613 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1614 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1615 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1617 GIM_CheckIsSafeToFold, /*InsnID*/1,
1618 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
1620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1624 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1625 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1626 GIR_EraseFromParent, /*InsnID*/0,
1627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1628 // GIR_Coverage, 5318,
1629 GIR_Done,
1630 // Label 94: @1954
1631 GIM_Try, /*On fail goto*//*Label 95*/ 2022, // Rule ID 5355 //
1632 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1635 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1636 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
1637 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1638 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1639 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1640 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1641 GIM_CheckIsSafeToFold, /*InsnID*/1,
1642 // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
1644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
1646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1648 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1649 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1650 GIR_EraseFromParent, /*InsnID*/0,
1651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1652 // GIR_Coverage, 5355,
1653 GIR_Done,
1654 // Label 95: @2022
1655 GIM_Try, /*On fail goto*//*Label 96*/ 2069, // Rule ID 73 //
1656 GIM_CheckFeatures, GIFBS_IsARM,
1657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1660 // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1665 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1666 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1667 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1668 GIR_EraseFromParent, /*InsnID*/0,
1669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1670 // GIR_Coverage, 73,
1671 GIR_Done,
1672 // Label 96: @2069
1673 GIM_Try, /*On fail goto*//*Label 97*/ 2116, // Rule ID 416 //
1674 GIM_CheckFeatures, GIFBS_IsThumb2,
1675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1678 // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1683 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1684 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1685 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1686 GIR_EraseFromParent, /*InsnID*/0,
1687 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1688 // GIR_Coverage, 416,
1689 GIR_Done,
1690 // Label 97: @2116
1691 GIM_Try, /*On fail goto*//*Label 98*/ 2163, // Rule ID 5336 //
1692 GIM_CheckFeatures, GIFBS_IsThumb2,
1693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1696 // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1701 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1702 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1703 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1704 GIR_EraseFromParent, /*InsnID*/0,
1705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1706 // GIR_Coverage, 5336,
1707 GIR_Done,
1708 // Label 98: @2163
1709 GIM_Reject,
1710 // Label 70: @2164
1711 GIM_Reject,
1712 // Label 61: @2165
1713 GIM_Try, /*On fail goto*//*Label 99*/ 2216, // Rule ID 776 //
1714 GIM_CheckFeatures, GIFBS_HasNEON,
1715 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1720 // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1725 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1726 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1727 GIR_EraseFromParent, /*InsnID*/0,
1728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1729 // GIR_Coverage, 776,
1730 GIR_Done,
1731 // Label 99: @2216
1732 GIM_Reject,
1733 // Label 62: @2217
1734 GIM_Try, /*On fail goto*//*Label 100*/ 2683,
1735 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1738 GIM_Try, /*On fail goto*//*Label 101*/ 2302, // Rule ID 5475 //
1739 GIM_CheckFeatures, GIFBS_HasNEON,
1740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1741 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1742 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1743 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1744 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1745 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1746 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1749 GIM_CheckIsSafeToFold, /*InsnID*/1,
1750 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1756 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1757 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1758 GIR_EraseFromParent, /*InsnID*/0,
1759 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1760 // GIR_Coverage, 5475,
1761 GIR_Done,
1762 // Label 101: @2302
1763 GIM_Try, /*On fail goto*//*Label 102*/ 2373, // Rule ID 5481 //
1764 GIM_CheckFeatures, GIFBS_HasNEON,
1765 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1766 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1767 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1768 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1769 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1770 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1771 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1772 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1774 GIM_CheckIsSafeToFold, /*InsnID*/1,
1775 // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1781 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1782 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1783 GIR_EraseFromParent, /*InsnID*/0,
1784 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1785 // GIR_Coverage, 5481,
1786 GIR_Done,
1787 // Label 102: @2373
1788 GIM_Try, /*On fail goto*//*Label 103*/ 2444, // Rule ID 1197 //
1789 GIM_CheckFeatures, GIFBS_HasNEON,
1790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1791 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1792 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1793 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1794 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1795 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1796 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1797 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1798 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1799 GIM_CheckIsSafeToFold, /*InsnID*/1,
1800 // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1806 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1807 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1808 GIR_EraseFromParent, /*InsnID*/0,
1809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1810 // GIR_Coverage, 1197,
1811 GIR_Done,
1812 // Label 103: @2444
1813 GIM_Try, /*On fail goto*//*Label 104*/ 2515, // Rule ID 1203 //
1814 GIM_CheckFeatures, GIFBS_HasNEON,
1815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1817 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1818 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1819 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1820 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1821 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1822 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1823 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1824 GIM_CheckIsSafeToFold, /*InsnID*/1,
1825 // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1831 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1832 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1833 GIR_EraseFromParent, /*InsnID*/0,
1834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1835 // GIR_Coverage, 1203,
1836 GIR_Done,
1837 // Label 104: @2515
1838 GIM_Try, /*On fail goto*//*Label 105*/ 2579, // Rule ID 5405 //
1839 GIM_CheckFeatures, GIFBS_HasNEON,
1840 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1841 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1842 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1843 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1844 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1845 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1847 GIM_CheckIsSafeToFold, /*InsnID*/1,
1848 // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1854 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1855 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1856 GIR_EraseFromParent, /*InsnID*/0,
1857 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1858 // GIR_Coverage, 5405,
1859 GIR_Done,
1860 // Label 105: @2579
1861 GIM_Try, /*On fail goto*//*Label 106*/ 2643, // Rule ID 903 //
1862 GIM_CheckFeatures, GIFBS_HasNEON,
1863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1864 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1865 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1866 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1867 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1868 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1869 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1870 GIM_CheckIsSafeToFold, /*InsnID*/1,
1871 // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1872 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1877 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1878 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1879 GIR_EraseFromParent, /*InsnID*/0,
1880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1881 // GIR_Coverage, 903,
1882 GIR_Done,
1883 // Label 106: @2643
1884 GIM_Try, /*On fail goto*//*Label 107*/ 2682, // Rule ID 772 //
1885 GIM_CheckFeatures, GIFBS_HasNEON,
1886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1888 // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1893 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1894 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1895 GIR_EraseFromParent, /*InsnID*/0,
1896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1897 // GIR_Coverage, 772,
1898 GIR_Done,
1899 // Label 107: @2682
1900 GIM_Reject,
1901 // Label 100: @2683
1902 GIM_Reject,
1903 // Label 63: @2684
1904 GIM_Try, /*On fail goto*//*Label 108*/ 3711,
1905 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1906 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1908 GIM_Try, /*On fail goto*//*Label 109*/ 2782, // Rule ID 5487 //
1909 GIM_CheckFeatures, GIFBS_HasNEON,
1910 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1911 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1912 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1913 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1914 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1915 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1916 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1917 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1918 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1919 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1920 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1922 GIM_CheckIsSafeToFold, /*InsnID*/1,
1923 GIM_CheckIsSafeToFold, /*InsnID*/2,
1924 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1930 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1931 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1932 GIR_EraseFromParent, /*InsnID*/0,
1933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1934 // GIR_Coverage, 5487,
1935 GIR_Done,
1936 // Label 109: @2782
1937 GIM_Try, /*On fail goto*//*Label 110*/ 2866, // Rule ID 5490 //
1938 GIM_CheckFeatures, GIFBS_HasNEON,
1939 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1940 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1941 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1942 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1943 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1944 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1945 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1946 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1947 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1948 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1949 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1951 GIM_CheckIsSafeToFold, /*InsnID*/1,
1952 GIM_CheckIsSafeToFold, /*InsnID*/2,
1953 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1959 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1960 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1961 GIR_EraseFromParent, /*InsnID*/0,
1962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1963 // GIR_Coverage, 5490,
1964 GIR_Done,
1965 // Label 110: @2866
1966 GIM_Try, /*On fail goto*//*Label 111*/ 2950, // Rule ID 1209 //
1967 GIM_CheckFeatures, GIFBS_HasNEON,
1968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1969 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1970 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1971 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1972 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1973 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1974 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1975 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1976 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1977 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1978 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1979 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1980 GIM_CheckIsSafeToFold, /*InsnID*/1,
1981 GIM_CheckIsSafeToFold, /*InsnID*/2,
1982 // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1988 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1989 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
1990 GIR_EraseFromParent, /*InsnID*/0,
1991 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1992 // GIR_Coverage, 1209,
1993 GIR_Done,
1994 // Label 111: @2950
1995 GIM_Try, /*On fail goto*//*Label 112*/ 3034, // Rule ID 1212 //
1996 GIM_CheckFeatures, GIFBS_HasNEON,
1997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1998 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1999 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2000 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2001 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2002 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2003 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2004 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2005 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
2006 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
2007 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2008 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2009 GIM_CheckIsSafeToFold, /*InsnID*/1,
2010 GIM_CheckIsSafeToFold, /*InsnID*/2,
2011 // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
2013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2017 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2018 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2019 GIR_EraseFromParent, /*InsnID*/0,
2020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2021 // GIR_Coverage, 1212,
2022 GIR_Done,
2023 // Label 112: @3034
2024 GIM_Try, /*On fail goto*//*Label 113*/ 3099, // Rule ID 796 //
2025 GIM_CheckFeatures, GIFBS_HasNEON,
2026 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2027 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2028 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2029 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2030 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2031 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2032 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2033 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2034 GIM_CheckIsSafeToFold, /*InsnID*/1,
2035 GIM_CheckIsSafeToFold, /*InsnID*/2,
2036 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2037 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2041 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2042 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2043 GIR_EraseFromParent, /*InsnID*/0,
2044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2045 // GIR_Coverage, 796,
2046 GIR_Done,
2047 // Label 113: @3099
2048 GIM_Try, /*On fail goto*//*Label 114*/ 3164, // Rule ID 795 //
2049 GIM_CheckFeatures, GIFBS_HasNEON,
2050 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2051 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2052 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2053 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2054 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2055 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2056 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2057 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2058 GIM_CheckIsSafeToFold, /*InsnID*/1,
2059 GIM_CheckIsSafeToFold, /*InsnID*/2,
2060 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2065 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2066 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2067 GIR_EraseFromParent, /*InsnID*/0,
2068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2069 // GIR_Coverage, 795,
2070 GIR_Done,
2071 // Label 114: @3164
2072 GIM_Try, /*On fail goto*//*Label 115*/ 3229, // Rule ID 784 //
2073 GIM_CheckFeatures, GIFBS_HasNEON,
2074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2075 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2076 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2077 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2078 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2079 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2080 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2081 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2082 GIM_CheckIsSafeToFold, /*InsnID*/1,
2083 GIM_CheckIsSafeToFold, /*InsnID*/2,
2084 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
2086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2089 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2090 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2091 GIR_EraseFromParent, /*InsnID*/0,
2092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2093 // GIR_Coverage, 784,
2094 GIR_Done,
2095 // Label 115: @3229
2096 GIM_Try, /*On fail goto*//*Label 116*/ 3294, // Rule ID 794 //
2097 GIM_CheckFeatures, GIFBS_HasNEON,
2098 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2099 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2100 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2101 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2102 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2103 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2104 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2105 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2106 GIM_CheckIsSafeToFold, /*InsnID*/1,
2107 GIM_CheckIsSafeToFold, /*InsnID*/2,
2108 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2113 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2114 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2115 GIR_EraseFromParent, /*InsnID*/0,
2116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2117 // GIR_Coverage, 794,
2118 GIR_Done,
2119 // Label 116: @3294
2120 GIM_Try, /*On fail goto*//*Label 117*/ 3359, // Rule ID 793 //
2121 GIM_CheckFeatures, GIFBS_HasNEON,
2122 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2123 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2124 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2125 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2126 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2127 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2128 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
2129 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2130 GIM_CheckIsSafeToFold, /*InsnID*/1,
2131 GIM_CheckIsSafeToFold, /*InsnID*/2,
2132 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
2134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2137 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2138 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2139 GIR_EraseFromParent, /*InsnID*/0,
2140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2141 // GIR_Coverage, 793,
2142 GIR_Done,
2143 // Label 117: @3359
2144 GIM_Try, /*On fail goto*//*Label 118*/ 3411, // Rule ID 5384 //
2145 GIM_CheckFeatures, GIFBS_HasNEON,
2146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2147 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2148 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2149 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2151 GIM_CheckIsSafeToFold, /*InsnID*/1,
2152 // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2157 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2158 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2159 GIR_EraseFromParent, /*InsnID*/0,
2160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2161 // GIR_Coverage, 5384,
2162 GIR_Done,
2163 // Label 118: @3411
2164 GIM_Try, /*On fail goto*//*Label 119*/ 3463, // Rule ID 5378 //
2165 GIM_CheckFeatures, GIFBS_HasNEON,
2166 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2167 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2168 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2169 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2171 GIM_CheckIsSafeToFold, /*InsnID*/1,
2172 // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
2174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2177 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2178 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2179 GIR_EraseFromParent, /*InsnID*/0,
2180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2181 // GIR_Coverage, 5378,
2182 GIR_Done,
2183 // Label 119: @3463
2184 GIM_Try, /*On fail goto*//*Label 120*/ 3515, // Rule ID 5383 //
2185 GIM_CheckFeatures, GIFBS_HasNEON,
2186 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2187 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2188 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2189 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2191 GIM_CheckIsSafeToFold, /*InsnID*/1,
2192 // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2197 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2198 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2199 GIR_EraseFromParent, /*InsnID*/0,
2200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2201 // GIR_Coverage, 5383,
2202 GIR_Done,
2203 // Label 120: @3515
2204 GIM_Try, /*On fail goto*//*Label 121*/ 3567, // Rule ID 805 //
2205 GIM_CheckFeatures, GIFBS_HasNEON,
2206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2207 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2208 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2209 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2210 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2211 GIM_CheckIsSafeToFold, /*InsnID*/1,
2212 // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2217 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2218 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2219 GIR_EraseFromParent, /*InsnID*/0,
2220 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2221 // GIR_Coverage, 805,
2222 GIR_Done,
2223 // Label 121: @3567
2224 GIM_Try, /*On fail goto*//*Label 122*/ 3619, // Rule ID 799 //
2225 GIM_CheckFeatures, GIFBS_HasNEON,
2226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2227 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2228 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2229 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2230 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2231 GIM_CheckIsSafeToFold, /*InsnID*/1,
2232 // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
2234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2237 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2238 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2239 GIR_EraseFromParent, /*InsnID*/0,
2240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2241 // GIR_Coverage, 799,
2242 GIR_Done,
2243 // Label 122: @3619
2244 GIM_Try, /*On fail goto*//*Label 123*/ 3671, // Rule ID 804 //
2245 GIM_CheckFeatures, GIFBS_HasNEON,
2246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2247 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2248 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2249 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2250 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2251 GIM_CheckIsSafeToFold, /*InsnID*/1,
2252 // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
2254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2257 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2258 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2259 GIR_EraseFromParent, /*InsnID*/0,
2260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2261 // GIR_Coverage, 804,
2262 GIR_Done,
2263 // Label 123: @3671
2264 GIM_Try, /*On fail goto*//*Label 124*/ 3710, // Rule ID 777 //
2265 GIM_CheckFeatures, GIFBS_HasNEON,
2266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2268 // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
2269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
2270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2273 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2274 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2275 GIR_EraseFromParent, /*InsnID*/0,
2276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2277 // GIR_Coverage, 777,
2278 GIR_Done,
2279 // Label 124: @3710
2280 GIM_Reject,
2281 // Label 108: @3711
2282 GIM_Reject,
2283 // Label 64: @3712
2284 GIM_Try, /*On fail goto*//*Label 125*/ 4178,
2285 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
2286 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
2287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2288 GIM_Try, /*On fail goto*//*Label 126*/ 3797, // Rule ID 5474 //
2289 GIM_CheckFeatures, GIFBS_HasNEON,
2290 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2291 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2292 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2293 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2294 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2295 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2296 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2297 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2299 GIM_CheckIsSafeToFold, /*InsnID*/1,
2300 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2306 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2307 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2308 GIR_EraseFromParent, /*InsnID*/0,
2309 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2310 // GIR_Coverage, 5474,
2311 GIR_Done,
2312 // Label 126: @3797
2313 GIM_Try, /*On fail goto*//*Label 127*/ 3868, // Rule ID 5480 //
2314 GIM_CheckFeatures, GIFBS_HasNEON,
2315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2316 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2317 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2318 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2319 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2320 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2321 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2322 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2324 GIM_CheckIsSafeToFold, /*InsnID*/1,
2325 // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 2143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2331 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2332 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2333 GIR_EraseFromParent, /*InsnID*/0,
2334 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2335 // GIR_Coverage, 5480,
2336 GIR_Done,
2337 // Label 127: @3868
2338 GIM_Try, /*On fail goto*//*Label 128*/ 3939, // Rule ID 1196 //
2339 GIM_CheckFeatures, GIFBS_HasNEON,
2340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2341 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2342 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2343 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2344 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2345 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2346 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2347 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2348 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2349 GIM_CheckIsSafeToFold, /*InsnID*/1,
2350 // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
2352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2356 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2357 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2358 GIR_EraseFromParent, /*InsnID*/0,
2359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2360 // GIR_Coverage, 1196,
2361 GIR_Done,
2362 // Label 128: @3939
2363 GIM_Try, /*On fail goto*//*Label 129*/ 4010, // Rule ID 1202 //
2364 GIM_CheckFeatures, GIFBS_HasNEON,
2365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2366 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2367 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2368 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2369 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2370 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2371 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
2372 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2373 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2374 GIM_CheckIsSafeToFold, /*InsnID*/1,
2375 // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 2143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
2377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2381 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2382 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2383 GIR_EraseFromParent, /*InsnID*/0,
2384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2385 // GIR_Coverage, 1202,
2386 GIR_Done,
2387 // Label 129: @4010
2388 GIM_Try, /*On fail goto*//*Label 130*/ 4074, // Rule ID 5404 //
2389 GIM_CheckFeatures, GIFBS_HasNEON,
2390 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2391 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2392 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2393 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2394 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2395 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2397 GIM_CheckIsSafeToFold, /*InsnID*/1,
2398 // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2404 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2405 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2406 GIR_EraseFromParent, /*InsnID*/0,
2407 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2408 // GIR_Coverage, 5404,
2409 GIR_Done,
2410 // Label 130: @4074
2411 GIM_Try, /*On fail goto*//*Label 131*/ 4138, // Rule ID 902 //
2412 GIM_CheckFeatures, GIFBS_HasNEON,
2413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2414 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2415 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2416 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2417 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
2418 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2419 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2420 GIM_CheckIsSafeToFold, /*InsnID*/1,
2421 // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
2423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2427 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2428 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2429 GIR_EraseFromParent, /*InsnID*/0,
2430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2431 // GIR_Coverage, 902,
2432 GIR_Done,
2433 // Label 131: @4138
2434 GIM_Try, /*On fail goto*//*Label 132*/ 4177, // Rule ID 771 //
2435 GIM_CheckFeatures, GIFBS_HasNEON,
2436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2438 // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
2440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2443 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2444 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2445 GIR_EraseFromParent, /*InsnID*/0,
2446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2447 // GIR_Coverage, 771,
2448 GIR_Done,
2449 // Label 132: @4177
2450 GIM_Reject,
2451 // Label 125: @4178
2452 GIM_Reject,
2453 // Label 65: @4179
2454 GIM_Try, /*On fail goto*//*Label 133*/ 5759,
2455 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2456 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2457 GIM_Try, /*On fail goto*//*Label 134*/ 4277, // Rule ID 5486 //
2458 GIM_CheckFeatures, GIFBS_HasNEON,
2459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2460 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2461 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2462 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2463 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2464 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2465 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2466 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2467 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2468 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2469 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2470 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2472 GIM_CheckIsSafeToFold, /*InsnID*/1,
2473 GIM_CheckIsSafeToFold, /*InsnID*/2,
2474 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2475 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2480 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2481 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2482 GIR_EraseFromParent, /*InsnID*/0,
2483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2484 // GIR_Coverage, 5486,
2485 GIR_Done,
2486 // Label 134: @4277
2487 GIM_Try, /*On fail goto*//*Label 135*/ 4365, // Rule ID 5489 //
2488 GIM_CheckFeatures, GIFBS_HasNEON,
2489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2490 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2491 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2492 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2493 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2494 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2495 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2496 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2497 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2498 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2499 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2500 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2502 GIM_CheckIsSafeToFold, /*InsnID*/1,
2503 GIM_CheckIsSafeToFold, /*InsnID*/2,
2504 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2510 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2511 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2512 GIR_EraseFromParent, /*InsnID*/0,
2513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2514 // GIR_Coverage, 5489,
2515 GIR_Done,
2516 // Label 135: @4365
2517 GIM_Try, /*On fail goto*//*Label 136*/ 4453, // Rule ID 1208 //
2518 GIM_CheckFeatures, GIFBS_HasNEON,
2519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2521 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2522 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2523 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2524 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2525 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2526 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2527 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2528 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2529 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2530 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2531 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2532 GIM_CheckIsSafeToFold, /*InsnID*/1,
2533 GIM_CheckIsSafeToFold, /*InsnID*/2,
2534 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2535 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2540 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2541 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2542 GIR_EraseFromParent, /*InsnID*/0,
2543 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2544 // GIR_Coverage, 1208,
2545 GIR_Done,
2546 // Label 136: @4453
2547 GIM_Try, /*On fail goto*//*Label 137*/ 4541, // Rule ID 1211 //
2548 GIM_CheckFeatures, GIFBS_HasNEON,
2549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2551 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2552 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2553 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2554 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2555 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2556 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2557 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2558 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2559 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2560 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2561 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2562 GIM_CheckIsSafeToFold, /*InsnID*/1,
2563 GIM_CheckIsSafeToFold, /*InsnID*/2,
2564 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2570 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2571 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2572 GIR_EraseFromParent, /*InsnID*/0,
2573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2574 // GIR_Coverage, 1211,
2575 GIR_Done,
2576 // Label 137: @4541
2577 GIM_Try, /*On fail goto*//*Label 138*/ 4616, // Rule ID 5478 //
2578 GIM_CheckFeatures, GIFBS_HasNEON,
2579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2581 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2582 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2583 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2584 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2585 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2586 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2587 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2589 GIM_CheckIsSafeToFold, /*InsnID*/1,
2590 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2142:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2591 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2596 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2597 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2598 GIR_EraseFromParent, /*InsnID*/0,
2599 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2600 // GIR_Coverage, 5478,
2601 GIR_Done,
2602 // Label 138: @4616
2603 GIM_Try, /*On fail goto*//*Label 139*/ 4691, // Rule ID 5484 //
2604 GIM_CheckFeatures, GIFBS_HasNEON,
2605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2606 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2607 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2608 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2609 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2610 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2611 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2615 GIM_CheckIsSafeToFold, /*InsnID*/1,
2616 // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2143:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2622 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2623 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2624 GIR_EraseFromParent, /*InsnID*/0,
2625 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2626 // GIR_Coverage, 5484,
2627 GIR_Done,
2628 // Label 139: @4691
2629 GIM_Try, /*On fail goto*//*Label 140*/ 4766, // Rule ID 1200 //
2630 GIM_CheckFeatures, GIFBS_HasNEON,
2631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2633 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2634 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2635 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2636 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2637 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2638 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2639 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2640 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2641 GIM_CheckIsSafeToFold, /*InsnID*/1,
2642 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2142:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2648 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2649 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2650 GIR_EraseFromParent, /*InsnID*/0,
2651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2652 // GIR_Coverage, 1200,
2653 GIR_Done,
2654 // Label 140: @4766
2655 GIM_Try, /*On fail goto*//*Label 141*/ 4841, // Rule ID 1206 //
2656 GIM_CheckFeatures, GIFBS_HasNEON,
2657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2659 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2660 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2661 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2662 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2663 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2664 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2665 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2666 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2667 GIM_CheckIsSafeToFold, /*InsnID*/1,
2668 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2143:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2674 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2675 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2676 GIR_EraseFromParent, /*InsnID*/0,
2677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2678 // GIR_Coverage, 1206,
2679 GIR_Done,
2680 // Label 141: @4841
2681 GIM_Try, /*On fail goto*//*Label 142*/ 4910, // Rule ID 792 //
2682 GIM_CheckFeatures, GIFBS_HasNEON,
2683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2684 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2685 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2686 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2687 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2688 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2689 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2690 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2691 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2692 GIM_CheckIsSafeToFold, /*InsnID*/1,
2693 GIM_CheckIsSafeToFold, /*InsnID*/2,
2694 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2699 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2700 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2701 GIR_EraseFromParent, /*InsnID*/0,
2702 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2703 // GIR_Coverage, 792,
2704 GIR_Done,
2705 // Label 142: @4910
2706 GIM_Try, /*On fail goto*//*Label 143*/ 4979, // Rule ID 791 //
2707 GIM_CheckFeatures, GIFBS_HasNEON,
2708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2709 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2710 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2711 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2712 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2713 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2714 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2715 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2716 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2717 GIM_CheckIsSafeToFold, /*InsnID*/1,
2718 GIM_CheckIsSafeToFold, /*InsnID*/2,
2719 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2724 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2725 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2726 GIR_EraseFromParent, /*InsnID*/0,
2727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2728 // GIR_Coverage, 791,
2729 GIR_Done,
2730 // Label 143: @4979
2731 GIM_Try, /*On fail goto*//*Label 144*/ 5048, // Rule ID 783 //
2732 GIM_CheckFeatures, GIFBS_HasNEON,
2733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2734 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2735 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2736 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2737 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2738 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2739 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2740 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2741 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2742 GIM_CheckIsSafeToFold, /*InsnID*/1,
2743 GIM_CheckIsSafeToFold, /*InsnID*/2,
2744 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2749 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2750 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2751 GIR_EraseFromParent, /*InsnID*/0,
2752 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2753 // GIR_Coverage, 783,
2754 GIR_Done,
2755 // Label 144: @5048
2756 GIM_Try, /*On fail goto*//*Label 145*/ 5117, // Rule ID 790 //
2757 GIM_CheckFeatures, GIFBS_HasNEON,
2758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2759 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2760 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2761 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2762 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2763 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2764 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
2765 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2766 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2767 GIM_CheckIsSafeToFold, /*InsnID*/1,
2768 GIM_CheckIsSafeToFold, /*InsnID*/2,
2769 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2770 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2774 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2775 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2776 GIR_EraseFromParent, /*InsnID*/0,
2777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2778 // GIR_Coverage, 790,
2779 GIR_Done,
2780 // Label 145: @5117
2781 GIM_Try, /*On fail goto*//*Label 146*/ 5186, // Rule ID 789 //
2782 GIM_CheckFeatures, GIFBS_HasNEON,
2783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2784 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2785 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2786 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2787 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2788 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2789 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2790 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2791 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2792 GIM_CheckIsSafeToFold, /*InsnID*/1,
2793 GIM_CheckIsSafeToFold, /*InsnID*/2,
2794 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2799 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2800 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2801 GIR_EraseFromParent, /*InsnID*/0,
2802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2803 // GIR_Coverage, 789,
2804 GIR_Done,
2805 // Label 146: @5186
2806 GIM_Try, /*On fail goto*//*Label 147*/ 5254, // Rule ID 5408 //
2807 GIM_CheckFeatures, GIFBS_HasNEON,
2808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2810 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2811 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2812 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2813 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2814 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2816 GIM_CheckIsSafeToFold, /*InsnID*/1,
2817 // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2823 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2824 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2825 GIR_EraseFromParent, /*InsnID*/0,
2826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2827 // GIR_Coverage, 5408,
2828 GIR_Done,
2829 // Label 147: @5254
2830 GIM_Try, /*On fail goto*//*Label 148*/ 5310, // Rule ID 5382 //
2831 GIM_CheckFeatures, GIFBS_HasNEON,
2832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2833 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2834 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2835 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2836 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2838 GIM_CheckIsSafeToFold, /*InsnID*/1,
2839 // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2844 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2845 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2846 GIR_EraseFromParent, /*InsnID*/0,
2847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2848 // GIR_Coverage, 5382,
2849 GIR_Done,
2850 // Label 148: @5310
2851 GIM_Try, /*On fail goto*//*Label 149*/ 5366, // Rule ID 5377 //
2852 GIM_CheckFeatures, GIFBS_HasNEON,
2853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2854 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2855 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2856 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2857 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2859 GIM_CheckIsSafeToFold, /*InsnID*/1,
2860 // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2865 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2866 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2867 GIR_EraseFromParent, /*InsnID*/0,
2868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2869 // GIR_Coverage, 5377,
2870 GIR_Done,
2871 // Label 149: @5366
2872 GIM_Try, /*On fail goto*//*Label 150*/ 5422, // Rule ID 5381 //
2873 GIM_CheckFeatures, GIFBS_HasNEON,
2874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2876 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2877 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2878 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2880 GIM_CheckIsSafeToFold, /*InsnID*/1,
2881 // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2882 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2886 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2887 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2888 GIR_EraseFromParent, /*InsnID*/0,
2889 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2890 // GIR_Coverage, 5381,
2891 GIR_Done,
2892 // Label 150: @5422
2893 GIM_Try, /*On fail goto*//*Label 151*/ 5490, // Rule ID 906 //
2894 GIM_CheckFeatures, GIFBS_HasNEON,
2895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2898 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2899 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2900 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2901 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2902 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2903 GIM_CheckIsSafeToFold, /*InsnID*/1,
2904 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2910 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2911 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2912 GIR_EraseFromParent, /*InsnID*/0,
2913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2914 // GIR_Coverage, 906,
2915 GIR_Done,
2916 // Label 151: @5490
2917 GIM_Try, /*On fail goto*//*Label 152*/ 5546, // Rule ID 803 //
2918 GIM_CheckFeatures, GIFBS_HasNEON,
2919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2921 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2922 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
2923 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2924 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2925 GIM_CheckIsSafeToFold, /*InsnID*/1,
2926 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2931 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2932 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2933 GIR_EraseFromParent, /*InsnID*/0,
2934 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2935 // GIR_Coverage, 803,
2936 GIR_Done,
2937 // Label 152: @5546
2938 GIM_Try, /*On fail goto*//*Label 153*/ 5602, // Rule ID 798 //
2939 GIM_CheckFeatures, GIFBS_HasNEON,
2940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2943 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2944 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2945 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2946 GIM_CheckIsSafeToFold, /*InsnID*/1,
2947 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2952 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2953 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2954 GIR_EraseFromParent, /*InsnID*/0,
2955 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2956 // GIR_Coverage, 798,
2957 GIR_Done,
2958 // Label 153: @5602
2959 GIM_Try, /*On fail goto*//*Label 154*/ 5658, // Rule ID 802 //
2960 GIM_CheckFeatures, GIFBS_HasNEON,
2961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2964 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2965 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2966 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2967 GIM_CheckIsSafeToFold, /*InsnID*/1,
2968 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2973 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2974 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2975 GIR_EraseFromParent, /*InsnID*/0,
2976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2977 // GIR_Coverage, 802,
2978 GIR_Done,
2979 // Label 154: @5658
2980 GIM_Try, /*On fail goto*//*Label 155*/ 5701, // Rule ID 775 //
2981 GIM_CheckFeatures, GIFBS_HasNEON,
2982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2985 // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2990 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2991 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
2992 GIR_EraseFromParent, /*InsnID*/0,
2993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2994 // GIR_Coverage, 775,
2995 GIR_Done,
2996 // Label 155: @5701
2997 GIM_Try, /*On fail goto*//*Label 156*/ 5758, // Rule ID 3486 //
2998 GIM_CheckFeatures, GIFBS_HasMVEInt,
2999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3002 // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
3003 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi32,
3007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3010 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3011 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3012 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3013 GIR_EraseFromParent, /*InsnID*/0,
3014 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3015 // GIR_Coverage, 3486,
3016 GIR_Done,
3017 // Label 156: @5758
3018 GIM_Reject,
3019 // Label 133: @5759
3020 GIM_Reject,
3021 // Label 66: @5760
3022 GIM_Try, /*On fail goto*//*Label 157*/ 6226,
3023 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3026 GIM_Try, /*On fail goto*//*Label 158*/ 5845, // Rule ID 5473 //
3027 GIM_CheckFeatures, GIFBS_HasNEON,
3028 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3029 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3030 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3031 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3032 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3033 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3034 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3035 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3037 GIM_CheckIsSafeToFold, /*InsnID*/1,
3038 // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 2142:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
3040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3044 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3045 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3046 GIR_EraseFromParent, /*InsnID*/0,
3047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3048 // GIR_Coverage, 5473,
3049 GIR_Done,
3050 // Label 158: @5845
3051 GIM_Try, /*On fail goto*//*Label 159*/ 5916, // Rule ID 5479 //
3052 GIM_CheckFeatures, GIFBS_HasNEON,
3053 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3054 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3055 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3056 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3057 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3058 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3059 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3060 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3062 GIM_CheckIsSafeToFold, /*InsnID*/1,
3063 // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 2143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
3065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3069 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3070 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3071 GIR_EraseFromParent, /*InsnID*/0,
3072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3073 // GIR_Coverage, 5479,
3074 GIR_Done,
3075 // Label 159: @5916
3076 GIM_Try, /*On fail goto*//*Label 160*/ 5987, // Rule ID 1195 //
3077 GIM_CheckFeatures, GIFBS_HasNEON,
3078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3079 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3080 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3081 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3082 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3083 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3084 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3085 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3086 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3087 GIM_CheckIsSafeToFold, /*InsnID*/1,
3088 // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 2142:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
3090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3094 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3095 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3096 GIR_EraseFromParent, /*InsnID*/0,
3097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3098 // GIR_Coverage, 1195,
3099 GIR_Done,
3100 // Label 160: @5987
3101 GIM_Try, /*On fail goto*//*Label 161*/ 6058, // Rule ID 1201 //
3102 GIM_CheckFeatures, GIFBS_HasNEON,
3103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3105 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3106 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3107 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3108 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3109 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
3110 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3111 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3112 GIM_CheckIsSafeToFold, /*InsnID*/1,
3113 // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 2143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
3115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3119 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3120 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3121 GIR_EraseFromParent, /*InsnID*/0,
3122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3123 // GIR_Coverage, 1201,
3124 GIR_Done,
3125 // Label 161: @6058
3126 GIM_Try, /*On fail goto*//*Label 162*/ 6122, // Rule ID 5403 //
3127 GIM_CheckFeatures, GIFBS_HasNEON,
3128 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3129 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3130 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3131 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3132 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3133 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3135 GIM_CheckIsSafeToFold, /*InsnID*/1,
3136 // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
3138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3142 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3143 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3144 GIR_EraseFromParent, /*InsnID*/0,
3145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3146 // GIR_Coverage, 5403,
3147 GIR_Done,
3148 // Label 162: @6122
3149 GIM_Try, /*On fail goto*//*Label 163*/ 6186, // Rule ID 901 //
3150 GIM_CheckFeatures, GIFBS_HasNEON,
3151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3153 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3154 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3155 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3156 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3157 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3158 GIM_CheckIsSafeToFold, /*InsnID*/1,
3159 // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
3161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3165 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3166 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3167 GIR_EraseFromParent, /*InsnID*/0,
3168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3169 // GIR_Coverage, 901,
3170 GIR_Done,
3171 // Label 163: @6186
3172 GIM_Try, /*On fail goto*//*Label 164*/ 6225, // Rule ID 770 //
3173 GIM_CheckFeatures, GIFBS_HasNEON,
3174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3176 // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
3178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3181 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3182 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3183 GIR_EraseFromParent, /*InsnID*/0,
3184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3185 // GIR_Coverage, 770,
3186 GIR_Done,
3187 // Label 164: @6225
3188 GIM_Reject,
3189 // Label 157: @6226
3190 GIM_Reject,
3191 // Label 67: @6227
3192 GIM_Try, /*On fail goto*//*Label 165*/ 7807,
3193 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3194 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3195 GIM_Try, /*On fail goto*//*Label 166*/ 6325, // Rule ID 5485 //
3196 GIM_CheckFeatures, GIFBS_HasNEON,
3197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3198 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3199 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3200 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3201 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3202 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3203 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3204 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
3205 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3206 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3207 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3208 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3210 GIM_CheckIsSafeToFold, /*InsnID*/1,
3211 GIM_CheckIsSafeToFold, /*InsnID*/2,
3212 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2142:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
3214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3218 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3219 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3220 GIR_EraseFromParent, /*InsnID*/0,
3221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3222 // GIR_Coverage, 5485,
3223 GIR_Done,
3224 // Label 166: @6325
3225 GIM_Try, /*On fail goto*//*Label 167*/ 6413, // Rule ID 5488 //
3226 GIM_CheckFeatures, GIFBS_HasNEON,
3227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3228 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3229 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3230 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3231 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3232 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3233 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3234 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
3235 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3236 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3237 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3238 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3240 GIM_CheckIsSafeToFold, /*InsnID*/1,
3241 GIM_CheckIsSafeToFold, /*InsnID*/2,
3242 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
3244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3248 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3249 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3250 GIR_EraseFromParent, /*InsnID*/0,
3251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3252 // GIR_Coverage, 5488,
3253 GIR_Done,
3254 // Label 167: @6413
3255 GIM_Try, /*On fail goto*//*Label 168*/ 6501, // Rule ID 1207 //
3256 GIM_CheckFeatures, GIFBS_HasNEON,
3257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3259 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3260 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3261 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3262 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3263 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3264 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3265 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
3266 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3267 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3268 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3269 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3270 GIM_CheckIsSafeToFold, /*InsnID*/1,
3271 GIM_CheckIsSafeToFold, /*InsnID*/2,
3272 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2142:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
3274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3278 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3279 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3280 GIR_EraseFromParent, /*InsnID*/0,
3281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3282 // GIR_Coverage, 1207,
3283 GIR_Done,
3284 // Label 168: @6501
3285 GIM_Try, /*On fail goto*//*Label 169*/ 6589, // Rule ID 1210 //
3286 GIM_CheckFeatures, GIFBS_HasNEON,
3287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3289 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3290 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3291 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3292 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3293 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
3294 GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
3295 GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
3296 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3297 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
3298 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3299 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
3300 GIM_CheckIsSafeToFold, /*InsnID*/1,
3301 GIM_CheckIsSafeToFold, /*InsnID*/2,
3302 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
3304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
3307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
3308 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3309 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3310 GIR_EraseFromParent, /*InsnID*/0,
3311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3312 // GIR_Coverage, 1210,
3313 GIR_Done,
3314 // Label 169: @6589
3315 GIM_Try, /*On fail goto*//*Label 170*/ 6664, // Rule ID 5477 //
3316 GIM_CheckFeatures, GIFBS_HasNEON,
3317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3318 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3319 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3320 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3321 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3322 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3323 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3324 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3325 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3327 GIM_CheckIsSafeToFold, /*InsnID*/1,
3328 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 2142:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3334 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3335 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3336 GIR_EraseFromParent, /*InsnID*/0,
3337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3338 // GIR_Coverage, 5477,
3339 GIR_Done,
3340 // Label 170: @6664
3341 GIM_Try, /*On fail goto*//*Label 171*/ 6739, // Rule ID 5483 //
3342 GIM_CheckFeatures, GIFBS_HasNEON,
3343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3344 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3345 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3346 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3347 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3348 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3349 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3350 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3351 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3353 GIM_CheckIsSafeToFold, /*InsnID*/1,
3354 // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 2143:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3360 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3361 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3362 GIR_EraseFromParent, /*InsnID*/0,
3363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3364 // GIR_Coverage, 5483,
3365 GIR_Done,
3366 // Label 171: @6739
3367 GIM_Try, /*On fail goto*//*Label 172*/ 6814, // Rule ID 1199 //
3368 GIM_CheckFeatures, GIFBS_HasNEON,
3369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3372 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3373 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3374 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3375 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3376 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3377 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3378 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3379 GIM_CheckIsSafeToFold, /*InsnID*/1,
3380 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 2142:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
3382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3386 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3387 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3388 GIR_EraseFromParent, /*InsnID*/0,
3389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3390 // GIR_Coverage, 1199,
3391 GIR_Done,
3392 // Label 172: @6814
3393 GIM_Try, /*On fail goto*//*Label 173*/ 6889, // Rule ID 1205 //
3394 GIM_CheckFeatures, GIFBS_HasNEON,
3395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3398 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3399 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3400 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3401 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3402 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
3403 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3404 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3405 GIM_CheckIsSafeToFold, /*InsnID*/1,
3406 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 2143:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
3408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3412 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3413 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3414 GIR_EraseFromParent, /*InsnID*/0,
3415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3416 // GIR_Coverage, 1205,
3417 GIR_Done,
3418 // Label 173: @6889
3419 GIM_Try, /*On fail goto*//*Label 174*/ 6958, // Rule ID 788 //
3420 GIM_CheckFeatures, GIFBS_HasNEON,
3421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3422 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3423 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3424 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3425 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3426 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3427 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
3428 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3429 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3430 GIM_CheckIsSafeToFold, /*InsnID*/1,
3431 GIM_CheckIsSafeToFold, /*InsnID*/2,
3432 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3437 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3438 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3439 GIR_EraseFromParent, /*InsnID*/0,
3440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3441 // GIR_Coverage, 788,
3442 GIR_Done,
3443 // Label 174: @6958
3444 GIM_Try, /*On fail goto*//*Label 175*/ 7027, // Rule ID 787 //
3445 GIM_CheckFeatures, GIFBS_HasNEON,
3446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3447 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3448 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3449 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3450 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3451 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3452 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3453 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3454 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3455 GIM_CheckIsSafeToFold, /*InsnID*/1,
3456 GIM_CheckIsSafeToFold, /*InsnID*/2,
3457 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3458 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3462 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3463 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3464 GIR_EraseFromParent, /*InsnID*/0,
3465 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3466 // GIR_Coverage, 787,
3467 GIR_Done,
3468 // Label 175: @7027
3469 GIM_Try, /*On fail goto*//*Label 176*/ 7096, // Rule ID 782 //
3470 GIM_CheckFeatures, GIFBS_HasNEON,
3471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3472 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3473 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3474 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3475 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3476 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3477 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3478 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3479 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3480 GIM_CheckIsSafeToFold, /*InsnID*/1,
3481 GIM_CheckIsSafeToFold, /*InsnID*/2,
3482 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
3484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3487 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3488 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3489 GIR_EraseFromParent, /*InsnID*/0,
3490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3491 // GIR_Coverage, 782,
3492 GIR_Done,
3493 // Label 176: @7096
3494 GIM_Try, /*On fail goto*//*Label 177*/ 7165, // Rule ID 786 //
3495 GIM_CheckFeatures, GIFBS_HasNEON,
3496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3498 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3499 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3500 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3501 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3502 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
3503 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3504 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3505 GIM_CheckIsSafeToFold, /*InsnID*/1,
3506 GIM_CheckIsSafeToFold, /*InsnID*/2,
3507 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3512 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3513 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3514 GIR_EraseFromParent, /*InsnID*/0,
3515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3516 // GIR_Coverage, 786,
3517 GIR_Done,
3518 // Label 177: @7165
3519 GIM_Try, /*On fail goto*//*Label 178*/ 7234, // Rule ID 785 //
3520 GIM_CheckFeatures, GIFBS_HasNEON,
3521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3522 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3523 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3524 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3525 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3526 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3527 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3528 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3529 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3530 GIM_CheckIsSafeToFold, /*InsnID*/1,
3531 GIM_CheckIsSafeToFold, /*InsnID*/2,
3532 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
3534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3537 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3538 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3539 GIR_EraseFromParent, /*InsnID*/0,
3540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3541 // GIR_Coverage, 785,
3542 GIR_Done,
3543 // Label 178: @7234
3544 GIM_Try, /*On fail goto*//*Label 179*/ 7302, // Rule ID 5407 //
3545 GIM_CheckFeatures, GIFBS_HasNEON,
3546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3547 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3548 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3549 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3550 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3551 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3552 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3554 GIM_CheckIsSafeToFold, /*InsnID*/1,
3555 // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3561 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3562 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3563 GIR_EraseFromParent, /*InsnID*/0,
3564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3565 // GIR_Coverage, 5407,
3566 GIR_Done,
3567 // Label 179: @7302
3568 GIM_Try, /*On fail goto*//*Label 180*/ 7358, // Rule ID 5380 //
3569 GIM_CheckFeatures, GIFBS_HasNEON,
3570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3571 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3572 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3573 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3574 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3576 GIM_CheckIsSafeToFold, /*InsnID*/1,
3577 // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3582 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3583 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3584 GIR_EraseFromParent, /*InsnID*/0,
3585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3586 // GIR_Coverage, 5380,
3587 GIR_Done,
3588 // Label 180: @7358
3589 GIM_Try, /*On fail goto*//*Label 181*/ 7414, // Rule ID 5376 //
3590 GIM_CheckFeatures, GIFBS_HasNEON,
3591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3592 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3593 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3594 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3595 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3597 GIM_CheckIsSafeToFold, /*InsnID*/1,
3598 // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3603 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3604 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3605 GIR_EraseFromParent, /*InsnID*/0,
3606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3607 // GIR_Coverage, 5376,
3608 GIR_Done,
3609 // Label 181: @7414
3610 GIM_Try, /*On fail goto*//*Label 182*/ 7470, // Rule ID 5379 //
3611 GIM_CheckFeatures, GIFBS_HasNEON,
3612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3613 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3614 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3615 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3618 GIM_CheckIsSafeToFold, /*InsnID*/1,
3619 // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
3623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3624 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3625 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3626 GIR_EraseFromParent, /*InsnID*/0,
3627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3628 // GIR_Coverage, 5379,
3629 GIR_Done,
3630 // Label 182: @7470
3631 GIM_Try, /*On fail goto*//*Label 183*/ 7538, // Rule ID 905 //
3632 GIM_CheckFeatures, GIFBS_HasNEON,
3633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3635 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3636 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3637 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3638 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3639 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3640 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3641 GIM_CheckIsSafeToFold, /*InsnID*/1,
3642 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
3644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3648 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3649 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3650 GIR_EraseFromParent, /*InsnID*/0,
3651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3652 // GIR_Coverage, 905,
3653 GIR_Done,
3654 // Label 183: @7538
3655 GIM_Try, /*On fail goto*//*Label 184*/ 7594, // Rule ID 801 //
3656 GIM_CheckFeatures, GIFBS_HasNEON,
3657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3659 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3660 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
3661 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3662 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3663 GIM_CheckIsSafeToFold, /*InsnID*/1,
3664 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3669 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3670 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3671 GIR_EraseFromParent, /*InsnID*/0,
3672 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3673 // GIR_Coverage, 801,
3674 GIR_Done,
3675 // Label 184: @7594
3676 GIM_Try, /*On fail goto*//*Label 185*/ 7650, // Rule ID 797 //
3677 GIM_CheckFeatures, GIFBS_HasNEON,
3678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3680 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3681 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3682 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3683 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3684 GIM_CheckIsSafeToFold, /*InsnID*/1,
3685 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
3687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3690 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3691 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3692 GIR_EraseFromParent, /*InsnID*/0,
3693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3694 // GIR_Coverage, 797,
3695 GIR_Done,
3696 // Label 185: @7650
3697 GIM_Try, /*On fail goto*//*Label 186*/ 7706, // Rule ID 800 //
3698 GIM_CheckFeatures, GIFBS_HasNEON,
3699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3701 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3702 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3703 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3704 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3705 GIM_CheckIsSafeToFold, /*InsnID*/1,
3706 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
3708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3711 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3712 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3713 GIR_EraseFromParent, /*InsnID*/0,
3714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3715 // GIR_Coverage, 800,
3716 GIR_Done,
3717 // Label 186: @7706
3718 GIM_Try, /*On fail goto*//*Label 187*/ 7749, // Rule ID 774 //
3719 GIM_CheckFeatures, GIFBS_HasNEON,
3720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3723 // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
3725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3728 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3729 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3730 GIR_EraseFromParent, /*InsnID*/0,
3731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3732 // GIR_Coverage, 774,
3733 GIR_Done,
3734 // Label 187: @7749
3735 GIM_Try, /*On fail goto*//*Label 188*/ 7806, // Rule ID 3482 //
3736 GIM_CheckFeatures, GIFBS_HasMVEInt,
3737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3740 // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3741 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3742 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3743 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi16,
3745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3748 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3749 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3750 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3751 GIR_EraseFromParent, /*InsnID*/0,
3752 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3753 // GIR_Coverage, 3482,
3754 GIR_Done,
3755 // Label 188: @7806
3756 GIM_Reject,
3757 // Label 165: @7807
3758 GIM_Reject,
3759 // Label 68: @7808
3760 GIM_Try, /*On fail goto*//*Label 189*/ 8355,
3761 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3763 GIM_Try, /*On fail goto*//*Label 190*/ 7893, // Rule ID 5476 //
3764 GIM_CheckFeatures, GIFBS_HasNEON,
3765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3766 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3767 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3768 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3769 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3770 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3771 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3772 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3773 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3775 GIM_CheckIsSafeToFold, /*InsnID*/1,
3776 // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 2142:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3782 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3783 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3784 GIR_EraseFromParent, /*InsnID*/0,
3785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3786 // GIR_Coverage, 5476,
3787 GIR_Done,
3788 // Label 190: @7893
3789 GIM_Try, /*On fail goto*//*Label 191*/ 7968, // Rule ID 5482 //
3790 GIM_CheckFeatures, GIFBS_HasNEON,
3791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3793 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3794 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3795 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3796 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3797 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3798 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3801 GIM_CheckIsSafeToFold, /*InsnID*/1,
3802 // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 2143:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3808 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3809 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3810 GIR_EraseFromParent, /*InsnID*/0,
3811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3812 // GIR_Coverage, 5482,
3813 GIR_Done,
3814 // Label 191: @7968
3815 GIM_Try, /*On fail goto*//*Label 192*/ 8043, // Rule ID 1198 //
3816 GIM_CheckFeatures, GIFBS_HasNEON,
3817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3819 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3820 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3821 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3822 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3824 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3825 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3826 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3827 GIM_CheckIsSafeToFold, /*InsnID*/1,
3828 // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 2142:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3834 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3835 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3836 GIR_EraseFromParent, /*InsnID*/0,
3837 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3838 // GIR_Coverage, 1198,
3839 GIR_Done,
3840 // Label 192: @8043
3841 GIM_Try, /*On fail goto*//*Label 193*/ 8118, // Rule ID 1204 //
3842 GIM_CheckFeatures, GIFBS_HasNEON,
3843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3845 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3846 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3847 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3848 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3849 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3850 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3851 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3852 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3853 GIM_CheckIsSafeToFold, /*InsnID*/1,
3854 // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 2143:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3860 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3861 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3862 GIR_EraseFromParent, /*InsnID*/0,
3863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3864 // GIR_Coverage, 1204,
3865 GIR_Done,
3866 // Label 193: @8118
3867 GIM_Try, /*On fail goto*//*Label 194*/ 8186, // Rule ID 5406 //
3868 GIM_CheckFeatures, GIFBS_HasNEON,
3869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3870 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3871 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3872 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3873 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3874 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3875 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3877 GIM_CheckIsSafeToFold, /*InsnID*/1,
3878 // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3884 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3885 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3886 GIR_EraseFromParent, /*InsnID*/0,
3887 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3888 // GIR_Coverage, 5406,
3889 GIR_Done,
3890 // Label 194: @8186
3891 GIM_Try, /*On fail goto*//*Label 195*/ 8254, // Rule ID 904 //
3892 GIM_CheckFeatures, GIFBS_HasNEON,
3893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3895 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3896 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3897 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3898 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3899 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3900 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3901 GIM_CheckIsSafeToFold, /*InsnID*/1,
3902 // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3908 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3909 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3910 GIR_EraseFromParent, /*InsnID*/0,
3911 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3912 // GIR_Coverage, 904,
3913 GIR_Done,
3914 // Label 195: @8254
3915 GIM_Try, /*On fail goto*//*Label 196*/ 8297, // Rule ID 773 //
3916 GIM_CheckFeatures, GIFBS_HasNEON,
3917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3920 // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3925 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3926 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3927 GIR_EraseFromParent, /*InsnID*/0,
3928 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3929 // GIR_Coverage, 773,
3930 GIR_Done,
3931 // Label 196: @8297
3932 GIM_Try, /*On fail goto*//*Label 197*/ 8354, // Rule ID 3478 //
3933 GIM_CheckFeatures, GIFBS_HasMVEInt,
3934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
3935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
3936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
3937 // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3938 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3939 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
3940 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
3941 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDi8,
3942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
3943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
3944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
3945 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
3946 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3947 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
3948 GIR_EraseFromParent, /*InsnID*/0,
3949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3950 // GIR_Coverage, 3478,
3951 GIR_Done,
3952 // Label 197: @8354
3953 GIM_Reject,
3954 // Label 189: @8355
3955 GIM_Reject,
3956 // Label 69: @8356
3957 GIM_Reject,
3958 // Label 1: @8357
3959 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 207*/ 11384,
3960 /*GILLT_s32*//*Label 198*/ 8377,
3961 /*GILLT_s64*//*Label 199*/ 8885,
3962 /*GILLT_v2s32*//*Label 200*/ 8937,
3963 /*GILLT_v2s64*//*Label 201*/ 9052, 0,
3964 /*GILLT_v4s16*//*Label 202*/ 9588,
3965 /*GILLT_v4s32*//*Label 203*/ 9703, 0, 0,
3966 /*GILLT_v8s8*//*Label 204*/ 10396,
3967 /*GILLT_v8s16*//*Label 205*/ 10511, 0, 0,
3968 /*GILLT_v16s8*//*Label 206*/ 11204,
3969 // Label 198: @8377
3970 GIM_Try, /*On fail goto*//*Label 208*/ 8884,
3971 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3972 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3973 GIM_Try, /*On fail goto*//*Label 209*/ 8441, // Rule ID 96 //
3974 GIM_CheckFeatures, GIFBS_IsARM,
3975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3976 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3977 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3978 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3979 // MIs[1] Operand 1
3980 // No operand predicates
3981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3982 GIM_CheckIsSafeToFold, /*InsnID*/1,
3983 // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3984 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3987 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3988 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3989 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3990 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
3991 GIR_EraseFromParent, /*InsnID*/0,
3992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3993 // GIR_Coverage, 96,
3994 GIR_Done,
3995 // Label 209: @8441
3996 GIM_Try, /*On fail goto*//*Label 210*/ 8495, // Rule ID 434 //
3997 GIM_CheckFeatures, GIFBS_IsThumb2,
3998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4000 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4001 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4002 // MIs[1] Operand 1
4003 // No operand predicates
4004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4005 GIM_CheckIsSafeToFold, /*InsnID*/1,
4006 // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
4008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4010 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4011 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4012 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4013 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4014 GIR_EraseFromParent, /*InsnID*/0,
4015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4016 // GIR_Coverage, 434,
4017 GIR_Done,
4018 // Label 210: @8495
4019 GIM_Try, /*On fail goto*//*Label 211*/ 8549, // Rule ID 76 //
4020 GIM_CheckFeatures, GIFBS_IsARM,
4021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4023 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4024 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4025 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4026 // MIs[1] Operand 1
4027 // No operand predicates
4028 GIM_CheckIsSafeToFold, /*InsnID*/1,
4029 // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
4031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4033 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4034 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4035 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4036 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4037 GIR_EraseFromParent, /*InsnID*/0,
4038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4039 // GIR_Coverage, 76,
4040 GIR_Done,
4041 // Label 211: @8549
4042 GIM_Try, /*On fail goto*//*Label 212*/ 8603, // Rule ID 418 //
4043 GIM_CheckFeatures, GIFBS_IsThumb2,
4044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4046 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4047 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4048 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4049 // MIs[1] Operand 1
4050 // No operand predicates
4051 GIM_CheckIsSafeToFold, /*InsnID*/1,
4052 // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
4054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4056 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4057 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4058 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4059 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4060 GIR_EraseFromParent, /*InsnID*/0,
4061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4062 // GIR_Coverage, 418,
4063 GIR_Done,
4064 // Label 212: @8603
4065 GIM_Try, /*On fail goto*//*Label 213*/ 8653, // Rule ID 419 //
4066 GIM_CheckFeatures, GIFBS_IsThumb2,
4067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4070 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4071 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
4072 // MIs[1] Operand 1
4073 // No operand predicates
4074 GIM_CheckIsSafeToFold, /*InsnID*/1,
4075 // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
4077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4079 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4080 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4081 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4082 GIR_EraseFromParent, /*InsnID*/0,
4083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4084 // GIR_Coverage, 419,
4085 GIR_Done,
4086 // Label 213: @8653
4087 GIM_Try, /*On fail goto*//*Label 214*/ 8721, // Rule ID 173 //
4088 GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
4089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4091 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4092 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4093 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4094 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4095 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4097 GIM_CheckIsSafeToFold, /*InsnID*/1,
4098 // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
4099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
4100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
4104 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4105 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4106 GIR_EraseFromParent, /*InsnID*/0,
4107 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4108 // GIR_Coverage, 173,
4109 GIR_Done,
4110 // Label 214: @8721
4111 GIM_Try, /*On fail goto*//*Label 215*/ 8789, // Rule ID 511 //
4112 GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
4113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4115 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4116 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4117 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4118 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4119 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4120 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4121 GIM_CheckIsSafeToFold, /*InsnID*/1,
4122 // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
4123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
4124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
4128 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4129 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4130 GIR_EraseFromParent, /*InsnID*/0,
4131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4132 // GIR_Coverage, 511,
4133 GIR_Done,
4134 // Label 215: @8789
4135 GIM_Try, /*On fail goto*//*Label 216*/ 8836, // Rule ID 77 //
4136 GIM_CheckFeatures, GIFBS_IsARM,
4137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4140 // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
4142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4145 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4146 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4147 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4148 GIR_EraseFromParent, /*InsnID*/0,
4149 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4150 // GIR_Coverage, 77,
4151 GIR_Done,
4152 // Label 216: @8836
4153 GIM_Try, /*On fail goto*//*Label 217*/ 8883, // Rule ID 420 //
4154 GIM_CheckFeatures, GIFBS_IsThumb2,
4155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4158 // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
4160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4163 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4164 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4165 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4166 GIR_EraseFromParent, /*InsnID*/0,
4167 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4168 // GIR_Coverage, 420,
4169 GIR_Done,
4170 // Label 217: @8883
4171 GIM_Reject,
4172 // Label 208: @8884
4173 GIM_Reject,
4174 // Label 199: @8885
4175 GIM_Try, /*On fail goto*//*Label 218*/ 8936, // Rule ID 980 //
4176 GIM_CheckFeatures, GIFBS_HasNEON,
4177 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
4178 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
4179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4182 // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
4183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
4184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4187 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4188 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4189 GIR_EraseFromParent, /*InsnID*/0,
4190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4191 // GIR_Coverage, 980,
4192 GIR_Done,
4193 // Label 218: @8936
4194 GIM_Reject,
4195 // Label 200: @8937
4196 GIM_Try, /*On fail goto*//*Label 219*/ 9051,
4197 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4198 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4201 GIM_Try, /*On fail goto*//*Label 220*/ 9015, // Rule ID 931 //
4202 GIM_CheckFeatures, GIFBS_HasNEON,
4203 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4204 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4205 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4206 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4207 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4208 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4209 GIM_CheckIsSafeToFold, /*InsnID*/1,
4210 // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
4212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4216 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4217 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4218 GIR_EraseFromParent, /*InsnID*/0,
4219 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4220 // GIR_Coverage, 931,
4221 GIR_Done,
4222 // Label 220: @9015
4223 GIM_Try, /*On fail goto*//*Label 221*/ 9050, // Rule ID 976 //
4224 GIM_CheckFeatures, GIFBS_HasNEON,
4225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4226 // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
4228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4231 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4232 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4233 GIR_EraseFromParent, /*InsnID*/0,
4234 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4235 // GIR_Coverage, 976,
4236 GIR_Done,
4237 // Label 221: @9050
4238 GIM_Reject,
4239 // Label 219: @9051
4240 GIM_Reject,
4241 // Label 201: @9052
4242 GIM_Try, /*On fail goto*//*Label 222*/ 9587,
4243 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
4244 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
4245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4246 GIM_Try, /*On fail goto*//*Label 223*/ 9131, // Rule ID 1000 //
4247 GIM_CheckFeatures, GIFBS_HasNEON,
4248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4249 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4250 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4251 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4252 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4253 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4254 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4255 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4256 GIM_CheckIsSafeToFold, /*InsnID*/1,
4257 GIM_CheckIsSafeToFold, /*InsnID*/2,
4258 // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4263 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4264 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4265 GIR_EraseFromParent, /*InsnID*/0,
4266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4267 // GIR_Coverage, 1000,
4268 GIR_Done,
4269 // Label 223: @9131
4270 GIM_Try, /*On fail goto*//*Label 224*/ 9196, // Rule ID 999 //
4271 GIM_CheckFeatures, GIFBS_HasNEON,
4272 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4273 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4274 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4275 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4276 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4277 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4278 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4279 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4280 GIM_CheckIsSafeToFold, /*InsnID*/1,
4281 GIM_CheckIsSafeToFold, /*InsnID*/2,
4282 // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4287 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4288 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4289 GIR_EraseFromParent, /*InsnID*/0,
4290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4291 // GIR_Coverage, 999,
4292 GIR_Done,
4293 // Label 224: @9196
4294 GIM_Try, /*On fail goto*//*Label 225*/ 9261, // Rule ID 988 //
4295 GIM_CheckFeatures, GIFBS_HasNEON,
4296 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4297 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4298 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4299 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4300 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4301 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4302 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4303 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4304 GIM_CheckIsSafeToFold, /*InsnID*/1,
4305 GIM_CheckIsSafeToFold, /*InsnID*/2,
4306 // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
4308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4311 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4312 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4313 GIR_EraseFromParent, /*InsnID*/0,
4314 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4315 // GIR_Coverage, 988,
4316 GIR_Done,
4317 // Label 225: @9261
4318 GIM_Try, /*On fail goto*//*Label 226*/ 9326, // Rule ID 998 //
4319 GIM_CheckFeatures, GIFBS_HasNEON,
4320 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4321 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4322 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4323 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4324 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4325 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4326 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4327 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4328 GIM_CheckIsSafeToFold, /*InsnID*/1,
4329 GIM_CheckIsSafeToFold, /*InsnID*/2,
4330 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4335 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4336 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4337 GIR_EraseFromParent, /*InsnID*/0,
4338 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4339 // GIR_Coverage, 998,
4340 GIR_Done,
4341 // Label 226: @9326
4342 GIM_Try, /*On fail goto*//*Label 227*/ 9391, // Rule ID 997 //
4343 GIM_CheckFeatures, GIFBS_HasNEON,
4344 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4345 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4346 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4347 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4348 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4349 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4350 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4351 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4352 GIM_CheckIsSafeToFold, /*InsnID*/1,
4353 GIM_CheckIsSafeToFold, /*InsnID*/2,
4354 // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
4356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4359 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4360 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4361 GIR_EraseFromParent, /*InsnID*/0,
4362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4363 // GIR_Coverage, 997,
4364 GIR_Done,
4365 // Label 227: @9391
4366 GIM_Try, /*On fail goto*//*Label 228*/ 9443, // Rule ID 1009 //
4367 GIM_CheckFeatures, GIFBS_HasNEON,
4368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4370 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4371 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4372 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4373 GIM_CheckIsSafeToFold, /*InsnID*/1,
4374 // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
4376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4379 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4380 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4381 GIR_EraseFromParent, /*InsnID*/0,
4382 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4383 // GIR_Coverage, 1009,
4384 GIR_Done,
4385 // Label 228: @9443
4386 GIM_Try, /*On fail goto*//*Label 229*/ 9495, // Rule ID 1003 //
4387 GIM_CheckFeatures, GIFBS_HasNEON,
4388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4389 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4390 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4391 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4392 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4393 GIM_CheckIsSafeToFold, /*InsnID*/1,
4394 // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
4396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4399 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4400 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4401 GIR_EraseFromParent, /*InsnID*/0,
4402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4403 // GIR_Coverage, 1003,
4404 GIR_Done,
4405 // Label 229: @9495
4406 GIM_Try, /*On fail goto*//*Label 230*/ 9547, // Rule ID 1008 //
4407 GIM_CheckFeatures, GIFBS_HasNEON,
4408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4409 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4410 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4411 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4412 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4413 GIM_CheckIsSafeToFold, /*InsnID*/1,
4414 // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
4416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4419 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4420 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4421 GIR_EraseFromParent, /*InsnID*/0,
4422 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4423 // GIR_Coverage, 1008,
4424 GIR_Done,
4425 // Label 230: @9547
4426 GIM_Try, /*On fail goto*//*Label 231*/ 9586, // Rule ID 981 //
4427 GIM_CheckFeatures, GIFBS_HasNEON,
4428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4430 // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
4431 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
4432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4435 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4436 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4437 GIR_EraseFromParent, /*InsnID*/0,
4438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4439 // GIR_Coverage, 981,
4440 GIR_Done,
4441 // Label 231: @9586
4442 GIM_Reject,
4443 // Label 222: @9587
4444 GIM_Reject,
4445 // Label 202: @9588
4446 GIM_Try, /*On fail goto*//*Label 232*/ 9702,
4447 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4451 GIM_Try, /*On fail goto*//*Label 233*/ 9666, // Rule ID 930 //
4452 GIM_CheckFeatures, GIFBS_HasNEON,
4453 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4454 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4455 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4456 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
4457 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4458 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4459 GIM_CheckIsSafeToFold, /*InsnID*/1,
4460 // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
4462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4466 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4467 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4468 GIR_EraseFromParent, /*InsnID*/0,
4469 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4470 // GIR_Coverage, 930,
4471 GIR_Done,
4472 // Label 233: @9666
4473 GIM_Try, /*On fail goto*//*Label 234*/ 9701, // Rule ID 975 //
4474 GIM_CheckFeatures, GIFBS_HasNEON,
4475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4476 // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
4478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4481 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4482 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4483 GIR_EraseFromParent, /*InsnID*/0,
4484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4485 // GIR_Coverage, 975,
4486 GIR_Done,
4487 // Label 234: @9701
4488 GIM_Reject,
4489 // Label 232: @9702
4490 GIM_Reject,
4491 // Label 203: @9703
4492 GIM_Try, /*On fail goto*//*Label 235*/ 10395,
4493 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4494 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4495 GIM_Try, /*On fail goto*//*Label 236*/ 9782, // Rule ID 996 //
4496 GIM_CheckFeatures, GIFBS_HasNEON,
4497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4499 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4500 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4501 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4502 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4503 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4504 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4505 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4506 GIM_CheckIsSafeToFold, /*InsnID*/1,
4507 GIM_CheckIsSafeToFold, /*InsnID*/2,
4508 // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4513 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4514 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4515 GIR_EraseFromParent, /*InsnID*/0,
4516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4517 // GIR_Coverage, 996,
4518 GIR_Done,
4519 // Label 236: @9782
4520 GIM_Try, /*On fail goto*//*Label 237*/ 9851, // Rule ID 995 //
4521 GIM_CheckFeatures, GIFBS_HasNEON,
4522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4523 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4524 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4525 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4526 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4527 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4528 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4529 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4530 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4531 GIM_CheckIsSafeToFold, /*InsnID*/1,
4532 GIM_CheckIsSafeToFold, /*InsnID*/2,
4533 // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4538 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4539 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4540 GIR_EraseFromParent, /*InsnID*/0,
4541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4542 // GIR_Coverage, 995,
4543 GIR_Done,
4544 // Label 237: @9851
4545 GIM_Try, /*On fail goto*//*Label 238*/ 9920, // Rule ID 987 //
4546 GIM_CheckFeatures, GIFBS_HasNEON,
4547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4548 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4549 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4550 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4551 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4552 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4553 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4554 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4555 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4556 GIM_CheckIsSafeToFold, /*InsnID*/1,
4557 GIM_CheckIsSafeToFold, /*InsnID*/2,
4558 // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
4560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4563 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4564 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4565 GIR_EraseFromParent, /*InsnID*/0,
4566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4567 // GIR_Coverage, 987,
4568 GIR_Done,
4569 // Label 238: @9920
4570 GIM_Try, /*On fail goto*//*Label 239*/ 9989, // Rule ID 994 //
4571 GIM_CheckFeatures, GIFBS_HasNEON,
4572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4573 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4574 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4575 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4576 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4577 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4578 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4579 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4580 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4581 GIM_CheckIsSafeToFold, /*InsnID*/1,
4582 GIM_CheckIsSafeToFold, /*InsnID*/2,
4583 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4588 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4589 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4590 GIR_EraseFromParent, /*InsnID*/0,
4591 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4592 // GIR_Coverage, 994,
4593 GIR_Done,
4594 // Label 239: @9989
4595 GIM_Try, /*On fail goto*//*Label 240*/ 10058, // Rule ID 993 //
4596 GIM_CheckFeatures, GIFBS_HasNEON,
4597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4598 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4599 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4600 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4601 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4602 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4603 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4604 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4605 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4606 GIM_CheckIsSafeToFold, /*InsnID*/1,
4607 GIM_CheckIsSafeToFold, /*InsnID*/2,
4608 // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
4610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4613 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4614 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4615 GIR_EraseFromParent, /*InsnID*/0,
4616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4617 // GIR_Coverage, 993,
4618 GIR_Done,
4619 // Label 240: @10058
4620 GIM_Try, /*On fail goto*//*Label 241*/ 10126, // Rule ID 934 //
4621 GIM_CheckFeatures, GIFBS_HasNEON,
4622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4624 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4625 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4626 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4627 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4628 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4629 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4630 GIM_CheckIsSafeToFold, /*InsnID*/1,
4631 // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
4633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4637 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4638 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4639 GIR_EraseFromParent, /*InsnID*/0,
4640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4641 // GIR_Coverage, 934,
4642 GIR_Done,
4643 // Label 241: @10126
4644 GIM_Try, /*On fail goto*//*Label 242*/ 10182, // Rule ID 1007 //
4645 GIM_CheckFeatures, GIFBS_HasNEON,
4646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4648 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4649 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4650 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4651 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4652 GIM_CheckIsSafeToFold, /*InsnID*/1,
4653 // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
4655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4658 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4659 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4660 GIR_EraseFromParent, /*InsnID*/0,
4661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4662 // GIR_Coverage, 1007,
4663 GIR_Done,
4664 // Label 242: @10182
4665 GIM_Try, /*On fail goto*//*Label 243*/ 10238, // Rule ID 1002 //
4666 GIM_CheckFeatures, GIFBS_HasNEON,
4667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4669 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4670 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4671 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4672 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4673 GIM_CheckIsSafeToFold, /*InsnID*/1,
4674 // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
4676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4679 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4680 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4681 GIR_EraseFromParent, /*InsnID*/0,
4682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4683 // GIR_Coverage, 1002,
4684 GIR_Done,
4685 // Label 243: @10238
4686 GIM_Try, /*On fail goto*//*Label 244*/ 10294, // Rule ID 1006 //
4687 GIM_CheckFeatures, GIFBS_HasNEON,
4688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4690 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4691 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4692 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4693 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4694 GIM_CheckIsSafeToFold, /*InsnID*/1,
4695 // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
4697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4700 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4701 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4702 GIR_EraseFromParent, /*InsnID*/0,
4703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4704 // GIR_Coverage, 1006,
4705 GIR_Done,
4706 // Label 244: @10294
4707 GIM_Try, /*On fail goto*//*Label 245*/ 10337, // Rule ID 979 //
4708 GIM_CheckFeatures, GIFBS_HasNEON,
4709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4712 // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
4714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4717 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4718 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4719 GIR_EraseFromParent, /*InsnID*/0,
4720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4721 // GIR_Coverage, 979,
4722 GIR_Done,
4723 // Label 245: @10337
4724 GIM_Try, /*On fail goto*//*Label 246*/ 10394, // Rule ID 3498 //
4725 GIM_CheckFeatures, GIFBS_HasMVEInt,
4726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
4727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
4728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
4729 // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4730 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4731 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
4732 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
4733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi32,
4734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
4735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
4736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
4737 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4738 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4739 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
4740 GIR_EraseFromParent, /*InsnID*/0,
4741 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4742 // GIR_Coverage, 3498,
4743 GIR_Done,
4744 // Label 246: @10394
4745 GIM_Reject,
4746 // Label 235: @10395
4747 GIM_Reject,
4748 // Label 204: @10396
4749 GIM_Try, /*On fail goto*//*Label 247*/ 10510,
4750 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4751 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4754 GIM_Try, /*On fail goto*//*Label 248*/ 10474, // Rule ID 929 //
4755 GIM_CheckFeatures, GIFBS_HasNEON,
4756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4757 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4758 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4759 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4760 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4761 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4762 GIM_CheckIsSafeToFold, /*InsnID*/1,
4763 // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
4765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4769 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4770 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4771 GIR_EraseFromParent, /*InsnID*/0,
4772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4773 // GIR_Coverage, 929,
4774 GIR_Done,
4775 // Label 248: @10474
4776 GIM_Try, /*On fail goto*//*Label 249*/ 10509, // Rule ID 974 //
4777 GIM_CheckFeatures, GIFBS_HasNEON,
4778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4779 // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
4781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4784 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4785 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4786 GIR_EraseFromParent, /*InsnID*/0,
4787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4788 // GIR_Coverage, 974,
4789 GIR_Done,
4790 // Label 249: @10509
4791 GIM_Reject,
4792 // Label 247: @10510
4793 GIM_Reject,
4794 // Label 205: @10511
4795 GIM_Try, /*On fail goto*//*Label 250*/ 11203,
4796 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4797 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4798 GIM_Try, /*On fail goto*//*Label 251*/ 10590, // Rule ID 992 //
4799 GIM_CheckFeatures, GIFBS_HasNEON,
4800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4801 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4802 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4803 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4804 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4805 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4806 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4807 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4808 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4809 GIM_CheckIsSafeToFold, /*InsnID*/1,
4810 GIM_CheckIsSafeToFold, /*InsnID*/2,
4811 // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4816 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4817 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4818 GIR_EraseFromParent, /*InsnID*/0,
4819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4820 // GIR_Coverage, 992,
4821 GIR_Done,
4822 // Label 251: @10590
4823 GIM_Try, /*On fail goto*//*Label 252*/ 10659, // Rule ID 991 //
4824 GIM_CheckFeatures, GIFBS_HasNEON,
4825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4826 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4827 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4828 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4829 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4830 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4831 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4832 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4833 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4834 GIM_CheckIsSafeToFold, /*InsnID*/1,
4835 GIM_CheckIsSafeToFold, /*InsnID*/2,
4836 // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4841 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4842 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4843 GIR_EraseFromParent, /*InsnID*/0,
4844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4845 // GIR_Coverage, 991,
4846 GIR_Done,
4847 // Label 252: @10659
4848 GIM_Try, /*On fail goto*//*Label 253*/ 10728, // Rule ID 986 //
4849 GIM_CheckFeatures, GIFBS_HasNEON,
4850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4851 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4852 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4853 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4854 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4855 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4856 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
4857 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4858 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4859 GIM_CheckIsSafeToFold, /*InsnID*/1,
4860 GIM_CheckIsSafeToFold, /*InsnID*/2,
4861 // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
4863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4866 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4867 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4868 GIR_EraseFromParent, /*InsnID*/0,
4869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4870 // GIR_Coverage, 986,
4871 GIR_Done,
4872 // Label 253: @10728
4873 GIM_Try, /*On fail goto*//*Label 254*/ 10797, // Rule ID 990 //
4874 GIM_CheckFeatures, GIFBS_HasNEON,
4875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4877 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4878 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4879 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4880 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4881 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
4882 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4883 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4884 GIM_CheckIsSafeToFold, /*InsnID*/1,
4885 GIM_CheckIsSafeToFold, /*InsnID*/2,
4886 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4891 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4892 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4893 GIR_EraseFromParent, /*InsnID*/0,
4894 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4895 // GIR_Coverage, 990,
4896 GIR_Done,
4897 // Label 254: @10797
4898 GIM_Try, /*On fail goto*//*Label 255*/ 10866, // Rule ID 989 //
4899 GIM_CheckFeatures, GIFBS_HasNEON,
4900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4901 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4902 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4903 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4904 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4905 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4906 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
4907 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4908 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4909 GIM_CheckIsSafeToFold, /*InsnID*/1,
4910 GIM_CheckIsSafeToFold, /*InsnID*/2,
4911 // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
4913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4916 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4917 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4918 GIR_EraseFromParent, /*InsnID*/0,
4919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4920 // GIR_Coverage, 989,
4921 GIR_Done,
4922 // Label 255: @10866
4923 GIM_Try, /*On fail goto*//*Label 256*/ 10934, // Rule ID 933 //
4924 GIM_CheckFeatures, GIFBS_HasNEON,
4925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4927 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4928 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
4929 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4930 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4931 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4932 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4933 GIM_CheckIsSafeToFold, /*InsnID*/1,
4934 // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
4936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
4938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4940 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4942 GIR_EraseFromParent, /*InsnID*/0,
4943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4944 // GIR_Coverage, 933,
4945 GIR_Done,
4946 // Label 256: @10934
4947 GIM_Try, /*On fail goto*//*Label 257*/ 10990, // Rule ID 1005 //
4948 GIM_CheckFeatures, GIFBS_HasNEON,
4949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4951 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4952 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
4953 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4954 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4955 GIM_CheckIsSafeToFold, /*InsnID*/1,
4956 // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
4958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4961 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4962 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4963 GIR_EraseFromParent, /*InsnID*/0,
4964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4965 // GIR_Coverage, 1005,
4966 GIR_Done,
4967 // Label 257: @10990
4968 GIM_Try, /*On fail goto*//*Label 258*/ 11046, // Rule ID 1001 //
4969 GIM_CheckFeatures, GIFBS_HasNEON,
4970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4972 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4973 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
4974 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4975 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4976 GIM_CheckIsSafeToFold, /*InsnID*/1,
4977 // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
4979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4982 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4983 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
4984 GIR_EraseFromParent, /*InsnID*/0,
4985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4986 // GIR_Coverage, 1001,
4987 GIR_Done,
4988 // Label 258: @11046
4989 GIM_Try, /*On fail goto*//*Label 259*/ 11102, // Rule ID 1004 //
4990 GIM_CheckFeatures, GIFBS_HasNEON,
4991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4993 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4994 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
4995 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4996 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4997 GIM_CheckIsSafeToFold, /*InsnID*/1,
4998 // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
5000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5003 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5004 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5005 GIR_EraseFromParent, /*InsnID*/0,
5006 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5007 // GIR_Coverage, 1004,
5008 GIR_Done,
5009 // Label 259: @11102
5010 GIM_Try, /*On fail goto*//*Label 260*/ 11145, // Rule ID 978 //
5011 GIM_CheckFeatures, GIFBS_HasNEON,
5012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5015 // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
5017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5020 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5021 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5022 GIR_EraseFromParent, /*InsnID*/0,
5023 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5024 // GIR_Coverage, 978,
5025 GIR_Done,
5026 // Label 260: @11145
5027 GIM_Try, /*On fail goto*//*Label 261*/ 11202, // Rule ID 3494 //
5028 GIM_CheckFeatures, GIFBS_HasMVEInt,
5029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5032 // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5033 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5034 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5035 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi16,
5037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5040 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5041 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5042 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5043 GIR_EraseFromParent, /*InsnID*/0,
5044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5045 // GIR_Coverage, 3494,
5046 GIR_Done,
5047 // Label 261: @11202
5048 GIM_Reject,
5049 // Label 250: @11203
5050 GIM_Reject,
5051 // Label 206: @11204
5052 GIM_Try, /*On fail goto*//*Label 262*/ 11383,
5053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5055 GIM_Try, /*On fail goto*//*Label 263*/ 11282, // Rule ID 932 //
5056 GIM_CheckFeatures, GIFBS_HasNEON,
5057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5060 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
5061 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5062 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5065 GIM_CheckIsSafeToFold, /*InsnID*/1,
5066 // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
5068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
5070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5072 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5073 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5074 GIR_EraseFromParent, /*InsnID*/0,
5075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5076 // GIR_Coverage, 932,
5077 GIR_Done,
5078 // Label 263: @11282
5079 GIM_Try, /*On fail goto*//*Label 264*/ 11325, // Rule ID 977 //
5080 GIM_CheckFeatures, GIFBS_HasNEON,
5081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5084 // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
5086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5089 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5090 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5091 GIR_EraseFromParent, /*InsnID*/0,
5092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5093 // GIR_Coverage, 977,
5094 GIR_Done,
5095 // Label 264: @11325
5096 GIM_Try, /*On fail goto*//*Label 265*/ 11382, // Rule ID 3490 //
5097 GIM_CheckFeatures, GIFBS_HasMVEInt,
5098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5101 // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5102 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5103 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5104 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBi8,
5106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5109 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5110 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5111 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5112 GIR_EraseFromParent, /*InsnID*/0,
5113 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5114 // GIR_Coverage, 3490,
5115 GIR_Done,
5116 // Label 265: @11382
5117 GIM_Reject,
5118 // Label 262: @11383
5119 GIM_Reject,
5120 // Label 207: @11384
5121 GIM_Reject,
5122 // Label 2: @11385
5123 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 273*/ 12216,
5124 /*GILLT_s32*//*Label 266*/ 11405, 0,
5125 /*GILLT_v2s32*//*Label 267*/ 11724, 0, 0,
5126 /*GILLT_v4s16*//*Label 268*/ 11776,
5127 /*GILLT_v4s32*//*Label 269*/ 11828, 0, 0,
5128 /*GILLT_v8s8*//*Label 270*/ 11940,
5129 /*GILLT_v8s16*//*Label 271*/ 11992, 0, 0,
5130 /*GILLT_v16s8*//*Label 272*/ 12104,
5131 // Label 266: @11405
5132 GIM_Try, /*On fail goto*//*Label 274*/ 11723,
5133 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5134 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5135 GIM_Try, /*On fail goto*//*Label 275*/ 11500, // Rule ID 186 //
5136 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
5137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5138 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5139 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5140 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5141 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5142 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5143 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5144 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5145 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5146 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5147 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5148 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5149 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
5150 GIM_CheckIsSafeToFold, /*InsnID*/1,
5151 GIM_CheckIsSafeToFold, /*InsnID*/2,
5152 // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
5154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5157 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5158 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5159 GIR_EraseFromParent, /*InsnID*/0,
5160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5161 // GIR_Coverage, 186,
5162 GIR_Done,
5163 // Label 275: @11500
5164 GIM_Try, /*On fail goto*//*Label 276*/ 11585, // Rule ID 522 //
5165 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5167 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5168 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5169 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5170 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5171 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5172 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5173 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5174 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5175 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5176 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5177 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5178 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
5179 GIM_CheckIsSafeToFold, /*InsnID*/1,
5180 GIM_CheckIsSafeToFold, /*InsnID*/2,
5181 // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
5183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5186 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5187 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5188 GIR_EraseFromParent, /*InsnID*/0,
5189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5190 // GIR_Coverage, 522,
5191 GIR_Done,
5192 // Label 276: @11585
5193 GIM_Try, /*On fail goto*//*Label 277*/ 11632, // Rule ID 169 //
5194 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
5198 // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
5199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
5200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5203 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5204 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5205 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5206 GIR_EraseFromParent, /*InsnID*/0,
5207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5208 // GIR_Coverage, 169,
5209 GIR_Done,
5210 // Label 277: @11632
5211 GIM_Try, /*On fail goto*//*Label 278*/ 11679, // Rule ID 170 //
5212 GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
5213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
5216 // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
5217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
5218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5221 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5222 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5223 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5224 GIR_EraseFromParent, /*InsnID*/0,
5225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5226 // GIR_Coverage, 170,
5227 GIR_Done,
5228 // Label 278: @11679
5229 GIM_Try, /*On fail goto*//*Label 279*/ 11722, // Rule ID 509 //
5230 GIM_CheckFeatures, GIFBS_IsThumb2,
5231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5234 // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
5236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5239 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5240 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5241 GIR_EraseFromParent, /*InsnID*/0,
5242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5243 // GIR_Coverage, 509,
5244 GIR_Done,
5245 // Label 279: @11722
5246 GIM_Reject,
5247 // Label 274: @11723
5248 GIM_Reject,
5249 // Label 267: @11724
5250 GIM_Try, /*On fail goto*//*Label 280*/ 11775, // Rule ID 851 //
5251 GIM_CheckFeatures, GIFBS_HasNEON,
5252 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
5253 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
5254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5257 // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
5259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5262 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5263 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5264 GIR_EraseFromParent, /*InsnID*/0,
5265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5266 // GIR_Coverage, 851,
5267 GIR_Done,
5268 // Label 280: @11775
5269 GIM_Reject,
5270 // Label 268: @11776
5271 GIM_Try, /*On fail goto*//*Label 281*/ 11827, // Rule ID 850 //
5272 GIM_CheckFeatures, GIFBS_HasNEON,
5273 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
5274 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
5275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5278 // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
5280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5283 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5284 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5285 GIR_EraseFromParent, /*InsnID*/0,
5286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5287 // GIR_Coverage, 850,
5288 GIR_Done,
5289 // Label 281: @11827
5290 GIM_Reject,
5291 // Label 269: @11828
5292 GIM_Try, /*On fail goto*//*Label 282*/ 11939,
5293 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
5294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
5295 GIM_Try, /*On fail goto*//*Label 283*/ 11881, // Rule ID 854 //
5296 GIM_CheckFeatures, GIFBS_HasNEON,
5297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5300 // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
5302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5305 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5306 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5307 GIR_EraseFromParent, /*InsnID*/0,
5308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5309 // GIR_Coverage, 854,
5310 GIR_Done,
5311 // Label 283: @11881
5312 GIM_Try, /*On fail goto*//*Label 284*/ 11938, // Rule ID 3456 //
5313 GIM_CheckFeatures, GIFBS_HasMVEInt,
5314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5317 // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5318 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5319 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5320 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi32,
5322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5325 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5326 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5327 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5328 GIR_EraseFromParent, /*InsnID*/0,
5329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5330 // GIR_Coverage, 3456,
5331 GIR_Done,
5332 // Label 284: @11938
5333 GIM_Reject,
5334 // Label 282: @11939
5335 GIM_Reject,
5336 // Label 270: @11940
5337 GIM_Try, /*On fail goto*//*Label 285*/ 11991, // Rule ID 849 //
5338 GIM_CheckFeatures, GIFBS_HasNEON,
5339 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
5340 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
5341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
5342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
5343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
5344 // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
5346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5349 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5350 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5351 GIR_EraseFromParent, /*InsnID*/0,
5352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5353 // GIR_Coverage, 849,
5354 GIR_Done,
5355 // Label 285: @11991
5356 GIM_Reject,
5357 // Label 271: @11992
5358 GIM_Try, /*On fail goto*//*Label 286*/ 12103,
5359 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
5360 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
5361 GIM_Try, /*On fail goto*//*Label 287*/ 12045, // Rule ID 853 //
5362 GIM_CheckFeatures, GIFBS_HasNEON,
5363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5366 // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
5368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5371 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5372 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5373 GIR_EraseFromParent, /*InsnID*/0,
5374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5375 // GIR_Coverage, 853,
5376 GIR_Done,
5377 // Label 287: @12045
5378 GIM_Try, /*On fail goto*//*Label 288*/ 12102, // Rule ID 3452 //
5379 GIM_CheckFeatures, GIFBS_HasMVEInt,
5380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5383 // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5384 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5385 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5386 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi16,
5388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5391 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5392 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5393 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5394 GIR_EraseFromParent, /*InsnID*/0,
5395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5396 // GIR_Coverage, 3452,
5397 GIR_Done,
5398 // Label 288: @12102
5399 GIM_Reject,
5400 // Label 286: @12103
5401 GIM_Reject,
5402 // Label 272: @12104
5403 GIM_Try, /*On fail goto*//*Label 289*/ 12215,
5404 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
5405 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
5406 GIM_Try, /*On fail goto*//*Label 290*/ 12157, // Rule ID 852 //
5407 GIM_CheckFeatures, GIFBS_HasNEON,
5408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
5409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
5410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
5411 // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
5413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5416 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5417 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5418 GIR_EraseFromParent, /*InsnID*/0,
5419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5420 // GIR_Coverage, 852,
5421 GIR_Done,
5422 // Label 290: @12157
5423 GIM_Try, /*On fail goto*//*Label 291*/ 12214, // Rule ID 3448 //
5424 GIM_CheckFeatures, GIFBS_HasMVEInt,
5425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
5426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
5427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
5428 // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5429 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5430 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
5431 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
5432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULi8,
5433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
5434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
5435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
5436 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5437 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5438 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
5439 GIR_EraseFromParent, /*InsnID*/0,
5440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5441 // GIR_Coverage, 3448,
5442 GIR_Done,
5443 // Label 291: @12214
5444 GIM_Reject,
5445 // Label 289: @12215
5446 GIM_Reject,
5447 // Label 273: @12216
5448 GIM_Reject,
5449 // Label 3: @12217
5450 GIM_Try, /*On fail goto*//*Label 292*/ 12318,
5451 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5452 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5453 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5454 GIM_Try, /*On fail goto*//*Label 293*/ 12274, // Rule ID 195 //
5455 GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
5456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5459 // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
5461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5464 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5465 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5466 GIR_EraseFromParent, /*InsnID*/0,
5467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5468 // GIR_Coverage, 195,
5469 GIR_Done,
5470 // Label 293: @12274
5471 GIM_Try, /*On fail goto*//*Label 294*/ 12317, // Rule ID 539 //
5472 GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
5473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5476 // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5477 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
5478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5481 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5482 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5483 GIR_EraseFromParent, /*InsnID*/0,
5484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5485 // GIR_Coverage, 539,
5486 GIR_Done,
5487 // Label 294: @12317
5488 GIM_Reject,
5489 // Label 292: @12318
5490 GIM_Reject,
5491 // Label 4: @12319
5492 GIM_Try, /*On fail goto*//*Label 295*/ 12420,
5493 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
5494 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5495 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5496 GIM_Try, /*On fail goto*//*Label 296*/ 12376, // Rule ID 196 //
5497 GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
5498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5501 // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
5503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5506 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5507 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5508 GIR_EraseFromParent, /*InsnID*/0,
5509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5510 // GIR_Coverage, 196,
5511 GIR_Done,
5512 // Label 296: @12376
5513 GIM_Try, /*On fail goto*//*Label 297*/ 12419, // Rule ID 540 //
5514 GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
5515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5518 // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
5520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
5523 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5524 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5525 GIR_EraseFromParent, /*InsnID*/0,
5526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5527 // GIR_Coverage, 540,
5528 GIR_Done,
5529 // Label 297: @12419
5530 GIM_Reject,
5531 // Label 295: @12420
5532 GIM_Reject,
5533 // Label 5: @12421
5534 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 307*/ 14763,
5535 /*GILLT_s32*//*Label 298*/ 12441, 0,
5536 /*GILLT_v2s32*//*Label 299*/ 14083,
5537 /*GILLT_v2s64*//*Label 300*/ 14135,
5538 /*GILLT_v4s1*//*Label 301*/ 14201, 0,
5539 /*GILLT_v4s32*//*Label 302*/ 14307, 0,
5540 /*GILLT_v8s1*//*Label 303*/ 14419, 0,
5541 /*GILLT_v8s16*//*Label 304*/ 14525, 0,
5542 /*GILLT_v16s1*//*Label 305*/ 14591,
5543 /*GILLT_v16s8*//*Label 306*/ 14697,
5544 // Label 298: @12441
5545 GIM_Try, /*On fail goto*//*Label 308*/ 14082,
5546 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5547 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5548 GIM_Try, /*On fail goto*//*Label 309*/ 12514, // Rule ID 1869 //
5549 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5551 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5552 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
5553 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5554 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5555 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5556 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
5557 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5558 GIM_CheckIsSafeToFold, /*InsnID*/1,
5559 // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
5560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
5561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
5563 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
5564 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5565 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5566 GIR_EraseFromParent, /*InsnID*/0,
5567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5568 // GIR_Coverage, 1869,
5569 GIR_Done,
5570 // Label 309: @12514
5571 GIM_Try, /*On fail goto*//*Label 310*/ 12577, // Rule ID 2105 //
5572 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5574 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5575 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
5576 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5577 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5578 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5579 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
5580 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5581 GIM_CheckIsSafeToFold, /*InsnID*/1,
5582 // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
5583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
5584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
5586 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
5587 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5588 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5589 GIR_EraseFromParent, /*InsnID*/0,
5590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5591 // GIR_Coverage, 2105,
5592 GIR_Done,
5593 // Label 310: @12577
5594 GIM_Try, /*On fail goto*//*Label 311*/ 12619, // Rule ID 1996 //
5595 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5598 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
5599 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
5601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5603 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5604 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5605 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5606 GIR_EraseFromParent, /*InsnID*/0,
5607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5608 // GIR_Coverage, 1996,
5609 GIR_Done,
5610 // Label 311: @12619
5611 GIM_Try, /*On fail goto*//*Label 312*/ 12661, // Rule ID 1997 //
5612 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5615 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
5616 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5617 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
5618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5620 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5621 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5622 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5623 GIR_EraseFromParent, /*InsnID*/0,
5624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5625 // GIR_Coverage, 1997,
5626 GIR_Done,
5627 // Label 312: @12661
5628 GIM_Try, /*On fail goto*//*Label 313*/ 12703, // Rule ID 1998 //
5629 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5632 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5633 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
5634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
5635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
5637 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5638 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5639 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5640 GIR_EraseFromParent, /*InsnID*/0,
5641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5642 // GIR_Coverage, 1998,
5643 GIR_Done,
5644 // Label 313: @12703
5645 GIM_Try, /*On fail goto*//*Label 314*/ 12745, // Rule ID 2214 //
5646 GIM_CheckFeatures, GIFBS_IsThumb2,
5647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5649 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
5650 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
5652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5654 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5655 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5656 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5657 GIR_EraseFromParent, /*InsnID*/0,
5658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5659 // GIR_Coverage, 2214,
5660 GIR_Done,
5661 // Label 314: @12745
5662 GIM_Try, /*On fail goto*//*Label 315*/ 12787, // Rule ID 2215 //
5663 GIM_CheckFeatures, GIFBS_IsThumb2,
5664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5666 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
5667 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
5669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5671 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5672 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5673 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5674 GIR_EraseFromParent, /*InsnID*/0,
5675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5676 // GIR_Coverage, 2215,
5677 GIR_Done,
5678 // Label 315: @12787
5679 GIM_Try, /*On fail goto*//*Label 316*/ 12829, // Rule ID 2216 //
5680 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5683 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
5684 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
5686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
5688 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5689 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5690 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5691 GIR_EraseFromParent, /*InsnID*/0,
5692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5693 // GIR_Coverage, 2216,
5694 GIR_Done,
5695 // Label 316: @12829
5696 GIM_Try, /*On fail goto*//*Label 317*/ 12904, // Rule ID 5312 //
5697 GIM_CheckFeatures, GIFBS_IsARM,
5698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5699 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5700 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5701 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5702 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5703 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5704 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5705 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5706 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5707 // MIs[2] Operand 1
5708 // No operand predicates
5709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5710 GIM_CheckIsSafeToFold, /*InsnID*/1,
5711 GIM_CheckIsSafeToFold, /*InsnID*/2,
5712 // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5716 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5717 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5718 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5719 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5720 GIR_EraseFromParent, /*InsnID*/0,
5721 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5722 // GIR_Coverage, 5312,
5723 GIR_Done,
5724 // Label 317: @12904
5725 GIM_Try, /*On fail goto*//*Label 318*/ 12979, // Rule ID 5345 //
5726 GIM_CheckFeatures, GIFBS_IsThumb2,
5727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5728 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5729 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5730 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5732 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5733 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5734 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5735 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5736 // MIs[2] Operand 1
5737 // No operand predicates
5738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5739 GIM_CheckIsSafeToFold, /*InsnID*/1,
5740 GIM_CheckIsSafeToFold, /*InsnID*/2,
5741 // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5745 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5746 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5747 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5748 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5749 GIR_EraseFromParent, /*InsnID*/0,
5750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5751 // GIR_Coverage, 5345,
5752 GIR_Done,
5753 // Label 318: @12979
5754 GIM_Try, /*On fail goto*//*Label 319*/ 13054, // Rule ID 5311 //
5755 GIM_CheckFeatures, GIFBS_IsARM,
5756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5757 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5758 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5759 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5760 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5761 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5762 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5763 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5764 // MIs[2] Operand 1
5765 // No operand predicates
5766 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5768 GIM_CheckIsSafeToFold, /*InsnID*/1,
5769 GIM_CheckIsSafeToFold, /*InsnID*/2,
5770 // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5774 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5775 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5776 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5777 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5778 GIR_EraseFromParent, /*InsnID*/0,
5779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5780 // GIR_Coverage, 5311,
5781 GIR_Done,
5782 // Label 319: @13054
5783 GIM_Try, /*On fail goto*//*Label 320*/ 13129, // Rule ID 5344 //
5784 GIM_CheckFeatures, GIFBS_IsThumb2,
5785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5787 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5788 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5789 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5790 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5791 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5792 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5793 // MIs[2] Operand 1
5794 // No operand predicates
5795 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5797 GIM_CheckIsSafeToFold, /*InsnID*/1,
5798 GIM_CheckIsSafeToFold, /*InsnID*/2,
5799 // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5803 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5804 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5805 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5806 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5807 GIR_EraseFromParent, /*InsnID*/0,
5808 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5809 // GIR_Coverage, 5344,
5810 GIR_Done,
5811 // Label 320: @13129
5812 GIM_Try, /*On fail goto*//*Label 321*/ 13204, // Rule ID 5310 //
5813 GIM_CheckFeatures, GIFBS_IsARM,
5814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5817 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5818 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5819 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5820 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5821 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5822 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5823 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5824 // MIs[2] Operand 1
5825 // No operand predicates
5826 GIM_CheckIsSafeToFold, /*InsnID*/1,
5827 GIM_CheckIsSafeToFold, /*InsnID*/2,
5828 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5832 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5833 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5834 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5835 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5836 GIR_EraseFromParent, /*InsnID*/0,
5837 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5838 // GIR_Coverage, 5310,
5839 GIR_Done,
5840 // Label 321: @13204
5841 GIM_Try, /*On fail goto*//*Label 322*/ 13279, // Rule ID 5343 //
5842 GIM_CheckFeatures, GIFBS_IsThumb2,
5843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5845 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5846 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5847 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5848 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5849 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
5850 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5851 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5852 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5853 // MIs[2] Operand 1
5854 // No operand predicates
5855 GIM_CheckIsSafeToFold, /*InsnID*/1,
5856 GIM_CheckIsSafeToFold, /*InsnID*/2,
5857 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5861 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5862 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5863 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5864 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5865 GIR_EraseFromParent, /*InsnID*/0,
5866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5867 // GIR_Coverage, 5343,
5868 GIR_Done,
5869 // Label 322: @13279
5870 GIM_Try, /*On fail goto*//*Label 323*/ 13354, // Rule ID 159 //
5871 GIM_CheckFeatures, GIFBS_IsARM,
5872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5875 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5876 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5877 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5878 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5879 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5880 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
5881 // MIs[2] Operand 1
5882 // No operand predicates
5883 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5884 GIM_CheckIsSafeToFold, /*InsnID*/1,
5885 GIM_CheckIsSafeToFold, /*InsnID*/2,
5886 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
5888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5890 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5891 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5892 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5893 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5894 GIR_EraseFromParent, /*InsnID*/0,
5895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5896 // GIR_Coverage, 159,
5897 GIR_Done,
5898 // Label 323: @13354
5899 GIM_Try, /*On fail goto*//*Label 324*/ 13429, // Rule ID 497 //
5900 GIM_CheckFeatures, GIFBS_IsThumb2,
5901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5903 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5904 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5905 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5906 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5907 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5908 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
5909 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
5910 // MIs[2] Operand 1
5911 // No operand predicates
5912 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5913 GIM_CheckIsSafeToFold, /*InsnID*/1,
5914 GIM_CheckIsSafeToFold, /*InsnID*/2,
5915 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
5917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5919 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
5920 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5921 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5922 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5923 GIR_EraseFromParent, /*InsnID*/0,
5924 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5925 // GIR_Coverage, 497,
5926 GIR_Done,
5927 // Label 324: @13429
5928 GIM_Try, /*On fail goto*//*Label 325*/ 13497, // Rule ID 5313 //
5929 GIM_CheckFeatures, GIFBS_IsARM,
5930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5932 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5933 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5934 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5935 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5936 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
5938 GIM_CheckIsSafeToFold, /*InsnID*/1,
5939 // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5940 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5944 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5945 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5946 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5947 GIR_EraseFromParent, /*InsnID*/0,
5948 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5949 // GIR_Coverage, 5313,
5950 GIR_Done,
5951 // Label 325: @13497
5952 GIM_Try, /*On fail goto*//*Label 326*/ 13565, // Rule ID 5346 //
5953 GIM_CheckFeatures, GIFBS_IsThumb2,
5954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5955 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5956 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5957 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5958 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5959 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5960 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
5962 GIM_CheckIsSafeToFold, /*InsnID*/1,
5963 // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
5965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
5967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5968 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5969 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5970 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5971 GIR_EraseFromParent, /*InsnID*/0,
5972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5973 // GIR_Coverage, 5346,
5974 GIR_Done,
5975 // Label 326: @13565
5976 GIM_Try, /*On fail goto*//*Label 327*/ 13633, // Rule ID 160 //
5977 GIM_CheckFeatures, GIFBS_IsARM,
5978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5980 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5981 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
5982 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5983 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5984 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5985 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
5986 GIM_CheckIsSafeToFold, /*InsnID*/1,
5987 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
5989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
5991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5992 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5993 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5994 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
5995 GIR_EraseFromParent, /*InsnID*/0,
5996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5997 // GIR_Coverage, 160,
5998 GIR_Done,
5999 // Label 327: @13633
6000 GIM_Try, /*On fail goto*//*Label 328*/ 13701, // Rule ID 498 //
6001 GIM_CheckFeatures, GIFBS_IsThumb2,
6002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6004 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6005 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6006 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6007 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6008 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6009 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6010 GIM_CheckIsSafeToFold, /*InsnID*/1,
6011 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
6013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6016 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6017 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6018 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6019 GIR_EraseFromParent, /*InsnID*/0,
6020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6021 // GIR_Coverage, 498,
6022 GIR_Done,
6023 // Label 328: @13701
6024 GIM_Try, /*On fail goto*//*Label 329*/ 13740, // Rule ID 352 //
6025 GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
6026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
6027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
6028 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
6029 // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTB,
6031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6033 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6034 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6035 GIR_EraseFromParent, /*InsnID*/0,
6036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6037 // GIR_Coverage, 352,
6038 GIR_Done,
6039 // Label 329: @13740
6040 GIM_Try, /*On fail goto*//*Label 330*/ 13779, // Rule ID 353 //
6041 GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
6042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
6043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
6044 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
6045 // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTH,
6047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6049 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6050 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6051 GIR_EraseFromParent, /*InsnID*/0,
6052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6053 // GIR_Coverage, 353,
6054 GIR_Done,
6055 // Label 330: @13779
6056 GIM_Try, /*On fail goto*//*Label 331*/ 13833, // Rule ID 147 //
6057 GIM_CheckFeatures, GIFBS_IsARM,
6058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6060 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6061 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6062 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
6063 // MIs[1] Operand 1
6064 // No operand predicates
6065 GIM_CheckIsSafeToFold, /*InsnID*/1,
6066 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri,
6068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6070 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6071 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6072 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6073 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6074 GIR_EraseFromParent, /*InsnID*/0,
6075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6076 // GIR_Coverage, 147,
6077 GIR_Done,
6078 // Label 331: @13833
6079 GIM_Try, /*On fail goto*//*Label 332*/ 13887, // Rule ID 488 //
6080 GIM_CheckFeatures, GIFBS_IsThumb2,
6081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6083 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6084 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6085 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6086 // MIs[1] Operand 1
6087 // No operand predicates
6088 GIM_CheckIsSafeToFold, /*InsnID*/1,
6089 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDri,
6091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6093 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6094 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6095 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6096 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6097 GIR_EraseFromParent, /*InsnID*/0,
6098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6099 // GIR_Coverage, 488,
6100 GIR_Done,
6101 // Label 332: @13887
6102 GIM_Try, /*On fail goto*//*Label 333*/ 13937, // Rule ID 163 //
6103 GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
6104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6106 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6107 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6108 // MIs[1] Operand 1
6109 // No operand predicates
6110 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
6111 GIM_CheckIsSafeToFold, /*InsnID*/1,
6112 // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
6113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BFC,
6114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6116 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6117 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6118 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6119 GIR_EraseFromParent, /*InsnID*/0,
6120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6121 // GIR_Coverage, 163,
6122 GIR_Done,
6123 // Label 333: @13937
6124 GIM_Try, /*On fail goto*//*Label 334*/ 13987, // Rule ID 500 //
6125 GIM_CheckFeatures, GIFBS_IsThumb2,
6126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6128 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6129 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6130 // MIs[1] Operand 1
6131 // No operand predicates
6132 GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
6133 GIM_CheckIsSafeToFold, /*InsnID*/1,
6134 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
6135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BFC,
6136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6138 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6139 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6140 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6141 GIR_EraseFromParent, /*InsnID*/0,
6142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6143 // GIR_Coverage, 500,
6144 GIR_Done,
6145 // Label 334: @13987
6146 GIM_Try, /*On fail goto*//*Label 335*/ 14034, // Rule ID 148 //
6147 GIM_CheckFeatures, GIFBS_IsARM,
6148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
6151 // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDrr,
6153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6156 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6157 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6158 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6159 GIR_EraseFromParent, /*InsnID*/0,
6160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6161 // GIR_Coverage, 148,
6162 GIR_Done,
6163 // Label 335: @14034
6164 GIM_Try, /*On fail goto*//*Label 336*/ 14081, // Rule ID 489 //
6165 GIM_CheckFeatures, GIFBS_IsThumb2,
6166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6169 // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr,
6171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6174 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6175 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6176 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6177 GIR_EraseFromParent, /*InsnID*/0,
6178 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6179 // GIR_Coverage, 489,
6180 GIR_Done,
6181 // Label 336: @14081
6182 GIM_Reject,
6183 // Label 308: @14082
6184 GIM_Reject,
6185 // Label 299: @14083
6186 GIM_Try, /*On fail goto*//*Label 337*/ 14134, // Rule ID 1147 //
6187 GIM_CheckFeatures, GIFBS_HasNEON,
6188 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6189 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
6190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6193 // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
6195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6198 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6199 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6200 GIR_EraseFromParent, /*InsnID*/0,
6201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6202 // GIR_Coverage, 1147,
6203 GIR_Done,
6204 // Label 337: @14134
6205 GIM_Reject,
6206 // Label 300: @14135
6207 GIM_Try, /*On fail goto*//*Label 338*/ 14200, // Rule ID 3364 //
6208 GIM_CheckFeatures, GIFBS_HasMVEInt,
6209 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
6210 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
6211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6214 // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
6215 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6216 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6217 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6222 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6223 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6224 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6225 GIR_EraseFromParent, /*InsnID*/0,
6226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6227 // GIR_Coverage, 3364,
6228 GIR_Done,
6229 // Label 338: @14200
6230 GIM_Reject,
6231 // Label 301: @14201
6232 GIM_Try, /*On fail goto*//*Label 339*/ 14306, // Rule ID 1844 //
6233 GIM_CheckFeatures, GIFBS_HasMVEInt,
6234 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
6235 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
6236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6239 // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6240 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6241 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6242 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6243 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6244 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6245 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6246 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6248 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6249 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6250 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6251 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6252 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6253 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6254 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6255 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6256 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6257 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6258 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6261 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6262 GIR_EraseFromParent, /*InsnID*/0,
6263 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6264 // GIR_Coverage, 1844,
6265 GIR_Done,
6266 // Label 339: @14306
6267 GIM_Reject,
6268 // Label 302: @14307
6269 GIM_Try, /*On fail goto*//*Label 340*/ 14418,
6270 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
6271 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6272 GIM_Try, /*On fail goto*//*Label 341*/ 14360, // Rule ID 1148 //
6273 GIM_CheckFeatures, GIFBS_HasNEON,
6274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6277 // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
6279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6282 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6283 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6284 GIR_EraseFromParent, /*InsnID*/0,
6285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6286 // GIR_Coverage, 1148,
6287 GIR_Done,
6288 // Label 341: @14360
6289 GIM_Try, /*On fail goto*//*Label 342*/ 14417, // Rule ID 3360 //
6290 GIM_CheckFeatures, GIFBS_HasMVEInt,
6291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6294 // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6295 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6296 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6297 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6302 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6303 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6304 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6305 GIR_EraseFromParent, /*InsnID*/0,
6306 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6307 // GIR_Coverage, 3360,
6308 GIR_Done,
6309 // Label 342: @14417
6310 GIM_Reject,
6311 // Label 340: @14418
6312 GIM_Reject,
6313 // Label 303: @14419
6314 GIM_Try, /*On fail goto*//*Label 343*/ 14524, // Rule ID 1845 //
6315 GIM_CheckFeatures, GIFBS_HasMVEInt,
6316 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
6317 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
6318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6321 // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6322 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6323 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6324 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6325 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6326 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6327 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6328 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6329 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6330 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6331 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6332 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6333 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6334 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6335 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6336 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6337 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6338 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6339 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6340 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6343 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6344 GIR_EraseFromParent, /*InsnID*/0,
6345 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6346 // GIR_Coverage, 1845,
6347 GIR_Done,
6348 // Label 343: @14524
6349 GIM_Reject,
6350 // Label 304: @14525
6351 GIM_Try, /*On fail goto*//*Label 344*/ 14590, // Rule ID 3356 //
6352 GIM_CheckFeatures, GIFBS_HasMVEInt,
6353 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
6354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
6355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6358 // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6359 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6360 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6361 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6366 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6367 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6368 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6369 GIR_EraseFromParent, /*InsnID*/0,
6370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6371 // GIR_Coverage, 3356,
6372 GIR_Done,
6373 // Label 344: @14590
6374 GIM_Reject,
6375 // Label 305: @14591
6376 GIM_Try, /*On fail goto*//*Label 345*/ 14696, // Rule ID 1843 //
6377 GIM_CheckFeatures, GIFBS_HasMVEInt,
6378 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
6379 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
6380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
6381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
6382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
6383 // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
6384 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6385 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
6386 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
6387 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6388 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
6389 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
6390 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
6391 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6392 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
6393 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
6394 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
6395 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ANDrr,
6396 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
6397 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
6398 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
6399 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
6400 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6401 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6402 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6405 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6406 GIR_EraseFromParent, /*InsnID*/0,
6407 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
6408 // GIR_Coverage, 1843,
6409 GIR_Done,
6410 // Label 345: @14696
6411 GIM_Reject,
6412 // Label 306: @14697
6413 GIM_Try, /*On fail goto*//*Label 346*/ 14762, // Rule ID 3352 //
6414 GIM_CheckFeatures, GIFBS_HasMVEInt,
6415 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
6416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
6417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
6418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
6419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
6420 // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6421 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
6423 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
6424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VAND,
6425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
6426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
6427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
6428 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
6429 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6430 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
6431 GIR_EraseFromParent, /*InsnID*/0,
6432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6433 // GIR_Coverage, 3352,
6434 GIR_Done,
6435 // Label 346: @14762
6436 GIM_Reject,
6437 // Label 307: @14763
6438 GIM_Reject,
6439 // Label 6: @14764
6440 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 356*/ 19586,
6441 /*GILLT_s32*//*Label 347*/ 14784, 0,
6442 /*GILLT_v2s32*//*Label 348*/ 18906,
6443 /*GILLT_v2s64*//*Label 349*/ 18958,
6444 /*GILLT_v4s1*//*Label 350*/ 19024, 0,
6445 /*GILLT_v4s32*//*Label 351*/ 19130, 0,
6446 /*GILLT_v8s1*//*Label 352*/ 19242, 0,
6447 /*GILLT_v8s16*//*Label 353*/ 19348, 0,
6448 /*GILLT_v16s1*//*Label 354*/ 19414,
6449 /*GILLT_v16s8*//*Label 355*/ 19520,
6450 // Label 347: @14784
6451 GIM_Try, /*On fail goto*//*Label 357*/ 18905,
6452 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
6453 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6454 GIM_Try, /*On fail goto*//*Label 358*/ 14914, // Rule ID 5528 //
6455 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6457 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6458 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6459 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6460 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6461 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6462 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6463 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6464 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6465 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6466 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
6467 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
6468 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6469 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6470 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6471 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6472 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6473 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
6474 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6475 // MIs[4] Rm
6476 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6477 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
6478 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
6479 GIM_CheckIsSafeToFold, /*InsnID*/1,
6480 GIM_CheckIsSafeToFold, /*InsnID*/2,
6481 GIM_CheckIsSafeToFold, /*InsnID*/3,
6482 GIM_CheckIsSafeToFold, /*InsnID*/4,
6483 // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
6485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6487 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6488 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6489 GIR_EraseFromParent, /*InsnID*/0,
6490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6491 // GIR_Coverage, 5528,
6492 GIR_Done,
6493 // Label 358: @14914
6494 GIM_Try, /*On fail goto*//*Label 359*/ 15034, // Rule ID 5570 //
6495 GIM_CheckFeatures, GIFBS_IsThumb2,
6496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6497 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6498 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6499 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6500 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6501 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6502 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6503 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6504 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6505 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6506 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
6507 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
6508 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6509 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6510 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6511 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6512 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6513 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
6514 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6515 // MIs[4] Rm
6516 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6517 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
6518 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
6519 GIM_CheckIsSafeToFold, /*InsnID*/1,
6520 GIM_CheckIsSafeToFold, /*InsnID*/2,
6521 GIM_CheckIsSafeToFold, /*InsnID*/3,
6522 GIM_CheckIsSafeToFold, /*InsnID*/4,
6523 // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
6525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6527 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6528 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6529 GIR_EraseFromParent, /*InsnID*/0,
6530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6531 // GIR_Coverage, 5570,
6532 GIR_Done,
6533 // Label 359: @15034
6534 GIM_Try, /*On fail goto*//*Label 360*/ 15154, // Rule ID 1927 //
6535 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6537 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6538 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6539 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6540 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6541 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6542 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6543 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6544 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6545 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6546 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
6547 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
6548 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6549 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6550 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6551 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6552 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6553 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
6554 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6555 // MIs[4] Rm
6556 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6557 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
6558 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
6559 GIM_CheckIsSafeToFold, /*InsnID*/1,
6560 GIM_CheckIsSafeToFold, /*InsnID*/2,
6561 GIM_CheckIsSafeToFold, /*InsnID*/3,
6562 GIM_CheckIsSafeToFold, /*InsnID*/4,
6563 // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6564 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
6565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6567 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6568 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6569 GIR_EraseFromParent, /*InsnID*/0,
6570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6571 // GIR_Coverage, 1927,
6572 GIR_Done,
6573 // Label 360: @15154
6574 GIM_Try, /*On fail goto*//*Label 361*/ 15274, // Rule ID 2187 //
6575 GIM_CheckFeatures, GIFBS_IsThumb2,
6576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6578 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6579 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6580 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6581 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6582 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6583 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6584 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6585 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6586 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
6587 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
6588 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6589 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6590 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6591 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6592 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
6593 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
6594 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6595 // MIs[4] Rm
6596 GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
6597 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
6598 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
6599 GIM_CheckIsSafeToFold, /*InsnID*/1,
6600 GIM_CheckIsSafeToFold, /*InsnID*/2,
6601 GIM_CheckIsSafeToFold, /*InsnID*/3,
6602 GIM_CheckIsSafeToFold, /*InsnID*/4,
6603 // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
6605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6607 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6608 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6609 GIR_EraseFromParent, /*InsnID*/0,
6610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6611 // GIR_Coverage, 2187,
6612 GIR_Done,
6613 // Label 361: @15274
6614 GIM_Try, /*On fail goto*//*Label 362*/ 15391, // Rule ID 5326 //
6615 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6617 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6618 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6619 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6620 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6621 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6622 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6623 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6624 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6625 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6626 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6627 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6628 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6629 // MIs[3] Operand 1
6630 // No operand predicates
6631 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6632 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6633 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6634 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6635 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6636 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6637 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6638 GIM_CheckIsSafeToFold, /*InsnID*/1,
6639 GIM_CheckIsSafeToFold, /*InsnID*/2,
6640 GIM_CheckIsSafeToFold, /*InsnID*/3,
6641 GIM_CheckIsSafeToFold, /*InsnID*/4,
6642 // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6647 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6648 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6649 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6650 GIR_EraseFromParent, /*InsnID*/0,
6651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6652 // GIR_Coverage, 5326,
6653 GIR_Done,
6654 // Label 362: @15391
6655 GIM_Try, /*On fail goto*//*Label 363*/ 15508, // Rule ID 5363 //
6656 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6658 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6659 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6660 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6661 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6662 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6663 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6664 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6665 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6666 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6667 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6668 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6669 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6670 // MIs[3] Operand 1
6671 // No operand predicates
6672 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6673 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6674 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6675 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6676 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6677 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6678 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6679 GIM_CheckIsSafeToFold, /*InsnID*/1,
6680 GIM_CheckIsSafeToFold, /*InsnID*/2,
6681 GIM_CheckIsSafeToFold, /*InsnID*/3,
6682 GIM_CheckIsSafeToFold, /*InsnID*/4,
6683 // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6688 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6689 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6690 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6691 GIR_EraseFromParent, /*InsnID*/0,
6692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6693 // GIR_Coverage, 5363,
6694 GIR_Done,
6695 // Label 363: @15508
6696 GIM_Try, /*On fail goto*//*Label 364*/ 15625, // Rule ID 5533 //
6697 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6699 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6700 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6701 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6702 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6703 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6704 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6705 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6706 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6707 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6708 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6709 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6710 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6711 // MIs[3] Operand 1
6712 // No operand predicates
6713 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6714 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6715 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6716 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6717 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6718 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6719 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6720 GIM_CheckIsSafeToFold, /*InsnID*/1,
6721 GIM_CheckIsSafeToFold, /*InsnID*/2,
6722 GIM_CheckIsSafeToFold, /*InsnID*/3,
6723 GIM_CheckIsSafeToFold, /*InsnID*/4,
6724 // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6725 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6729 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6730 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6731 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6732 GIR_EraseFromParent, /*InsnID*/0,
6733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6734 // GIR_Coverage, 5533,
6735 GIR_Done,
6736 // Label 364: @15625
6737 GIM_Try, /*On fail goto*//*Label 365*/ 15742, // Rule ID 5575 //
6738 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6740 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6741 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6742 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6743 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6744 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6745 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
6746 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6747 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6748 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6749 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6750 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6751 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6752 // MIs[3] Operand 1
6753 // No operand predicates
6754 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
6755 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6756 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6757 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6758 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6759 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6760 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
6761 GIM_CheckIsSafeToFold, /*InsnID*/1,
6762 GIM_CheckIsSafeToFold, /*InsnID*/2,
6763 GIM_CheckIsSafeToFold, /*InsnID*/3,
6764 GIM_CheckIsSafeToFold, /*InsnID*/4,
6765 // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
6769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6770 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6771 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6772 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6773 GIR_EraseFromParent, /*InsnID*/0,
6774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6775 // GIR_Coverage, 5575,
6776 GIR_Done,
6777 // Label 365: @15742
6778 GIM_Try, /*On fail goto*//*Label 366*/ 15859, // Rule ID 5325 //
6779 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6781 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6782 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6783 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6784 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6785 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6786 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6787 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6788 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6789 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6790 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6791 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6792 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6793 // MIs[3] Operand 1
6794 // No operand predicates
6795 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6796 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6797 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6798 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6799 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6800 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6801 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
6802 GIM_CheckIsSafeToFold, /*InsnID*/1,
6803 GIM_CheckIsSafeToFold, /*InsnID*/2,
6804 GIM_CheckIsSafeToFold, /*InsnID*/3,
6805 GIM_CheckIsSafeToFold, /*InsnID*/4,
6806 // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6811 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6812 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6813 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6814 GIR_EraseFromParent, /*InsnID*/0,
6815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6816 // GIR_Coverage, 5325,
6817 GIR_Done,
6818 // Label 366: @15859
6819 GIM_Try, /*On fail goto*//*Label 367*/ 15976, // Rule ID 5362 //
6820 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6822 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6823 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6824 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6825 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6826 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6827 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
6828 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6829 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6830 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6831 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
6832 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
6833 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
6834 // MIs[3] Operand 1
6835 // No operand predicates
6836 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6837 GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
6838 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
6839 GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
6840 GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
6841 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6842 GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
6843 GIM_CheckIsSafeToFold, /*InsnID*/1,
6844 GIM_CheckIsSafeToFold, /*InsnID*/2,
6845 GIM_CheckIsSafeToFold, /*InsnID*/3,
6846 GIM_CheckIsSafeToFold, /*InsnID*/4,
6847 // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
6851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6852 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
6853 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6854 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6855 GIR_EraseFromParent, /*InsnID*/0,
6856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6857 // GIR_Coverage, 5362,
6858 GIR_Done,
6859 // Label 367: @15976
6860 GIM_Try, /*On fail goto*//*Label 368*/ 16093, // Rule ID 203 //
6861 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6863 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6864 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6865 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6866 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6867 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6868 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6869 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6870 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6871 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6872 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6873 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6874 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6875 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6876 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6877 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6878 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6879 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6880 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6881 // MIs[4] Operand 1
6882 // No operand predicates
6883 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6884 GIM_CheckIsSafeToFold, /*InsnID*/1,
6885 GIM_CheckIsSafeToFold, /*InsnID*/2,
6886 GIM_CheckIsSafeToFold, /*InsnID*/3,
6887 GIM_CheckIsSafeToFold, /*InsnID*/4,
6888 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
6893 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6894 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6895 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6896 GIR_EraseFromParent, /*InsnID*/0,
6897 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6898 // GIR_Coverage, 203,
6899 GIR_Done,
6900 // Label 368: @16093
6901 GIM_Try, /*On fail goto*//*Label 369*/ 16210, // Rule ID 547 //
6902 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6905 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6906 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6907 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6908 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6909 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6910 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6911 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6912 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6913 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6914 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6915 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6916 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6917 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6918 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6919 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6920 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6921 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
6922 // MIs[4] Operand 1
6923 // No operand predicates
6924 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6925 GIM_CheckIsSafeToFold, /*InsnID*/1,
6926 GIM_CheckIsSafeToFold, /*InsnID*/2,
6927 GIM_CheckIsSafeToFold, /*InsnID*/3,
6928 GIM_CheckIsSafeToFold, /*InsnID*/4,
6929 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
6930 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
6934 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6935 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6936 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6937 GIR_EraseFromParent, /*InsnID*/0,
6938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6939 // GIR_Coverage, 547,
6940 GIR_Done,
6941 // Label 369: @16210
6942 GIM_Try, /*On fail goto*//*Label 370*/ 16327, // Rule ID 1932 //
6943 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6945 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6946 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6947 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6948 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6949 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6950 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6951 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6952 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6953 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6954 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6955 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6956 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
6957 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6958 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6959 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6960 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
6961 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
6962 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
6963 // MIs[4] Operand 1
6964 // No operand predicates
6965 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
6966 GIM_CheckIsSafeToFold, /*InsnID*/1,
6967 GIM_CheckIsSafeToFold, /*InsnID*/2,
6968 GIM_CheckIsSafeToFold, /*InsnID*/3,
6969 GIM_CheckIsSafeToFold, /*InsnID*/4,
6970 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
6971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
6975 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
6976 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6977 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
6978 GIR_EraseFromParent, /*InsnID*/0,
6979 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6980 // GIR_Coverage, 1932,
6981 GIR_Done,
6982 // Label 370: @16327
6983 GIM_Try, /*On fail goto*//*Label 371*/ 16444, // Rule ID 2192 //
6984 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6986 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6987 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
6988 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6989 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6990 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6991 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
6992 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6993 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
6994 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6995 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6996 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
6997 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
6998 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6999 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7000 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7001 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7002 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7003 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
7004 // MIs[4] Operand 1
7005 // No operand predicates
7006 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7007 GIM_CheckIsSafeToFold, /*InsnID*/1,
7008 GIM_CheckIsSafeToFold, /*InsnID*/2,
7009 GIM_CheckIsSafeToFold, /*InsnID*/3,
7010 GIM_CheckIsSafeToFold, /*InsnID*/4,
7011 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7016 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7017 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7018 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7019 GIR_EraseFromParent, /*InsnID*/0,
7020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7021 // GIR_Coverage, 2192,
7022 GIR_Done,
7023 // Label 371: @16444
7024 GIM_Try, /*On fail goto*//*Label 372*/ 16561, // Rule ID 202 //
7025 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7027 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7028 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7029 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7030 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7031 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7032 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7033 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7034 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7035 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7036 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7037 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7038 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
7039 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7040 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7041 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7042 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7043 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7044 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
7045 // MIs[4] Operand 1
7046 // No operand predicates
7047 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7048 GIM_CheckIsSafeToFold, /*InsnID*/1,
7049 GIM_CheckIsSafeToFold, /*InsnID*/2,
7050 GIM_CheckIsSafeToFold, /*InsnID*/3,
7051 GIM_CheckIsSafeToFold, /*InsnID*/4,
7052 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7057 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7058 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7059 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7060 GIR_EraseFromParent, /*InsnID*/0,
7061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7062 // GIR_Coverage, 202,
7063 GIR_Done,
7064 // Label 372: @16561
7065 GIM_Try, /*On fail goto*//*Label 373*/ 16678, // Rule ID 546 //
7066 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7068 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7069 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7070 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7071 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7072 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7073 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7074 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7075 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7076 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7077 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7078 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7079 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
7080 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7081 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7082 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7083 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7084 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
7085 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
7086 // MIs[4] Operand 1
7087 // No operand predicates
7088 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7089 GIM_CheckIsSafeToFold, /*InsnID*/1,
7090 GIM_CheckIsSafeToFold, /*InsnID*/2,
7091 GIM_CheckIsSafeToFold, /*InsnID*/3,
7092 GIM_CheckIsSafeToFold, /*InsnID*/4,
7093 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7098 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7099 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7100 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7101 GIR_EraseFromParent, /*InsnID*/0,
7102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7103 // GIR_Coverage, 546,
7104 GIR_Done,
7105 // Label 373: @16678
7106 GIM_Try, /*On fail goto*//*Label 374*/ 16766, // Rule ID 1928 //
7107 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7109 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7110 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7111 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7112 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7113 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7114 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7115 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7116 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7117 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7118 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7119 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7120 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7121 GIM_CheckIsSafeToFold, /*InsnID*/1,
7122 GIM_CheckIsSafeToFold, /*InsnID*/2,
7123 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
7124 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7128 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7129 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7130 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7131 GIR_EraseFromParent, /*InsnID*/0,
7132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7133 // GIR_Coverage, 1928,
7134 GIR_Done,
7135 // Label 374: @16766
7136 GIM_Try, /*On fail goto*//*Label 375*/ 16854, // Rule ID 2188 //
7137 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7140 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7141 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7142 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7144 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7145 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7146 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7147 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7148 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7149 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7150 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
7151 GIM_CheckIsSafeToFold, /*InsnID*/1,
7152 GIM_CheckIsSafeToFold, /*InsnID*/2,
7153 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
7154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7158 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7159 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7160 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7161 GIR_EraseFromParent, /*InsnID*/0,
7162 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7163 // GIR_Coverage, 2188,
7164 GIR_Done,
7165 // Label 375: @16854
7166 GIM_Try, /*On fail goto*//*Label 376*/ 16942, // Rule ID 5529 //
7167 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7169 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7170 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7171 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7172 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7173 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7174 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7175 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7176 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7177 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7178 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7179 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7180 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7181 GIM_CheckIsSafeToFold, /*InsnID*/1,
7182 GIM_CheckIsSafeToFold, /*InsnID*/2,
7183 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
7184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
7187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7188 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7189 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7190 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7191 GIR_EraseFromParent, /*InsnID*/0,
7192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7193 // GIR_Coverage, 5529,
7194 GIR_Done,
7195 // Label 376: @16942
7196 GIM_Try, /*On fail goto*//*Label 377*/ 17030, // Rule ID 5571 //
7197 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7199 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7200 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7201 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7202 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7203 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7204 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7205 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7206 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
7207 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7208 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7209 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7210 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
7211 GIM_CheckIsSafeToFold, /*InsnID*/1,
7212 GIM_CheckIsSafeToFold, /*InsnID*/2,
7213 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
7214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
7217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7218 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7219 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7220 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7221 GIR_EraseFromParent, /*InsnID*/0,
7222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7223 // GIR_Coverage, 5571,
7224 GIR_Done,
7225 // Label 377: @17030
7226 GIM_Try, /*On fail goto*//*Label 378*/ 17126, // Rule ID 1931 //
7227 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7230 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7231 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7232 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7233 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7234 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7235 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7236 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
7237 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7238 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7239 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7240 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7241 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7242 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7243 // MIs[3] Operand 1
7244 // No operand predicates
7245 GIM_CheckIsSafeToFold, /*InsnID*/1,
7246 GIM_CheckIsSafeToFold, /*InsnID*/2,
7247 GIM_CheckIsSafeToFold, /*InsnID*/3,
7248 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7253 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7254 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7255 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7256 GIR_EraseFromParent, /*InsnID*/0,
7257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7258 // GIR_Coverage, 1931,
7259 GIR_Done,
7260 // Label 378: @17126
7261 GIM_Try, /*On fail goto*//*Label 379*/ 17222, // Rule ID 2191 //
7262 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7264 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7265 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7266 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7267 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7268 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7269 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7270 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7271 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
7272 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7273 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7274 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7275 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7276 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7277 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7278 // MIs[3] Operand 1
7279 // No operand predicates
7280 GIM_CheckIsSafeToFold, /*InsnID*/1,
7281 GIM_CheckIsSafeToFold, /*InsnID*/2,
7282 GIM_CheckIsSafeToFold, /*InsnID*/3,
7283 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7288 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7289 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7290 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7291 GIR_EraseFromParent, /*InsnID*/0,
7292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7293 // GIR_Coverage, 2191,
7294 GIR_Done,
7295 // Label 379: @17222
7296 GIM_Try, /*On fail goto*//*Label 380*/ 17318, // Rule ID 1930 //
7297 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7300 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7301 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7302 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7303 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7304 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7305 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7306 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
7307 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7308 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7309 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7310 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7311 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7312 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
7313 // MIs[3] Operand 1
7314 // No operand predicates
7315 GIM_CheckIsSafeToFold, /*InsnID*/1,
7316 GIM_CheckIsSafeToFold, /*InsnID*/2,
7317 GIM_CheckIsSafeToFold, /*InsnID*/3,
7318 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7323 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7324 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7325 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7326 GIR_EraseFromParent, /*InsnID*/0,
7327 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7328 // GIR_Coverage, 1930,
7329 GIR_Done,
7330 // Label 380: @17318
7331 GIM_Try, /*On fail goto*//*Label 381*/ 17414, // Rule ID 2190 //
7332 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7334 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7335 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7336 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7337 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7338 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7339 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
7340 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7341 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
7342 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7343 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7344 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7345 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7346 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7347 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
7348 // MIs[3] Operand 1
7349 // No operand predicates
7350 GIM_CheckIsSafeToFold, /*InsnID*/1,
7351 GIM_CheckIsSafeToFold, /*InsnID*/2,
7352 GIM_CheckIsSafeToFold, /*InsnID*/3,
7353 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7358 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7359 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7360 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7361 GIR_EraseFromParent, /*InsnID*/0,
7362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7363 // GIR_Coverage, 2190,
7364 GIR_Done,
7365 // Label 381: @17414
7366 GIM_Try, /*On fail goto*//*Label 382*/ 17510, // Rule ID 1929 //
7367 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7370 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7371 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7372 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7373 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7374 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7375 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7376 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
7377 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7378 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7379 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7380 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7381 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7382 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7383 // MIs[3] Operand 1
7384 // No operand predicates
7385 GIM_CheckIsSafeToFold, /*InsnID*/1,
7386 GIM_CheckIsSafeToFold, /*InsnID*/2,
7387 GIM_CheckIsSafeToFold, /*InsnID*/3,
7388 // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7393 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7394 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7395 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7396 GIR_EraseFromParent, /*InsnID*/0,
7397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7398 // GIR_Coverage, 1929,
7399 GIR_Done,
7400 // Label 382: @17510
7401 GIM_Try, /*On fail goto*//*Label 383*/ 17606, // Rule ID 2189 //
7402 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7404 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7405 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
7406 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7407 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7408 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7409 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
7410 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7411 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
7412 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7413 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7414 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7415 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7416 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
7417 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7418 // MIs[3] Operand 1
7419 // No operand predicates
7420 GIM_CheckIsSafeToFold, /*InsnID*/1,
7421 GIM_CheckIsSafeToFold, /*InsnID*/2,
7422 GIM_CheckIsSafeToFold, /*InsnID*/3,
7423 // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7428 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7429 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7430 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7431 GIR_EraseFromParent, /*InsnID*/0,
7432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7433 // GIR_Coverage, 2189,
7434 GIR_Done,
7435 // Label 383: @17606
7436 GIM_Try, /*On fail goto*//*Label 384*/ 17702, // Rule ID 5532 //
7437 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7439 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7440 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
7441 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7442 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7443 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7444 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7445 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7446 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7447 // MIs[2] Operand 1
7448 // No operand predicates
7449 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7450 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7451 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7452 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7453 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7454 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7455 GIM_CheckIsSafeToFold, /*InsnID*/1,
7456 GIM_CheckIsSafeToFold, /*InsnID*/2,
7457 GIM_CheckIsSafeToFold, /*InsnID*/3,
7458 // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7463 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7464 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7465 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7466 GIR_EraseFromParent, /*InsnID*/0,
7467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7468 // GIR_Coverage, 5532,
7469 GIR_Done,
7470 // Label 384: @17702
7471 GIM_Try, /*On fail goto*//*Label 385*/ 17798, // Rule ID 5574 //
7472 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7474 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7475 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
7476 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7477 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7478 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7479 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7480 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7481 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7482 // MIs[2] Operand 1
7483 // No operand predicates
7484 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7485 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7486 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7487 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7488 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7489 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7490 GIM_CheckIsSafeToFold, /*InsnID*/1,
7491 GIM_CheckIsSafeToFold, /*InsnID*/2,
7492 GIM_CheckIsSafeToFold, /*InsnID*/3,
7493 // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7498 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7499 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7500 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7501 GIR_EraseFromParent, /*InsnID*/0,
7502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7503 // GIR_Coverage, 5574,
7504 GIR_Done,
7505 // Label 385: @17798
7506 GIM_Try, /*On fail goto*//*Label 386*/ 17894, // Rule ID 5531 //
7507 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7509 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7510 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
7511 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7512 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7513 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7514 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7515 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7516 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
7517 // MIs[2] Operand 1
7518 // No operand predicates
7519 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7520 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7521 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7522 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7523 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7524 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7525 GIM_CheckIsSafeToFold, /*InsnID*/1,
7526 GIM_CheckIsSafeToFold, /*InsnID*/2,
7527 GIM_CheckIsSafeToFold, /*InsnID*/3,
7528 // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
7530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7533 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7534 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7535 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7536 GIR_EraseFromParent, /*InsnID*/0,
7537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7538 // GIR_Coverage, 5531,
7539 GIR_Done,
7540 // Label 386: @17894
7541 GIM_Try, /*On fail goto*//*Label 387*/ 17990, // Rule ID 5573 //
7542 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7544 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7545 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
7546 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7547 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7548 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7549 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7550 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7551 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
7552 // MIs[2] Operand 1
7553 // No operand predicates
7554 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7555 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7556 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7557 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7558 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7559 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
7560 GIM_CheckIsSafeToFold, /*InsnID*/1,
7561 GIM_CheckIsSafeToFold, /*InsnID*/2,
7562 GIM_CheckIsSafeToFold, /*InsnID*/3,
7563 // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
7564 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
7565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7568 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7569 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7570 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7571 GIR_EraseFromParent, /*InsnID*/0,
7572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7573 // GIR_Coverage, 5573,
7574 GIR_Done,
7575 // Label 387: @17990
7576 GIM_Try, /*On fail goto*//*Label 388*/ 18086, // Rule ID 5530 //
7577 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
7578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7579 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7580 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
7581 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7582 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7583 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7584 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7585 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7586 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7587 // MIs[2] Operand 1
7588 // No operand predicates
7589 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7590 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7591 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7592 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7593 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7594 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
7595 GIM_CheckIsSafeToFold, /*InsnID*/1,
7596 GIM_CheckIsSafeToFold, /*InsnID*/2,
7597 GIM_CheckIsSafeToFold, /*InsnID*/3,
7598 // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
7600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
7602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7603 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7604 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7605 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7606 GIR_EraseFromParent, /*InsnID*/0,
7607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7608 // GIR_Coverage, 5530,
7609 GIR_Done,
7610 // Label 388: @18086
7611 GIM_Try, /*On fail goto*//*Label 389*/ 18182, // Rule ID 5572 //
7612 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
7613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7615 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
7616 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7617 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7618 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7619 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7620 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7621 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
7622 // MIs[2] Operand 1
7623 // No operand predicates
7624 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7625 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
7626 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7627 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7628 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7629 GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
7630 GIM_CheckIsSafeToFold, /*InsnID*/1,
7631 GIM_CheckIsSafeToFold, /*InsnID*/2,
7632 GIM_CheckIsSafeToFold, /*InsnID*/3,
7633 // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
7634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
7635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
7637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
7638 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
7639 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7640 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7641 GIR_EraseFromParent, /*InsnID*/0,
7642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7643 // GIR_Coverage, 5572,
7644 GIR_Done,
7645 // Label 389: @18182
7646 GIM_Try, /*On fail goto*//*Label 390*/ 18257, // Rule ID 5350 //
7647 GIM_CheckFeatures, GIFBS_IsThumb2,
7648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7649 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7650 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7651 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7652 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7653 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
7654 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7655 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7656 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7657 // MIs[2] Operand 1
7658 // No operand predicates
7659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7660 GIM_CheckIsSafeToFold, /*InsnID*/1,
7661 GIM_CheckIsSafeToFold, /*InsnID*/2,
7662 // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7666 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7667 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7668 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7669 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7670 GIR_EraseFromParent, /*InsnID*/0,
7671 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7672 // GIR_Coverage, 5350,
7673 GIR_Done,
7674 // Label 390: @18257
7675 GIM_Try, /*On fail goto*//*Label 391*/ 18332, // Rule ID 5349 //
7676 GIM_CheckFeatures, GIFBS_IsThumb2,
7677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7679 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7680 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7681 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7682 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7683 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7684 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7685 // MIs[2] Operand 1
7686 // No operand predicates
7687 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7689 GIM_CheckIsSafeToFold, /*InsnID*/1,
7690 GIM_CheckIsSafeToFold, /*InsnID*/2,
7691 // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7695 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7696 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7697 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7698 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7699 GIR_EraseFromParent, /*InsnID*/0,
7700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7701 // GIR_Coverage, 5349,
7702 GIR_Done,
7703 // Label 391: @18332
7704 GIM_Try, /*On fail goto*//*Label 392*/ 18407, // Rule ID 5348 //
7705 GIM_CheckFeatures, GIFBS_IsThumb2,
7706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7708 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7709 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7710 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7711 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7712 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
7713 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
7714 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7715 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7716 // MIs[2] Operand 1
7717 // No operand predicates
7718 GIM_CheckIsSafeToFold, /*InsnID*/1,
7719 GIM_CheckIsSafeToFold, /*InsnID*/2,
7720 // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7724 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7725 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7726 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7727 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7728 GIR_EraseFromParent, /*InsnID*/0,
7729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7730 // GIR_Coverage, 5348,
7731 GIR_Done,
7732 // Label 392: @18407
7733 GIM_Try, /*On fail goto*//*Label 393*/ 18482, // Rule ID 503 //
7734 GIM_CheckFeatures, GIFBS_IsThumb2,
7735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7737 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7738 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7739 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7740 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7741 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7742 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
7743 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7744 // MIs[2] Operand 1
7745 // No operand predicates
7746 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7747 GIM_CheckIsSafeToFold, /*InsnID*/1,
7748 GIM_CheckIsSafeToFold, /*InsnID*/2,
7749 // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
7751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7753 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7754 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7755 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7756 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7757 GIR_EraseFromParent, /*InsnID*/0,
7758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7759 // GIR_Coverage, 503,
7760 GIR_Done,
7761 // Label 393: @18482
7762 GIM_Try, /*On fail goto*//*Label 394*/ 18550, // Rule ID 5351 //
7763 GIM_CheckFeatures, GIFBS_IsThumb2,
7764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7765 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7766 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7767 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7768 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7769 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7770 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7772 GIM_CheckIsSafeToFold, /*InsnID*/1,
7773 // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
7777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7778 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7779 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7780 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7781 GIR_EraseFromParent, /*InsnID*/0,
7782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7783 // GIR_Coverage, 5351,
7784 GIR_Done,
7785 // Label 394: @18550
7786 GIM_Try, /*On fail goto*//*Label 395*/ 18618, // Rule ID 504 //
7787 GIM_CheckFeatures, GIFBS_IsThumb2,
7788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7790 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7791 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
7792 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7793 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7794 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7795 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
7796 GIM_CheckIsSafeToFold, /*InsnID*/1,
7797 // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
7799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7802 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7803 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7804 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7805 GIR_EraseFromParent, /*InsnID*/0,
7806 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7807 // GIR_Coverage, 504,
7808 GIR_Done,
7809 // Label 395: @18618
7810 GIM_Try, /*On fail goto*//*Label 396*/ 18660, // Rule ID 1862 //
7811 GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
7812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
7813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7814 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
7815 // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
7816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVTi16,
7817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7819 GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
7820 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7821 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7822 GIR_EraseFromParent, /*InsnID*/0,
7823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7824 // GIR_Coverage, 1862,
7825 GIR_Done,
7826 // Label 396: @18660
7827 GIM_Try, /*On fail goto*//*Label 397*/ 18702, // Rule ID 2087 //
7828 GIM_CheckFeatures, GIFBS_IsThumb2,
7829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7831 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
7832 // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
7833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVTi16,
7834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7836 GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
7837 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7838 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7839 GIR_EraseFromParent, /*InsnID*/0,
7840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7841 // GIR_Coverage, 2087,
7842 GIR_Done,
7843 // Label 397: @18702
7844 GIM_Try, /*On fail goto*//*Label 398*/ 18756, // Rule ID 151 //
7845 GIM_CheckFeatures, GIFBS_IsARM,
7846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7849 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7850 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
7851 // MIs[1] Operand 1
7852 // No operand predicates
7853 GIM_CheckIsSafeToFold, /*InsnID*/1,
7854 // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRri,
7856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7858 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7859 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7860 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7861 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7862 GIR_EraseFromParent, /*InsnID*/0,
7863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7864 // GIR_Coverage, 151,
7865 GIR_Done,
7866 // Label 398: @18756
7867 GIM_Try, /*On fail goto*//*Label 399*/ 18810, // Rule ID 491 //
7868 GIM_CheckFeatures, GIFBS_IsThumb2,
7869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7871 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7872 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
7873 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
7874 // MIs[1] Operand 1
7875 // No operand predicates
7876 GIM_CheckIsSafeToFold, /*InsnID*/1,
7877 // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRri,
7879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7881 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7882 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7883 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7884 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7885 GIR_EraseFromParent, /*InsnID*/0,
7886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7887 // GIR_Coverage, 491,
7888 GIR_Done,
7889 // Label 399: @18810
7890 GIM_Try, /*On fail goto*//*Label 400*/ 18857, // Rule ID 152 //
7891 GIM_CheckFeatures, GIFBS_IsARM,
7892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
7893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
7894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
7895 // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7896 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRrr,
7897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
7900 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7901 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7902 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7903 GIR_EraseFromParent, /*InsnID*/0,
7904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7905 // GIR_Coverage, 152,
7906 GIR_Done,
7907 // Label 400: @18857
7908 GIM_Try, /*On fail goto*//*Label 401*/ 18904, // Rule ID 492 //
7909 GIM_CheckFeatures, GIFBS_IsThumb2,
7910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
7911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
7912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
7913 // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr,
7915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
7916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
7917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
7918 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7919 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7920 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7921 GIR_EraseFromParent, /*InsnID*/0,
7922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7923 // GIR_Coverage, 492,
7924 GIR_Done,
7925 // Label 401: @18904
7926 GIM_Reject,
7927 // Label 357: @18905
7928 GIM_Reject,
7929 // Label 348: @18906
7930 GIM_Try, /*On fail goto*//*Label 402*/ 18957, // Rule ID 1151 //
7931 GIM_CheckFeatures, GIFBS_HasNEON,
7932 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7933 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
7934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
7937 // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
7939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
7941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
7942 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7943 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7944 GIR_EraseFromParent, /*InsnID*/0,
7945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7946 // GIR_Coverage, 1151,
7947 GIR_Done,
7948 // Label 402: @18957
7949 GIM_Reject,
7950 // Label 349: @18958
7951 GIM_Try, /*On fail goto*//*Label 403*/ 19023, // Rule ID 3378 //
7952 GIM_CheckFeatures, GIFBS_HasMVEInt,
7953 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7954 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
7955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
7956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
7957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
7958 // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7959 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7960 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
7961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
7962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
7963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
7964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
7965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
7966 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
7967 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
7968 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
7969 GIR_EraseFromParent, /*InsnID*/0,
7970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7971 // GIR_Coverage, 3378,
7972 GIR_Done,
7973 // Label 403: @19023
7974 GIM_Reject,
7975 // Label 350: @19024
7976 GIM_Try, /*On fail goto*//*Label 404*/ 19129, // Rule ID 1850 //
7977 GIM_CheckFeatures, GIFBS_HasMVEInt,
7978 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
7979 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
7980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
7981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
7982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
7983 // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7984 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7985 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7986 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7987 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7988 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
7989 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7990 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
7991 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7992 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
7993 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7994 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
7995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
7996 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
7997 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
7998 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
7999 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8000 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8001 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8002 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8005 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8006 GIR_EraseFromParent, /*InsnID*/0,
8007 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8008 // GIR_Coverage, 1850,
8009 GIR_Done,
8010 // Label 404: @19129
8011 GIM_Reject,
8012 // Label 351: @19130
8013 GIM_Try, /*On fail goto*//*Label 405*/ 19241,
8014 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8015 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8016 GIM_Try, /*On fail goto*//*Label 406*/ 19183, // Rule ID 1152 //
8017 GIM_CheckFeatures, GIFBS_HasNEON,
8018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8021 // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
8022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
8023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8026 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8027 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8028 GIR_EraseFromParent, /*InsnID*/0,
8029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8030 // GIR_Coverage, 1152,
8031 GIR_Done,
8032 // Label 406: @19183
8033 GIM_Try, /*On fail goto*//*Label 407*/ 19240, // Rule ID 3374 //
8034 GIM_CheckFeatures, GIFBS_HasMVEInt,
8035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8038 // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
8039 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8040 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8041 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8046 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8047 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8048 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8049 GIR_EraseFromParent, /*InsnID*/0,
8050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8051 // GIR_Coverage, 3374,
8052 GIR_Done,
8053 // Label 407: @19240
8054 GIM_Reject,
8055 // Label 405: @19241
8056 GIM_Reject,
8057 // Label 352: @19242
8058 GIM_Try, /*On fail goto*//*Label 408*/ 19347, // Rule ID 1851 //
8059 GIM_CheckFeatures, GIFBS_HasMVEInt,
8060 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
8061 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
8062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8065 // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8066 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8067 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8068 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8069 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8070 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8071 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8072 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8073 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8074 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8075 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8076 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8077 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
8078 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8079 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8080 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8081 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8082 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8083 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8084 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8087 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8088 GIR_EraseFromParent, /*InsnID*/0,
8089 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8090 // GIR_Coverage, 1851,
8091 GIR_Done,
8092 // Label 408: @19347
8093 GIM_Reject,
8094 // Label 353: @19348
8095 GIM_Try, /*On fail goto*//*Label 409*/ 19413, // Rule ID 3370 //
8096 GIM_CheckFeatures, GIFBS_HasMVEInt,
8097 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8102 // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
8103 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8104 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8105 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8106 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8110 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8111 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8112 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8113 GIR_EraseFromParent, /*InsnID*/0,
8114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8115 // GIR_Coverage, 3370,
8116 GIR_Done,
8117 // Label 409: @19413
8118 GIM_Reject,
8119 // Label 354: @19414
8120 GIM_Try, /*On fail goto*//*Label 410*/ 19519, // Rule ID 1849 //
8121 GIM_CheckFeatures, GIFBS_HasMVEInt,
8122 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
8123 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
8124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8127 // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8128 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8129 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8130 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8131 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8132 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8133 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8134 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8135 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8136 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8137 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8138 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8139 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2ORRrr,
8140 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8141 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8142 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8143 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8144 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8145 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8146 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8149 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8150 GIR_EraseFromParent, /*InsnID*/0,
8151 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8152 // GIR_Coverage, 1849,
8153 GIR_Done,
8154 // Label 410: @19519
8155 GIM_Reject,
8156 // Label 355: @19520
8157 GIM_Try, /*On fail goto*//*Label 411*/ 19585, // Rule ID 3366 //
8158 GIM_CheckFeatures, GIFBS_HasMVEInt,
8159 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8160 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8164 // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
8165 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8166 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8167 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VORR,
8169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8172 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8173 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8174 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8175 GIR_EraseFromParent, /*InsnID*/0,
8176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8177 // GIR_Coverage, 3366,
8178 GIR_Done,
8179 // Label 411: @19585
8180 GIM_Reject,
8181 // Label 356: @19586
8182 GIM_Reject,
8183 // Label 7: @19587
8184 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 421*/ 20687,
8185 /*GILLT_s32*//*Label 412*/ 19607, 0,
8186 /*GILLT_v2s32*//*Label 413*/ 20007,
8187 /*GILLT_v2s64*//*Label 414*/ 20059,
8188 /*GILLT_v4s1*//*Label 415*/ 20125, 0,
8189 /*GILLT_v4s32*//*Label 416*/ 20231, 0,
8190 /*GILLT_v8s1*//*Label 417*/ 20343, 0,
8191 /*GILLT_v8s16*//*Label 418*/ 20449, 0,
8192 /*GILLT_v16s1*//*Label 419*/ 20515,
8193 /*GILLT_v16s8*//*Label 420*/ 20621,
8194 // Label 412: @19607
8195 GIM_Try, /*On fail goto*//*Label 422*/ 20006,
8196 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
8197 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8198 GIM_Try, /*On fail goto*//*Label 423*/ 19667, // Rule ID 5353 //
8199 GIM_CheckFeatures, GIFBS_IsThumb2,
8200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8201 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, -1,
8202 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8203 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8204 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8205 // MIs[1] Operand 1
8206 // No operand predicates
8207 GIM_CheckIsSafeToFold, /*InsnID*/1,
8208 // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
8209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
8210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8211 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8212 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8213 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8214 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8215 GIR_EraseFromParent, /*InsnID*/0,
8216 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8217 // GIR_Coverage, 5353,
8218 GIR_Done,
8219 // Label 423: @19667
8220 GIM_Try, /*On fail goto*//*Label 424*/ 19717, // Rule ID 506 //
8221 GIM_CheckFeatures, GIFBS_IsThumb2,
8222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8223 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8224 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8225 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8226 // MIs[1] Operand 1
8227 // No operand predicates
8228 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
8229 GIM_CheckIsSafeToFold, /*InsnID*/1,
8230 // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
8231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
8232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8233 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8234 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8235 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8236 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8237 GIR_EraseFromParent, /*InsnID*/0,
8238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8239 // GIR_Coverage, 506,
8240 GIR_Done,
8241 // Label 424: @19717
8242 GIM_Try, /*On fail goto*//*Label 425*/ 19760, // Rule ID 507 //
8243 GIM_CheckFeatures, GIFBS_IsThumb2,
8244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8246 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
8247 // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
8248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNr,
8249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
8251 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8252 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8253 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8254 GIR_EraseFromParent, /*InsnID*/0,
8255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8256 // GIR_Coverage, 507,
8257 GIR_Done,
8258 // Label 425: @19760
8259 GIM_Try, /*On fail goto*//*Label 426*/ 19803, // Rule ID 165 //
8260 GIM_CheckFeatures, GIFBS_IsARM,
8261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8263 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
8264 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
8265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVNr,
8266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
8268 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8269 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8270 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8271 GIR_EraseFromParent, /*InsnID*/0,
8272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8273 // GIR_Coverage, 165,
8274 GIR_Done,
8275 // Label 426: @19803
8276 GIM_Try, /*On fail goto*//*Label 427*/ 19857, // Rule ID 155 //
8277 GIM_CheckFeatures, GIFBS_IsARM,
8278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8281 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8282 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
8283 // MIs[1] Operand 1
8284 // No operand predicates
8285 GIM_CheckIsSafeToFold, /*InsnID*/1,
8286 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORri,
8288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8290 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8291 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8292 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8293 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8294 GIR_EraseFromParent, /*InsnID*/0,
8295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8296 // GIR_Coverage, 155,
8297 GIR_Done,
8298 // Label 427: @19857
8299 GIM_Try, /*On fail goto*//*Label 428*/ 19911, // Rule ID 494 //
8300 GIM_CheckFeatures, GIFBS_IsThumb2,
8301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8303 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8304 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
8305 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
8306 // MIs[1] Operand 1
8307 // No operand predicates
8308 GIM_CheckIsSafeToFold, /*InsnID*/1,
8309 // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8310 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORri,
8311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8313 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8314 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8315 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8316 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8317 GIR_EraseFromParent, /*InsnID*/0,
8318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8319 // GIR_Coverage, 494,
8320 GIR_Done,
8321 // Label 428: @19911
8322 GIM_Try, /*On fail goto*//*Label 429*/ 19958, // Rule ID 156 //
8323 GIM_CheckFeatures, GIFBS_IsARM,
8324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
8327 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORrr,
8329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8332 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8333 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8334 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8335 GIR_EraseFromParent, /*InsnID*/0,
8336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8337 // GIR_Coverage, 156,
8338 GIR_Done,
8339 // Label 429: @19958
8340 GIM_Try, /*On fail goto*//*Label 430*/ 20005, // Rule ID 495 //
8341 GIM_CheckFeatures, GIFBS_IsThumb2,
8342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
8344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
8345 // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORrr,
8347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
8349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8350 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8351 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8352 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8353 GIR_EraseFromParent, /*InsnID*/0,
8354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8355 // GIR_Coverage, 495,
8356 GIR_Done,
8357 // Label 430: @20005
8358 GIM_Reject,
8359 // Label 422: @20006
8360 GIM_Reject,
8361 // Label 413: @20007
8362 GIM_Try, /*On fail goto*//*Label 431*/ 20058, // Rule ID 1149 //
8363 GIM_CheckFeatures, GIFBS_HasNEON,
8364 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8369 // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
8370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
8371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8374 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8375 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8376 GIR_EraseFromParent, /*InsnID*/0,
8377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8378 // GIR_Coverage, 1149,
8379 GIR_Done,
8380 // Label 431: @20058
8381 GIM_Reject,
8382 // Label 414: @20059
8383 GIM_Try, /*On fail goto*//*Label 432*/ 20124, // Rule ID 3392 //
8384 GIM_CheckFeatures, GIFBS_HasMVEInt,
8385 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
8387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8390 // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
8391 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8392 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8393 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
8395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8398 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8399 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8400 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8401 GIR_EraseFromParent, /*InsnID*/0,
8402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8403 // GIR_Coverage, 3392,
8404 GIR_Done,
8405 // Label 432: @20124
8406 GIM_Reject,
8407 // Label 415: @20125
8408 GIM_Try, /*On fail goto*//*Label 433*/ 20230, // Rule ID 1847 //
8409 GIM_CheckFeatures, GIFBS_HasMVEInt,
8410 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1,
8411 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1,
8412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8415 // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8416 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8417 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8418 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8419 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8420 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8421 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8422 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8423 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8424 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8425 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8426 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8427 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
8428 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8429 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8430 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8431 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8432 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8433 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8434 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8437 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8438 GIR_EraseFromParent, /*InsnID*/0,
8439 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8440 // GIR_Coverage, 1847,
8441 GIR_Done,
8442 // Label 433: @20230
8443 GIM_Reject,
8444 // Label 416: @20231
8445 GIM_Try, /*On fail goto*//*Label 434*/ 20342,
8446 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8447 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8448 GIM_Try, /*On fail goto*//*Label 435*/ 20284, // Rule ID 1150 //
8449 GIM_CheckFeatures, GIFBS_HasNEON,
8450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8453 // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
8454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
8455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
8457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8458 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8459 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8460 GIR_EraseFromParent, /*InsnID*/0,
8461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8462 // GIR_Coverage, 1150,
8463 GIR_Done,
8464 // Label 435: @20284
8465 GIM_Try, /*On fail goto*//*Label 436*/ 20341, // Rule ID 3388 //
8466 GIM_CheckFeatures, GIFBS_HasMVEInt,
8467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8470 // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
8471 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8472 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8473 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
8475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8478 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8479 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8480 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8481 GIR_EraseFromParent, /*InsnID*/0,
8482 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8483 // GIR_Coverage, 3388,
8484 GIR_Done,
8485 // Label 436: @20341
8486 GIM_Reject,
8487 // Label 434: @20342
8488 GIM_Reject,
8489 // Label 417: @20343
8490 GIM_Try, /*On fail goto*//*Label 437*/ 20448, // Rule ID 1848 //
8491 GIM_CheckFeatures, GIFBS_HasMVEInt,
8492 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1,
8493 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1,
8494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8497 // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8498 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8499 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8500 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8501 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8502 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8503 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8504 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8505 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8506 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8507 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8508 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8509 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
8510 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8511 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8512 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8513 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8514 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8515 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8516 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8519 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8520 GIR_EraseFromParent, /*InsnID*/0,
8521 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8522 // GIR_Coverage, 1848,
8523 GIR_Done,
8524 // Label 437: @20448
8525 GIM_Reject,
8526 // Label 418: @20449
8527 GIM_Try, /*On fail goto*//*Label 438*/ 20514, // Rule ID 3384 //
8528 GIM_CheckFeatures, GIFBS_HasMVEInt,
8529 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8530 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8534 // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
8535 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8536 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8537 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
8539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8542 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8543 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8544 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8545 GIR_EraseFromParent, /*InsnID*/0,
8546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8547 // GIR_Coverage, 3384,
8548 GIR_Done,
8549 // Label 438: @20514
8550 GIM_Reject,
8551 // Label 419: @20515
8552 GIM_Try, /*On fail goto*//*Label 439*/ 20620, // Rule ID 1846 //
8553 GIM_CheckFeatures, GIFBS_HasMVEInt,
8554 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1,
8555 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1,
8556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
8557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::VCCRRegClassID,
8558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::VCCRRegClassID,
8559 // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8560 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8561 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8562 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8563 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
8564 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
8565 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8566 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
8567 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
8568 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
8569 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8570 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
8571 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2EORrr,
8572 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8573 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
8574 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
8575 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8576 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8577 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8578 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8579 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8581 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8582 GIR_EraseFromParent, /*InsnID*/0,
8583 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::VCCRRegClassID,
8584 // GIR_Coverage, 1846,
8585 GIR_Done,
8586 // Label 439: @20620
8587 GIM_Reject,
8588 // Label 420: @20621
8589 GIM_Try, /*On fail goto*//*Label 440*/ 20686, // Rule ID 3380 //
8590 GIM_CheckFeatures, GIFBS_HasMVEInt,
8591 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8592 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
8594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
8595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
8596 // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
8597 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
8598 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
8599 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
8600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VEOR,
8601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
8602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
8603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
8604 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8605 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8606 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
8607 GIR_EraseFromParent, /*InsnID*/0,
8608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8609 // GIR_Coverage, 3380,
8610 GIR_Done,
8611 // Label 440: @20686
8612 GIM_Reject,
8613 // Label 421: @20687
8614 GIM_Reject,
8615 // Label 8: @20688
8616 GIM_Try, /*On fail goto*//*Label 441*/ 21081,
8617 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
8618 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 15, /*)*//*default:*//*Label 446*/ 21080,
8619 /*GILLT_v2s64*//*Label 442*/ 20710, 0, 0,
8620 /*GILLT_v4s32*//*Label 443*/ 20771, 0, 0, 0,
8621 /*GILLT_v8s16*//*Label 444*/ 20875, 0, 0,
8622 /*GILLT_v16s8*//*Label 445*/ 21019,
8623 // Label 442: @20710
8624 GIM_Try, /*On fail goto*//*Label 447*/ 20770, // Rule ID 3013 //
8625 GIM_CheckFeatures, GIFBS_HasNEON,
8626 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8627 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8631 // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
8632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8635 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8637 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8638 GIR_EraseFromParent, /*InsnID*/0,
8639 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8640 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8641 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8642 // GIR_Coverage, 3013,
8643 GIR_Done,
8644 // Label 447: @20770
8645 GIM_Reject,
8646 // Label 443: @20771
8647 GIM_Try, /*On fail goto*//*Label 448*/ 20874,
8648 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8649 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8653 GIM_Try, /*On fail goto*//*Label 449*/ 20833, // Rule ID 3014 //
8654 GIM_CheckFeatures, GIFBS_HasNEON,
8655 // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
8656 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8659 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8661 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8662 GIR_EraseFromParent, /*InsnID*/0,
8663 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8664 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8665 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8666 // GIR_Coverage, 3014,
8667 GIR_Done,
8668 // Label 449: @20833
8669 GIM_Try, /*On fail goto*//*Label 450*/ 20873, // Rule ID 3017 //
8670 GIM_CheckFeatures, GIFBS_HasNEON,
8671 // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
8672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8675 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8677 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8678 GIR_EraseFromParent, /*InsnID*/0,
8679 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8680 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8681 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8682 // GIR_Coverage, 3017,
8683 GIR_Done,
8684 // Label 450: @20873
8685 GIM_Reject,
8686 // Label 448: @20874
8687 GIM_Reject,
8688 // Label 444: @20875
8689 GIM_Try, /*On fail goto*//*Label 451*/ 21018,
8690 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8691 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8695 GIM_Try, /*On fail goto*//*Label 452*/ 20937, // Rule ID 3015 //
8696 GIM_CheckFeatures, GIFBS_HasNEON,
8697 // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
8698 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8701 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8703 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8704 GIR_EraseFromParent, /*InsnID*/0,
8705 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8706 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8707 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8708 // GIR_Coverage, 3015,
8709 GIR_Done,
8710 // Label 452: @20937
8711 GIM_Try, /*On fail goto*//*Label 453*/ 20977, // Rule ID 3018 //
8712 GIM_CheckFeatures, GIFBS_HasNEON,
8713 // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
8714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8717 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8719 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8720 GIR_EraseFromParent, /*InsnID*/0,
8721 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8722 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8723 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8724 // GIR_Coverage, 3018,
8725 GIR_Done,
8726 // Label 453: @20977
8727 GIM_Try, /*On fail goto*//*Label 454*/ 21017, // Rule ID 3019 //
8728 GIM_CheckFeatures, GIFBS_HasNEON,
8729 // (concat_vectors:{ *:[v8bf16] } DPR:{ *:[v4bf16] }:$Dn, DPR:{ *:[v4bf16] }:$Dm) => (REG_SEQUENCE:{ *:[v8bf16] } QPR:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4bf16] }:$Dm, dsub_1:{ *:[i32] })
8730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8733 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8735 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8736 GIR_EraseFromParent, /*InsnID*/0,
8737 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8738 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8739 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8740 // GIR_Coverage, 3019,
8741 GIR_Done,
8742 // Label 454: @21017
8743 GIM_Reject,
8744 // Label 451: @21018
8745 GIM_Reject,
8746 // Label 445: @21019
8747 GIM_Try, /*On fail goto*//*Label 455*/ 21079, // Rule ID 3016 //
8748 GIM_CheckFeatures, GIFBS_HasNEON,
8749 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8750 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8754 // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
8755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE,
8756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
8758 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
8759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8760 GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
8761 GIR_EraseFromParent, /*InsnID*/0,
8762 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
8763 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPRRegClassID,
8764 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, ARM::DPRRegClassID,
8765 // GIR_Coverage, 3016,
8766 GIR_Done,
8767 // Label 455: @21079
8768 GIM_Reject,
8769 // Label 446: @21080
8770 GIM_Reject,
8771 // Label 441: @21081
8772 GIM_Reject,
8773 // Label 9: @21082
8774 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 465*/ 31846,
8775 /*GILLT_s32*//*Label 456*/ 21102,
8776 /*GILLT_s64*//*Label 457*/ 21242,
8777 /*GILLT_v2s32*//*Label 458*/ 22187,
8778 /*GILLT_v2s64*//*Label 459*/ 23132, 0,
8779 /*GILLT_v4s16*//*Label 460*/ 25015,
8780 /*GILLT_v4s32*//*Label 461*/ 26247, 0, 0,
8781 /*GILLT_v8s8*//*Label 462*/ 28130,
8782 /*GILLT_v8s16*//*Label 463*/ 28642, 0, 0,
8783 /*GILLT_v16s8*//*Label 464*/ 30812,
8784 // Label 456: @21102
8785 GIM_Try, /*On fail goto*//*Label 466*/ 21241,
8786 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
8787 GIM_Try, /*On fail goto*//*Label 467*/ 21143, // Rule ID 703 //
8788 GIM_CheckFeatures, GIFBS_HasFPRegs,
8789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
8790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
8791 // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
8792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVRS,
8793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
8794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
8795 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8796 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8797 GIR_EraseFromParent, /*InsnID*/0,
8798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8799 // GIR_Coverage, 703,
8800 GIR_Done,
8801 // Label 467: @21143
8802 GIM_Try, /*On fail goto*//*Label 468*/ 21178, // Rule ID 704 //
8803 GIM_CheckFeatures, GIFBS_HasFPRegs_UseVMOVSR,
8804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8806 // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
8807 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVSR,
8808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sn
8809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
8810 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8811 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8812 GIR_EraseFromParent, /*InsnID*/0,
8813 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8814 // GIR_Coverage, 704,
8815 GIR_Done,
8816 // Label 468: @21178
8817 GIM_Try, /*On fail goto*//*Label 469*/ 21240, // Rule ID 2633 //
8818 GIM_CheckFeatures, GIFBS_DontUseVMOVSR_HasNEON,
8819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
8821 // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
8822 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
8823 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VMOVDRR,
8824 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
8825 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
8826 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
8827 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
8828 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
8829 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8832 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
8833 GIR_EraseFromParent, /*InsnID*/0,
8834 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
8835 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
8836 // GIR_Coverage, 2633,
8837 GIR_Done,
8838 // Label 469: @21240
8839 GIM_Reject,
8840 // Label 466: @21241
8841 GIM_Reject,
8842 // Label 457: @21242
8843 GIM_Try, /*On fail goto*//*Label 470*/ 21276, // Rule ID 2635 //
8844 GIM_CheckFeatures, GIFBS_HasNEON,
8845 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8848 // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src
8849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8852 GIR_EraseFromParent, /*InsnID*/0,
8853 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8854 // GIR_Coverage, 2635,
8855 GIR_Done,
8856 // Label 470: @21276
8857 GIM_Try, /*On fail goto*//*Label 471*/ 21310, // Rule ID 2636 //
8858 GIM_CheckFeatures, GIFBS_HasNEON,
8859 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8862 // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src
8863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8866 GIR_EraseFromParent, /*InsnID*/0,
8867 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8868 // GIR_Coverage, 2636,
8869 GIR_Done,
8870 // Label 471: @21310
8871 GIM_Try, /*On fail goto*//*Label 472*/ 21344, // Rule ID 2651 //
8872 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8873 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8876 // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src
8877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8880 GIR_EraseFromParent, /*InsnID*/0,
8881 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8882 // GIR_Coverage, 2651,
8883 GIR_Done,
8884 // Label 472: @21344
8885 GIM_Try, /*On fail goto*//*Label 473*/ 21378, // Rule ID 2652 //
8886 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8887 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8890 // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src
8891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8894 GIR_EraseFromParent, /*InsnID*/0,
8895 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8896 // GIR_Coverage, 2652,
8897 GIR_Done,
8898 // Label 473: @21378
8899 GIM_Try, /*On fail goto*//*Label 474*/ 21412, // Rule ID 2653 //
8900 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8901 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8904 // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src
8905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8908 GIR_EraseFromParent, /*InsnID*/0,
8909 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8910 // GIR_Coverage, 2653,
8911 GIR_Done,
8912 // Label 474: @21412
8913 GIM_Try, /*On fail goto*//*Label 475*/ 21446, // Rule ID 2654 //
8914 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8915 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8918 // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[f64] }:$src
8919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8922 GIR_EraseFromParent, /*InsnID*/0,
8923 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8924 // GIR_Coverage, 2654,
8925 GIR_Done,
8926 // Label 475: @21446
8927 GIM_Try, /*On fail goto*//*Label 476*/ 21480, // Rule ID 2655 //
8928 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8929 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8932 // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src
8933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8936 GIR_EraseFromParent, /*InsnID*/0,
8937 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8938 // GIR_Coverage, 2655,
8939 GIR_Done,
8940 // Label 476: @21480
8941 GIM_Try, /*On fail goto*//*Label 477*/ 21514, // Rule ID 2656 //
8942 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8943 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
8944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8946 // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src
8947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8950 GIR_EraseFromParent, /*InsnID*/0,
8951 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8952 // GIR_Coverage, 2656,
8953 GIR_Done,
8954 // Label 477: @21514
8955 GIM_Try, /*On fail goto*//*Label 478*/ 21548, // Rule ID 2657 //
8956 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8957 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8960 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src
8961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8964 GIR_EraseFromParent, /*InsnID*/0,
8965 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8966 // GIR_Coverage, 2657,
8967 GIR_Done,
8968 // Label 478: @21548
8969 GIM_Try, /*On fail goto*//*Label 479*/ 21582, // Rule ID 2658 //
8970 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8971 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8974 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src
8975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8978 GIR_EraseFromParent, /*InsnID*/0,
8979 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8980 // GIR_Coverage, 2658,
8981 GIR_Done,
8982 // Label 479: @21582
8983 GIM_Try, /*On fail goto*//*Label 480*/ 21616, // Rule ID 2659 //
8984 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8985 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8988 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src
8989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8992 GIR_EraseFromParent, /*InsnID*/0,
8993 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
8994 // GIR_Coverage, 2659,
8995 GIR_Done,
8996 // Label 480: @21616
8997 GIM_Try, /*On fail goto*//*Label 481*/ 21650, // Rule ID 2660 //
8998 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
8999 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9002 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v1i64] }:$src
9003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9006 GIR_EraseFromParent, /*InsnID*/0,
9007 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9008 // GIR_Coverage, 2660,
9009 GIR_Done,
9010 // Label 481: @21650
9011 GIM_Try, /*On fail goto*//*Label 482*/ 21684, // Rule ID 2661 //
9012 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9013 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9016 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src
9017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9020 GIR_EraseFromParent, /*InsnID*/0,
9021 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9022 // GIR_Coverage, 2661,
9023 GIR_Done,
9024 // Label 482: @21684
9025 GIM_Try, /*On fail goto*//*Label 483*/ 21718, // Rule ID 2662 //
9026 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9027 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9030 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src
9031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9034 GIR_EraseFromParent, /*InsnID*/0,
9035 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9036 // GIR_Coverage, 2662,
9037 GIR_Done,
9038 // Label 483: @21718
9039 GIM_Try, /*On fail goto*//*Label 484*/ 21757, // Rule ID 2743 //
9040 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9041 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9044 // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
9045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9048 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9049 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9050 GIR_EraseFromParent, /*InsnID*/0,
9051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9052 // GIR_Coverage, 2743,
9053 GIR_Done,
9054 // Label 484: @21757
9055 GIM_Try, /*On fail goto*//*Label 485*/ 21796, // Rule ID 2744 //
9056 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9057 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9060 // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
9061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9064 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9065 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9066 GIR_EraseFromParent, /*InsnID*/0,
9067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9068 // GIR_Coverage, 2744,
9069 GIR_Done,
9070 // Label 485: @21796
9071 GIM_Try, /*On fail goto*//*Label 486*/ 21835, // Rule ID 2745 //
9072 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9073 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9076 // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
9077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9080 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9081 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9082 GIR_EraseFromParent, /*InsnID*/0,
9083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9084 // GIR_Coverage, 2745,
9085 GIR_Done,
9086 // Label 486: @21835
9087 GIM_Try, /*On fail goto*//*Label 487*/ 21874, // Rule ID 2746 //
9088 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9089 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9092 // (bitconvert:{ *:[f64] } DPR:{ *:[v4bf16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4bf16] }:$src)
9093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9096 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9097 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9098 GIR_EraseFromParent, /*InsnID*/0,
9099 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9100 // GIR_Coverage, 2746,
9101 GIR_Done,
9102 // Label 487: @21874
9103 GIM_Try, /*On fail goto*//*Label 488*/ 21913, // Rule ID 2747 //
9104 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9105 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9108 // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
9109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9112 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9113 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9114 GIR_EraseFromParent, /*InsnID*/0,
9115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9116 // GIR_Coverage, 2747,
9117 GIR_Done,
9118 // Label 488: @21913
9119 GIM_Try, /*On fail goto*//*Label 489*/ 21952, // Rule ID 2748 //
9120 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9121 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9124 // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
9125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
9126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9128 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9129 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9130 GIR_EraseFromParent, /*InsnID*/0,
9131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9132 // GIR_Coverage, 2748,
9133 GIR_Done,
9134 // Label 489: @21952
9135 GIM_Try, /*On fail goto*//*Label 490*/ 21991, // Rule ID 2749 //
9136 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9137 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9140 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
9141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9144 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9145 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9146 GIR_EraseFromParent, /*InsnID*/0,
9147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9148 // GIR_Coverage, 2749,
9149 GIR_Done,
9150 // Label 490: @21991
9151 GIM_Try, /*On fail goto*//*Label 491*/ 22030, // Rule ID 2750 //
9152 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9153 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9156 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
9157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9160 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9161 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9162 GIR_EraseFromParent, /*InsnID*/0,
9163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9164 // GIR_Coverage, 2750,
9165 GIR_Done,
9166 // Label 491: @22030
9167 GIM_Try, /*On fail goto*//*Label 492*/ 22069, // Rule ID 2751 //
9168 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9169 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9172 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
9173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9176 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9177 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9178 GIR_EraseFromParent, /*InsnID*/0,
9179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9180 // GIR_Coverage, 2751,
9181 GIR_Done,
9182 // Label 492: @22069
9183 GIM_Try, /*On fail goto*//*Label 493*/ 22108, // Rule ID 2752 //
9184 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9185 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9188 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4bf16] }:$src)
9189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9192 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9193 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9194 GIR_EraseFromParent, /*InsnID*/0,
9195 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9196 // GIR_Coverage, 2752,
9197 GIR_Done,
9198 // Label 493: @22108
9199 GIM_Try, /*On fail goto*//*Label 494*/ 22147, // Rule ID 2753 //
9200 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9201 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9204 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
9205 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9208 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9209 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9210 GIR_EraseFromParent, /*InsnID*/0,
9211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9212 // GIR_Coverage, 2753,
9213 GIR_Done,
9214 // Label 494: @22147
9215 GIM_Try, /*On fail goto*//*Label 495*/ 22186, // Rule ID 2754 //
9216 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9217 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9220 // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
9221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
9222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9224 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9225 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9226 GIR_EraseFromParent, /*InsnID*/0,
9227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9228 // GIR_Coverage, 2754,
9229 GIR_Done,
9230 // Label 495: @22186
9231 GIM_Reject,
9232 // Label 458: @22187
9233 GIM_Try, /*On fail goto*//*Label 496*/ 22221, // Rule ID 2637 //
9234 GIM_CheckFeatures, GIFBS_HasNEON,
9235 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9238 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src
9239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9242 GIR_EraseFromParent, /*InsnID*/0,
9243 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9244 // GIR_Coverage, 2637,
9245 GIR_Done,
9246 // Label 496: @22221
9247 GIM_Try, /*On fail goto*//*Label 497*/ 22255, // Rule ID 2638 //
9248 GIM_CheckFeatures, GIFBS_HasNEON,
9249 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
9250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9252 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src
9253 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9256 GIR_EraseFromParent, /*InsnID*/0,
9257 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9258 // GIR_Coverage, 2638,
9259 GIR_Done,
9260 // Label 497: @22255
9261 GIM_Try, /*On fail goto*//*Label 498*/ 22289, // Rule ID 2663 //
9262 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9263 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9266 // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src
9267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9270 GIR_EraseFromParent, /*InsnID*/0,
9271 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9272 // GIR_Coverage, 2663,
9273 GIR_Done,
9274 // Label 498: @22289
9275 GIM_Try, /*On fail goto*//*Label 499*/ 22323, // Rule ID 2664 //
9276 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9277 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9280 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src
9281 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9284 GIR_EraseFromParent, /*InsnID*/0,
9285 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9286 // GIR_Coverage, 2664,
9287 GIR_Done,
9288 // Label 499: @22323
9289 GIM_Try, /*On fail goto*//*Label 500*/ 22357, // Rule ID 2665 //
9290 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9291 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9294 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src
9295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9298 GIR_EraseFromParent, /*InsnID*/0,
9299 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9300 // GIR_Coverage, 2665,
9301 GIR_Done,
9302 // Label 500: @22357
9303 GIM_Try, /*On fail goto*//*Label 501*/ 22391, // Rule ID 2666 //
9304 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9305 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9308 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v2f32] }:$src
9309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9312 GIR_EraseFromParent, /*InsnID*/0,
9313 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9314 // GIR_Coverage, 2666,
9315 GIR_Done,
9316 // Label 501: @22391
9317 GIM_Try, /*On fail goto*//*Label 502*/ 22425, // Rule ID 2667 //
9318 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9319 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9322 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src
9323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9326 GIR_EraseFromParent, /*InsnID*/0,
9327 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9328 // GIR_Coverage, 2667,
9329 GIR_Done,
9330 // Label 502: @22425
9331 GIM_Try, /*On fail goto*//*Label 503*/ 22459, // Rule ID 2668 //
9332 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9333 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9336 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src
9337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9340 GIR_EraseFromParent, /*InsnID*/0,
9341 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9342 // GIR_Coverage, 2668,
9343 GIR_Done,
9344 // Label 503: @22459
9345 GIM_Try, /*On fail goto*//*Label 504*/ 22493, // Rule ID 2669 //
9346 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9347 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9350 // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src
9351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9354 GIR_EraseFromParent, /*InsnID*/0,
9355 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9356 // GIR_Coverage, 2669,
9357 GIR_Done,
9358 // Label 504: @22493
9359 GIM_Try, /*On fail goto*//*Label 505*/ 22527, // Rule ID 2670 //
9360 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9361 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9364 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src
9365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9368 GIR_EraseFromParent, /*InsnID*/0,
9369 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9370 // GIR_Coverage, 2670,
9371 GIR_Done,
9372 // Label 505: @22527
9373 GIM_Try, /*On fail goto*//*Label 506*/ 22561, // Rule ID 2671 //
9374 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9375 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9378 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src
9379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9382 GIR_EraseFromParent, /*InsnID*/0,
9383 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9384 // GIR_Coverage, 2671,
9385 GIR_Done,
9386 // Label 506: @22561
9387 GIM_Try, /*On fail goto*//*Label 507*/ 22595, // Rule ID 2672 //
9388 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9389 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9392 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v2i32] }:$src
9393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9396 GIR_EraseFromParent, /*InsnID*/0,
9397 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9398 // GIR_Coverage, 2672,
9399 GIR_Done,
9400 // Label 507: @22595
9401 GIM_Try, /*On fail goto*//*Label 508*/ 22629, // Rule ID 2673 //
9402 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9403 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9406 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src
9407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9410 GIR_EraseFromParent, /*InsnID*/0,
9411 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9412 // GIR_Coverage, 2673,
9413 GIR_Done,
9414 // Label 508: @22629
9415 GIM_Try, /*On fail goto*//*Label 509*/ 22663, // Rule ID 2674 //
9416 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9417 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9420 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src
9421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9424 GIR_EraseFromParent, /*InsnID*/0,
9425 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
9426 // GIR_Coverage, 2674,
9427 GIR_Done,
9428 // Label 509: @22663
9429 GIM_Try, /*On fail goto*//*Label 510*/ 22702, // Rule ID 2755 //
9430 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9431 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9434 // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
9435 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9438 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9439 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9440 GIR_EraseFromParent, /*InsnID*/0,
9441 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9442 // GIR_Coverage, 2755,
9443 GIR_Done,
9444 // Label 510: @22702
9445 GIM_Try, /*On fail goto*//*Label 511*/ 22741, // Rule ID 2756 //
9446 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9447 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9450 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
9451 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9454 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9455 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9456 GIR_EraseFromParent, /*InsnID*/0,
9457 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9458 // GIR_Coverage, 2756,
9459 GIR_Done,
9460 // Label 511: @22741
9461 GIM_Try, /*On fail goto*//*Label 512*/ 22780, // Rule ID 2757 //
9462 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9463 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9466 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
9467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9470 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9471 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9472 GIR_EraseFromParent, /*InsnID*/0,
9473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9474 // GIR_Coverage, 2757,
9475 GIR_Done,
9476 // Label 512: @22780
9477 GIM_Try, /*On fail goto*//*Label 513*/ 22819, // Rule ID 2758 //
9478 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9479 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9482 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4bf16] }:$src)
9483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9486 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9487 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9488 GIR_EraseFromParent, /*InsnID*/0,
9489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9490 // GIR_Coverage, 2758,
9491 GIR_Done,
9492 // Label 513: @22819
9493 GIM_Try, /*On fail goto*//*Label 514*/ 22858, // Rule ID 2759 //
9494 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9495 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9498 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
9499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9502 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9503 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9504 GIR_EraseFromParent, /*InsnID*/0,
9505 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9506 // GIR_Coverage, 2759,
9507 GIR_Done,
9508 // Label 514: @22858
9509 GIM_Try, /*On fail goto*//*Label 515*/ 22897, // Rule ID 2760 //
9510 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9511 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9514 // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
9515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
9516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9518 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9519 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9520 GIR_EraseFromParent, /*InsnID*/0,
9521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9522 // GIR_Coverage, 2760,
9523 GIR_Done,
9524 // Label 515: @22897
9525 GIM_Try, /*On fail goto*//*Label 516*/ 22936, // Rule ID 2761 //
9526 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9527 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9530 // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
9531 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9534 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9535 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9536 GIR_EraseFromParent, /*InsnID*/0,
9537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9538 // GIR_Coverage, 2761,
9539 GIR_Done,
9540 // Label 516: @22936
9541 GIM_Try, /*On fail goto*//*Label 517*/ 22975, // Rule ID 2762 //
9542 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9543 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
9544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9546 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
9547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
9548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9550 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9551 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9552 GIR_EraseFromParent, /*InsnID*/0,
9553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9554 // GIR_Coverage, 2762,
9555 GIR_Done,
9556 // Label 517: @22975
9557 GIM_Try, /*On fail goto*//*Label 518*/ 23014, // Rule ID 2763 //
9558 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9559 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9562 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
9563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9566 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9567 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9568 GIR_EraseFromParent, /*InsnID*/0,
9569 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9570 // GIR_Coverage, 2763,
9571 GIR_Done,
9572 // Label 518: @23014
9573 GIM_Try, /*On fail goto*//*Label 519*/ 23053, // Rule ID 2764 //
9574 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9575 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9578 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4bf16] }:$src)
9579 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9582 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9583 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9584 GIR_EraseFromParent, /*InsnID*/0,
9585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9586 // GIR_Coverage, 2764,
9587 GIR_Done,
9588 // Label 519: @23053
9589 GIM_Try, /*On fail goto*//*Label 520*/ 23092, // Rule ID 2765 //
9590 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9591 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
9592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9594 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
9595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
9596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9598 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9599 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9600 GIR_EraseFromParent, /*InsnID*/0,
9601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9602 // GIR_Coverage, 2765,
9603 GIR_Done,
9604 // Label 520: @23092
9605 GIM_Try, /*On fail goto*//*Label 521*/ 23131, // Rule ID 2766 //
9606 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9607 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
9608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
9610 // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
9611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
9612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9614 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9615 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9616 GIR_EraseFromParent, /*InsnID*/0,
9617 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9618 // GIR_Coverage, 2766,
9619 GIR_Done,
9620 // Label 521: @23131
9621 GIM_Reject,
9622 // Label 459: @23132
9623 GIM_Try, /*On fail goto*//*Label 522*/ 23166, // Rule ID 2643 //
9624 GIM_CheckFeatures, GIFBS_HasNEON,
9625 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9628 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src
9629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9632 GIR_EraseFromParent, /*InsnID*/0,
9633 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9634 // GIR_Coverage, 2643,
9635 GIR_Done,
9636 // Label 522: @23166
9637 GIM_Try, /*On fail goto*//*Label 523*/ 23200, // Rule ID 2644 //
9638 GIM_CheckFeatures, GIFBS_HasNEON,
9639 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
9640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9642 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src
9643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9646 GIR_EraseFromParent, /*InsnID*/0,
9647 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9648 // GIR_Coverage, 2644,
9649 GIR_Done,
9650 // Label 523: @23200
9651 GIM_Try, /*On fail goto*//*Label 524*/ 23234, // Rule ID 2697 //
9652 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9653 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9656 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src
9657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9660 GIR_EraseFromParent, /*InsnID*/0,
9661 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9662 // GIR_Coverage, 2697,
9663 GIR_Done,
9664 // Label 524: @23234
9665 GIM_Try, /*On fail goto*//*Label 525*/ 23268, // Rule ID 2698 //
9666 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9667 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9670 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src
9671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9674 GIR_EraseFromParent, /*InsnID*/0,
9675 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9676 // GIR_Coverage, 2698,
9677 GIR_Done,
9678 // Label 525: @23268
9679 GIM_Try, /*On fail goto*//*Label 526*/ 23302, // Rule ID 2699 //
9680 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9681 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9684 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src
9685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9688 GIR_EraseFromParent, /*InsnID*/0,
9689 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9690 // GIR_Coverage, 2699,
9691 GIR_Done,
9692 // Label 526: @23302
9693 GIM_Try, /*On fail goto*//*Label 527*/ 23336, // Rule ID 2700 //
9694 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9695 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9698 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v2f64] }:$src
9699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9702 GIR_EraseFromParent, /*InsnID*/0,
9703 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9704 // GIR_Coverage, 2700,
9705 GIR_Done,
9706 // Label 527: @23336
9707 GIM_Try, /*On fail goto*//*Label 528*/ 23370, // Rule ID 2701 //
9708 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9709 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9712 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src
9713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9716 GIR_EraseFromParent, /*InsnID*/0,
9717 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9718 // GIR_Coverage, 2701,
9719 GIR_Done,
9720 // Label 528: @23370
9721 GIM_Try, /*On fail goto*//*Label 529*/ 23404, // Rule ID 2702 //
9722 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9723 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9726 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src
9727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9730 GIR_EraseFromParent, /*InsnID*/0,
9731 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9732 // GIR_Coverage, 2702,
9733 GIR_Done,
9734 // Label 529: @23404
9735 GIM_Try, /*On fail goto*//*Label 530*/ 23438, // Rule ID 2703 //
9736 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9740 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src
9741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9744 GIR_EraseFromParent, /*InsnID*/0,
9745 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9746 // GIR_Coverage, 2703,
9747 GIR_Done,
9748 // Label 530: @23438
9749 GIM_Try, /*On fail goto*//*Label 531*/ 23472, // Rule ID 2704 //
9750 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9751 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9754 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src
9755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9758 GIR_EraseFromParent, /*InsnID*/0,
9759 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9760 // GIR_Coverage, 2704,
9761 GIR_Done,
9762 // Label 531: @23472
9763 GIM_Try, /*On fail goto*//*Label 532*/ 23506, // Rule ID 2705 //
9764 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9765 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9768 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src
9769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9772 GIR_EraseFromParent, /*InsnID*/0,
9773 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9774 // GIR_Coverage, 2705,
9775 GIR_Done,
9776 // Label 532: @23506
9777 GIM_Try, /*On fail goto*//*Label 533*/ 23540, // Rule ID 2706 //
9778 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9779 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9782 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v2i64] }:$src
9783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9786 GIR_EraseFromParent, /*InsnID*/0,
9787 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9788 // GIR_Coverage, 2706,
9789 GIR_Done,
9790 // Label 533: @23540
9791 GIM_Try, /*On fail goto*//*Label 534*/ 23574, // Rule ID 2707 //
9792 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9793 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9796 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src
9797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9800 GIR_EraseFromParent, /*InsnID*/0,
9801 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9802 // GIR_Coverage, 2707,
9803 GIR_Done,
9804 // Label 534: @23574
9805 GIM_Try, /*On fail goto*//*Label 535*/ 23608, // Rule ID 2708 //
9806 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
9807 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9810 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src
9811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
9813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9814 GIR_EraseFromParent, /*InsnID*/0,
9815 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
9816 // GIR_Coverage, 2708,
9817 GIR_Done,
9818 // Label 535: @23608
9819 GIM_Try, /*On fail goto*//*Label 536*/ 23647, // Rule ID 2789 //
9820 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9821 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9824 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
9825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9828 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9829 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9830 GIR_EraseFromParent, /*InsnID*/0,
9831 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9832 // GIR_Coverage, 2789,
9833 GIR_Done,
9834 // Label 536: @23647
9835 GIM_Try, /*On fail goto*//*Label 537*/ 23686, // Rule ID 2790 //
9836 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9837 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9840 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
9841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9844 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9845 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9846 GIR_EraseFromParent, /*InsnID*/0,
9847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9848 // GIR_Coverage, 2790,
9849 GIR_Done,
9850 // Label 537: @23686
9851 GIM_Try, /*On fail goto*//*Label 538*/ 23725, // Rule ID 2791 //
9852 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9853 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9856 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
9857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9860 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9861 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9862 GIR_EraseFromParent, /*InsnID*/0,
9863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9864 // GIR_Coverage, 2791,
9865 GIR_Done,
9866 // Label 538: @23725
9867 GIM_Try, /*On fail goto*//*Label 539*/ 23764, // Rule ID 2792 //
9868 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9869 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9872 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8bf16] }:$src)
9873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9876 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9877 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9878 GIR_EraseFromParent, /*InsnID*/0,
9879 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9880 // GIR_Coverage, 2792,
9881 GIR_Done,
9882 // Label 539: @23764
9883 GIM_Try, /*On fail goto*//*Label 540*/ 23803, // Rule ID 2793 //
9884 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9885 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9888 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
9889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9892 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9893 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9894 GIR_EraseFromParent, /*InsnID*/0,
9895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9896 // GIR_Coverage, 2793,
9897 GIR_Done,
9898 // Label 540: @23803
9899 GIM_Try, /*On fail goto*//*Label 541*/ 23842, // Rule ID 2794 //
9900 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9901 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9904 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
9905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
9906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9908 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9909 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9910 GIR_EraseFromParent, /*InsnID*/0,
9911 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9912 // GIR_Coverage, 2794,
9913 GIR_Done,
9914 // Label 541: @23842
9915 GIM_Try, /*On fail goto*//*Label 542*/ 23881, // Rule ID 2795 //
9916 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9917 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9920 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
9921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9924 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9925 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9926 GIR_EraseFromParent, /*InsnID*/0,
9927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9928 // GIR_Coverage, 2795,
9929 GIR_Done,
9930 // Label 542: @23881
9931 GIM_Try, /*On fail goto*//*Label 543*/ 23920, // Rule ID 2796 //
9932 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9933 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
9934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9936 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
9937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9940 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9942 GIR_EraseFromParent, /*InsnID*/0,
9943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9944 // GIR_Coverage, 2796,
9945 GIR_Done,
9946 // Label 543: @23920
9947 GIM_Try, /*On fail goto*//*Label 544*/ 23959, // Rule ID 2797 //
9948 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9949 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9952 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
9953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9956 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9957 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9958 GIR_EraseFromParent, /*InsnID*/0,
9959 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9960 // GIR_Coverage, 2797,
9961 GIR_Done,
9962 // Label 544: @23959
9963 GIM_Try, /*On fail goto*//*Label 545*/ 23998, // Rule ID 2798 //
9964 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9965 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9968 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8bf16] }:$src)
9969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9972 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9973 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9974 GIR_EraseFromParent, /*InsnID*/0,
9975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9976 // GIR_Coverage, 2798,
9977 GIR_Done,
9978 // Label 545: @23998
9979 GIM_Try, /*On fail goto*//*Label 546*/ 24037, // Rule ID 2799 //
9980 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9981 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
9982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
9984 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
9985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
9986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
9988 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9989 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
9990 GIR_EraseFromParent, /*InsnID*/0,
9991 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9992 // GIR_Coverage, 2799,
9993 GIR_Done,
9994 // Label 546: @24037
9995 GIM_Try, /*On fail goto*//*Label 547*/ 24076, // Rule ID 2800 //
9996 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
9997 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
9998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10000 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
10001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
10002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10004 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10005 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10006 GIR_EraseFromParent, /*InsnID*/0,
10007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10008 // GIR_Coverage, 2800,
10009 GIR_Done,
10010 // Label 547: @24076
10011 GIM_Try, /*On fail goto*//*Label 548*/ 24110, // Rule ID 5157 //
10012 GIM_CheckFeatures, GIFBS_HasMVEInt,
10013 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10016 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src
10017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10020 GIR_EraseFromParent, /*InsnID*/0,
10021 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10022 // GIR_Coverage, 5157,
10023 GIR_Done,
10024 // Label 548: @24110
10025 GIM_Try, /*On fail goto*//*Label 549*/ 24144, // Rule ID 5158 //
10026 GIM_CheckFeatures, GIFBS_HasMVEInt,
10027 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10030 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src
10031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10034 GIR_EraseFromParent, /*InsnID*/0,
10035 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10036 // GIR_Coverage, 5158,
10037 GIR_Done,
10038 // Label 549: @24144
10039 GIM_Try, /*On fail goto*//*Label 550*/ 24178, // Rule ID 5163 //
10040 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10041 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10044 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src
10045 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10048 GIR_EraseFromParent, /*InsnID*/0,
10049 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10050 // GIR_Coverage, 5163,
10051 GIR_Done,
10052 // Label 550: @24178
10053 GIM_Try, /*On fail goto*//*Label 551*/ 24212, // Rule ID 5164 //
10054 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10055 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10058 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src
10059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10062 GIR_EraseFromParent, /*InsnID*/0,
10063 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10064 // GIR_Coverage, 5164,
10065 GIR_Done,
10066 // Label 551: @24212
10067 GIM_Try, /*On fail goto*//*Label 552*/ 24246, // Rule ID 5165 //
10068 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10069 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10072 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src
10073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10076 GIR_EraseFromParent, /*InsnID*/0,
10077 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10078 // GIR_Coverage, 5165,
10079 GIR_Done,
10080 // Label 552: @24246
10081 GIM_Try, /*On fail goto*//*Label 553*/ 24280, // Rule ID 5166 //
10082 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10083 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10086 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src
10087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10090 GIR_EraseFromParent, /*InsnID*/0,
10091 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10092 // GIR_Coverage, 5166,
10093 GIR_Done,
10094 // Label 553: @24280
10095 GIM_Try, /*On fail goto*//*Label 554*/ 24314, // Rule ID 5167 //
10096 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10097 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10100 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src
10101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10103 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10104 GIR_EraseFromParent, /*InsnID*/0,
10105 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10106 // GIR_Coverage, 5167,
10107 GIR_Done,
10108 // Label 554: @24314
10109 GIM_Try, /*On fail goto*//*Label 555*/ 24348, // Rule ID 5168 //
10110 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10111 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10114 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src
10115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10118 GIR_EraseFromParent, /*InsnID*/0,
10119 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10120 // GIR_Coverage, 5168,
10121 GIR_Done,
10122 // Label 555: @24348
10123 GIM_Try, /*On fail goto*//*Label 556*/ 24382, // Rule ID 5169 //
10124 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10125 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10128 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src
10129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10132 GIR_EraseFromParent, /*InsnID*/0,
10133 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10134 // GIR_Coverage, 5169,
10135 GIR_Done,
10136 // Label 556: @24382
10137 GIM_Try, /*On fail goto*//*Label 557*/ 24416, // Rule ID 5170 //
10138 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10139 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10142 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src
10143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10146 GIR_EraseFromParent, /*InsnID*/0,
10147 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10148 // GIR_Coverage, 5170,
10149 GIR_Done,
10150 // Label 557: @24416
10151 GIM_Try, /*On fail goto*//*Label 558*/ 24450, // Rule ID 5171 //
10152 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10153 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10156 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src
10157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10160 GIR_EraseFromParent, /*InsnID*/0,
10161 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10162 // GIR_Coverage, 5171,
10163 GIR_Done,
10164 // Label 558: @24450
10165 GIM_Try, /*On fail goto*//*Label 559*/ 24484, // Rule ID 5172 //
10166 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
10167 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10170 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src
10171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10174 GIR_EraseFromParent, /*InsnID*/0,
10175 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
10176 // GIR_Coverage, 5172,
10177 GIR_Done,
10178 // Label 559: @24484
10179 GIM_Try, /*On fail goto*//*Label 560*/ 24537, // Rule ID 5199 //
10180 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10181 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10184 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
10185 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10186 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10187 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10191 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10192 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10193 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10194 GIR_EraseFromParent, /*InsnID*/0,
10195 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10196 // GIR_Coverage, 5199,
10197 GIR_Done,
10198 // Label 560: @24537
10199 GIM_Try, /*On fail goto*//*Label 561*/ 24590, // Rule ID 5200 //
10200 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10201 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10204 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
10205 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10206 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10207 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10211 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10212 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10213 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10214 GIR_EraseFromParent, /*InsnID*/0,
10215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10216 // GIR_Coverage, 5200,
10217 GIR_Done,
10218 // Label 561: @24590
10219 GIM_Try, /*On fail goto*//*Label 562*/ 24643, // Rule ID 5201 //
10220 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10221 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10224 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
10225 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10226 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10227 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10228 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10231 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10232 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10233 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10234 GIR_EraseFromParent, /*InsnID*/0,
10235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10236 // GIR_Coverage, 5201,
10237 GIR_Done,
10238 // Label 562: @24643
10239 GIM_Try, /*On fail goto*//*Label 563*/ 24696, // Rule ID 5202 //
10240 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10241 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10244 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
10245 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10246 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10247 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10251 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10252 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10253 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10254 GIR_EraseFromParent, /*InsnID*/0,
10255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10256 // GIR_Coverage, 5202,
10257 GIR_Done,
10258 // Label 563: @24696
10259 GIM_Try, /*On fail goto*//*Label 564*/ 24749, // Rule ID 5203 //
10260 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10261 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10264 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
10265 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10267 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
10269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10271 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10272 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10273 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10274 GIR_EraseFromParent, /*InsnID*/0,
10275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10276 // GIR_Coverage, 5203,
10277 GIR_Done,
10278 // Label 564: @24749
10279 GIM_Try, /*On fail goto*//*Label 565*/ 24802, // Rule ID 5204 //
10280 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10281 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10284 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
10285 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10286 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10287 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10291 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10292 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10293 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10294 GIR_EraseFromParent, /*InsnID*/0,
10295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10296 // GIR_Coverage, 5204,
10297 GIR_Done,
10298 // Label 565: @24802
10299 GIM_Try, /*On fail goto*//*Label 566*/ 24855, // Rule ID 5205 //
10300 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10301 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10304 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
10305 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10306 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10307 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
10309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10311 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10312 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10313 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10314 GIR_EraseFromParent, /*InsnID*/0,
10315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10316 // GIR_Coverage, 5205,
10317 GIR_Done,
10318 // Label 566: @24855
10319 GIM_Try, /*On fail goto*//*Label 567*/ 24908, // Rule ID 5206 //
10320 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10321 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10324 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
10325 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10326 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10327 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10331 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10332 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10333 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10334 GIR_EraseFromParent, /*InsnID*/0,
10335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10336 // GIR_Coverage, 5206,
10337 GIR_Done,
10338 // Label 567: @24908
10339 GIM_Try, /*On fail goto*//*Label 568*/ 24961, // Rule ID 5207 //
10340 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10341 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10344 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
10345 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10346 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10347 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
10349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10351 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10352 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10353 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10354 GIR_EraseFromParent, /*InsnID*/0,
10355 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10356 // GIR_Coverage, 5207,
10357 GIR_Done,
10358 // Label 568: @24961
10359 GIM_Try, /*On fail goto*//*Label 569*/ 25014, // Rule ID 5208 //
10360 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
10361 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
10363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
10364 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
10365 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10366 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
10367 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
10368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
10369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
10370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10371 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10372 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10373 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
10374 GIR_EraseFromParent, /*InsnID*/0,
10375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10376 // GIR_Coverage, 5208,
10377 GIR_Done,
10378 // Label 569: @25014
10379 GIM_Reject,
10380 // Label 460: @25015
10381 GIM_Try, /*On fail goto*//*Label 570*/ 25049, // Rule ID 2639 //
10382 GIM_CheckFeatures, GIFBS_HasNEON,
10383 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10386 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src
10387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10390 GIR_EraseFromParent, /*InsnID*/0,
10391 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10392 // GIR_Coverage, 2639,
10393 GIR_Done,
10394 // Label 570: @25049
10395 GIM_Try, /*On fail goto*//*Label 571*/ 25083, // Rule ID 2640 //
10396 GIM_CheckFeatures, GIFBS_HasNEON,
10397 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10400 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src
10401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10404 GIR_EraseFromParent, /*InsnID*/0,
10405 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10406 // GIR_Coverage, 2640,
10407 GIR_Done,
10408 // Label 571: @25083
10409 GIM_Try, /*On fail goto*//*Label 572*/ 25117, // Rule ID 2641 //
10410 GIM_CheckFeatures, GIFBS_HasNEON,
10411 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10414 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v4i16] }:$src
10415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10418 GIR_EraseFromParent, /*InsnID*/0,
10419 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10420 // GIR_Coverage, 2641,
10421 GIR_Done,
10422 // Label 572: @25117
10423 GIM_Try, /*On fail goto*//*Label 573*/ 25151, // Rule ID 2642 //
10424 GIM_CheckFeatures, GIFBS_HasNEON,
10425 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
10426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10428 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4bf16] }:$src
10429 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10432 GIR_EraseFromParent, /*InsnID*/0,
10433 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10434 // GIR_Coverage, 2642,
10435 GIR_Done,
10436 // Label 573: @25151
10437 GIM_Try, /*On fail goto*//*Label 574*/ 25185, // Rule ID 2675 //
10438 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10439 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10442 // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src
10443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10446 GIR_EraseFromParent, /*InsnID*/0,
10447 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10448 // GIR_Coverage, 2675,
10449 GIR_Done,
10450 // Label 574: @25185
10451 GIM_Try, /*On fail goto*//*Label 575*/ 25219, // Rule ID 2676 //
10452 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10453 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10456 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src
10457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10460 GIR_EraseFromParent, /*InsnID*/0,
10461 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10462 // GIR_Coverage, 2676,
10463 GIR_Done,
10464 // Label 575: @25219
10465 GIM_Try, /*On fail goto*//*Label 576*/ 25253, // Rule ID 2677 //
10466 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10467 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10470 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src
10471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10474 GIR_EraseFromParent, /*InsnID*/0,
10475 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10476 // GIR_Coverage, 2677,
10477 GIR_Done,
10478 // Label 576: @25253
10479 GIM_Try, /*On fail goto*//*Label 577*/ 25287, // Rule ID 2678 //
10480 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10481 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10484 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src
10485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10488 GIR_EraseFromParent, /*InsnID*/0,
10489 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10490 // GIR_Coverage, 2678,
10491 GIR_Done,
10492 // Label 577: @25287
10493 GIM_Try, /*On fail goto*//*Label 578*/ 25321, // Rule ID 2679 //
10494 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10495 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10498 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src
10499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10502 GIR_EraseFromParent, /*InsnID*/0,
10503 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10504 // GIR_Coverage, 2679,
10505 GIR_Done,
10506 // Label 578: @25321
10507 GIM_Try, /*On fail goto*//*Label 579*/ 25355, // Rule ID 2680 //
10508 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10509 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10512 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4bf16] }:$src
10513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10516 GIR_EraseFromParent, /*InsnID*/0,
10517 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10518 // GIR_Coverage, 2680,
10519 GIR_Done,
10520 // Label 579: @25355
10521 GIM_Try, /*On fail goto*//*Label 580*/ 25389, // Rule ID 2681 //
10522 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10523 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10526 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4bf16] }:$src
10527 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10530 GIR_EraseFromParent, /*InsnID*/0,
10531 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10532 // GIR_Coverage, 2681,
10533 GIR_Done,
10534 // Label 580: @25389
10535 GIM_Try, /*On fail goto*//*Label 581*/ 25423, // Rule ID 2682 //
10536 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10537 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10540 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4bf16] }:$src
10541 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10544 GIR_EraseFromParent, /*InsnID*/0,
10545 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10546 // GIR_Coverage, 2682,
10547 GIR_Done,
10548 // Label 581: @25423
10549 GIM_Try, /*On fail goto*//*Label 582*/ 25457, // Rule ID 2683 //
10550 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10551 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10554 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4bf16] }:$src
10555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10558 GIR_EraseFromParent, /*InsnID*/0,
10559 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10560 // GIR_Coverage, 2683,
10561 GIR_Done,
10562 // Label 582: @25457
10563 GIM_Try, /*On fail goto*//*Label 583*/ 25491, // Rule ID 2684 //
10564 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10565 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10568 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4bf16] }:$src
10569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10572 GIR_EraseFromParent, /*InsnID*/0,
10573 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10574 // GIR_Coverage, 2684,
10575 GIR_Done,
10576 // Label 583: @25491
10577 GIM_Try, /*On fail goto*//*Label 584*/ 25525, // Rule ID 2685 //
10578 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10579 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10582 // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src
10583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10586 GIR_EraseFromParent, /*InsnID*/0,
10587 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10588 // GIR_Coverage, 2685,
10589 GIR_Done,
10590 // Label 584: @25525
10591 GIM_Try, /*On fail goto*//*Label 585*/ 25559, // Rule ID 2686 //
10592 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10593 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10596 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src
10597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10600 GIR_EraseFromParent, /*InsnID*/0,
10601 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10602 // GIR_Coverage, 2686,
10603 GIR_Done,
10604 // Label 585: @25559
10605 GIM_Try, /*On fail goto*//*Label 586*/ 25593, // Rule ID 2687 //
10606 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10607 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10610 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src
10611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10614 GIR_EraseFromParent, /*InsnID*/0,
10615 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10616 // GIR_Coverage, 2687,
10617 GIR_Done,
10618 // Label 586: @25593
10619 GIM_Try, /*On fail goto*//*Label 587*/ 25627, // Rule ID 2688 //
10620 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10621 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10624 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src
10625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10628 GIR_EraseFromParent, /*InsnID*/0,
10629 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10630 // GIR_Coverage, 2688,
10631 GIR_Done,
10632 // Label 587: @25627
10633 GIM_Try, /*On fail goto*//*Label 588*/ 25661, // Rule ID 2689 //
10634 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10635 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10638 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src
10639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10642 GIR_EraseFromParent, /*InsnID*/0,
10643 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
10644 // GIR_Coverage, 2689,
10645 GIR_Done,
10646 // Label 588: @25661
10647 GIM_Try, /*On fail goto*//*Label 589*/ 25700, // Rule ID 2767 //
10648 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10649 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10652 // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
10653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
10654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10656 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10657 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10658 GIR_EraseFromParent, /*InsnID*/0,
10659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10660 // GIR_Coverage, 2767,
10661 GIR_Done,
10662 // Label 589: @25700
10663 GIM_Try, /*On fail goto*//*Label 590*/ 25739, // Rule ID 2768 //
10664 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10665 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10668 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
10669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
10670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10672 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10673 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10674 GIR_EraseFromParent, /*InsnID*/0,
10675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10676 // GIR_Coverage, 2768,
10677 GIR_Done,
10678 // Label 590: @25739
10679 GIM_Try, /*On fail goto*//*Label 591*/ 25778, // Rule ID 2769 //
10680 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10681 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10684 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
10685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10688 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10689 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10690 GIR_EraseFromParent, /*InsnID*/0,
10691 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10692 // GIR_Coverage, 2769,
10693 GIR_Done,
10694 // Label 591: @25778
10695 GIM_Try, /*On fail goto*//*Label 592*/ 25817, // Rule ID 2770 //
10696 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10697 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10700 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
10701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10704 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10705 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10706 GIR_EraseFromParent, /*InsnID*/0,
10707 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10708 // GIR_Coverage, 2770,
10709 GIR_Done,
10710 // Label 592: @25817
10711 GIM_Try, /*On fail goto*//*Label 593*/ 25856, // Rule ID 2771 //
10712 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10713 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10716 // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
10717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10720 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10721 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10722 GIR_EraseFromParent, /*InsnID*/0,
10723 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10724 // GIR_Coverage, 2771,
10725 GIR_Done,
10726 // Label 593: @25856
10727 GIM_Try, /*On fail goto*//*Label 594*/ 25895, // Rule ID 2772 //
10728 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10729 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10732 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4bf16] } DPR:{ *:[f64] }:$src)
10733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
10734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10736 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10737 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10738 GIR_EraseFromParent, /*InsnID*/0,
10739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10740 // GIR_Coverage, 2772,
10741 GIR_Done,
10742 // Label 594: @25895
10743 GIM_Try, /*On fail goto*//*Label 595*/ 25934, // Rule ID 2773 //
10744 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10745 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10748 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4bf16] } DPR:{ *:[v1i64] }:$src)
10749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
10750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10752 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10753 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10754 GIR_EraseFromParent, /*InsnID*/0,
10755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10756 // GIR_Coverage, 2773,
10757 GIR_Done,
10758 // Label 595: @25934
10759 GIM_Try, /*On fail goto*//*Label 596*/ 25973, // Rule ID 2774 //
10760 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10761 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10764 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2f32] }:$src)
10765 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10768 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10769 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10770 GIR_EraseFromParent, /*InsnID*/0,
10771 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10772 // GIR_Coverage, 2774,
10773 GIR_Done,
10774 // Label 596: @25973
10775 GIM_Try, /*On fail goto*//*Label 597*/ 26012, // Rule ID 2775 //
10776 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10777 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10780 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4bf16] } DPR:{ *:[v2i32] }:$src)
10781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10784 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10785 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10786 GIR_EraseFromParent, /*InsnID*/0,
10787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10788 // GIR_Coverage, 2775,
10789 GIR_Done,
10790 // Label 597: @26012
10791 GIM_Try, /*On fail goto*//*Label 598*/ 26051, // Rule ID 2776 //
10792 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10793 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10796 // (bitconvert:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4bf16] } DPR:{ *:[v8i8] }:$src)
10797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10800 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10801 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10802 GIR_EraseFromParent, /*InsnID*/0,
10803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10804 // GIR_Coverage, 2776,
10805 GIR_Done,
10806 // Label 598: @26051
10807 GIM_Try, /*On fail goto*//*Label 599*/ 26090, // Rule ID 2777 //
10808 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10809 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10812 // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
10813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
10814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10816 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10817 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10818 GIR_EraseFromParent, /*InsnID*/0,
10819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10820 // GIR_Coverage, 2777,
10821 GIR_Done,
10822 // Label 599: @26090
10823 GIM_Try, /*On fail goto*//*Label 600*/ 26129, // Rule ID 2778 //
10824 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10825 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
10826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10828 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
10829 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
10830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10832 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10833 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10834 GIR_EraseFromParent, /*InsnID*/0,
10835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10836 // GIR_Coverage, 2778,
10837 GIR_Done,
10838 // Label 600: @26129
10839 GIM_Try, /*On fail goto*//*Label 601*/ 26168, // Rule ID 2779 //
10840 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10841 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10844 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
10845 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10848 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10849 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10850 GIR_EraseFromParent, /*InsnID*/0,
10851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10852 // GIR_Coverage, 2779,
10853 GIR_Done,
10854 // Label 601: @26168
10855 GIM_Try, /*On fail goto*//*Label 602*/ 26207, // Rule ID 2780 //
10856 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10857 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
10858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10860 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
10861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
10862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10864 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10865 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10866 GIR_EraseFromParent, /*InsnID*/0,
10867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10868 // GIR_Coverage, 2780,
10869 GIR_Done,
10870 // Label 602: @26207
10871 GIM_Try, /*On fail goto*//*Label 603*/ 26246, // Rule ID 2781 //
10872 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
10873 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
10874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
10876 // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
10877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
10878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10880 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10881 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
10882 GIR_EraseFromParent, /*InsnID*/0,
10883 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10884 // GIR_Coverage, 2781,
10885 GIR_Done,
10886 // Label 603: @26246
10887 GIM_Reject,
10888 // Label 461: @26247
10889 GIM_Try, /*On fail goto*//*Label 604*/ 26281, // Rule ID 2645 //
10890 GIM_CheckFeatures, GIFBS_HasNEON,
10891 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10894 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src
10895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10898 GIR_EraseFromParent, /*InsnID*/0,
10899 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10900 // GIR_Coverage, 2645,
10901 GIR_Done,
10902 // Label 604: @26281
10903 GIM_Try, /*On fail goto*//*Label 605*/ 26315, // Rule ID 2646 //
10904 GIM_CheckFeatures, GIFBS_HasNEON,
10905 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
10906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10908 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src
10909 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10912 GIR_EraseFromParent, /*InsnID*/0,
10913 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10914 // GIR_Coverage, 2646,
10915 GIR_Done,
10916 // Label 605: @26315
10917 GIM_Try, /*On fail goto*//*Label 606*/ 26349, // Rule ID 2709 //
10918 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10919 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10922 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src
10923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10926 GIR_EraseFromParent, /*InsnID*/0,
10927 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10928 // GIR_Coverage, 2709,
10929 GIR_Done,
10930 // Label 606: @26349
10931 GIM_Try, /*On fail goto*//*Label 607*/ 26383, // Rule ID 2710 //
10932 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10933 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
10934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10936 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src
10937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10940 GIR_EraseFromParent, /*InsnID*/0,
10941 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10942 // GIR_Coverage, 2710,
10943 GIR_Done,
10944 // Label 607: @26383
10945 GIM_Try, /*On fail goto*//*Label 608*/ 26417, // Rule ID 2711 //
10946 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10950 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src
10951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10954 GIR_EraseFromParent, /*InsnID*/0,
10955 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10956 // GIR_Coverage, 2711,
10957 GIR_Done,
10958 // Label 608: @26417
10959 GIM_Try, /*On fail goto*//*Label 609*/ 26451, // Rule ID 2712 //
10960 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10961 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10964 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v4f32] }:$src
10965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10968 GIR_EraseFromParent, /*InsnID*/0,
10969 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10970 // GIR_Coverage, 2712,
10971 GIR_Done,
10972 // Label 609: @26451
10973 GIM_Try, /*On fail goto*//*Label 610*/ 26485, // Rule ID 2713 //
10974 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10975 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
10976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10978 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src
10979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10982 GIR_EraseFromParent, /*InsnID*/0,
10983 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10984 // GIR_Coverage, 2713,
10985 GIR_Done,
10986 // Label 610: @26485
10987 GIM_Try, /*On fail goto*//*Label 611*/ 26519, // Rule ID 2714 //
10988 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
10989 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
10990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
10992 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src
10993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
10995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
10996 GIR_EraseFromParent, /*InsnID*/0,
10997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
10998 // GIR_Coverage, 2714,
10999 GIR_Done,
11000 // Label 611: @26519
11001 GIM_Try, /*On fail goto*//*Label 612*/ 26553, // Rule ID 2715 //
11002 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11003 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11006 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src
11007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11010 GIR_EraseFromParent, /*InsnID*/0,
11011 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11012 // GIR_Coverage, 2715,
11013 GIR_Done,
11014 // Label 612: @26553
11015 GIM_Try, /*On fail goto*//*Label 613*/ 26587, // Rule ID 2716 //
11016 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11017 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11020 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src
11021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11024 GIR_EraseFromParent, /*InsnID*/0,
11025 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11026 // GIR_Coverage, 2716,
11027 GIR_Done,
11028 // Label 613: @26587
11029 GIM_Try, /*On fail goto*//*Label 614*/ 26621, // Rule ID 2717 //
11030 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11031 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11034 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src
11035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11038 GIR_EraseFromParent, /*InsnID*/0,
11039 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11040 // GIR_Coverage, 2717,
11041 GIR_Done,
11042 // Label 614: @26621
11043 GIM_Try, /*On fail goto*//*Label 615*/ 26655, // Rule ID 2718 //
11044 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11045 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11048 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v4i32] }:$src
11049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11052 GIR_EraseFromParent, /*InsnID*/0,
11053 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11054 // GIR_Coverage, 2718,
11055 GIR_Done,
11056 // Label 615: @26655
11057 GIM_Try, /*On fail goto*//*Label 616*/ 26689, // Rule ID 2719 //
11058 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11059 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11062 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src
11063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11066 GIR_EraseFromParent, /*InsnID*/0,
11067 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11068 // GIR_Coverage, 2719,
11069 GIR_Done,
11070 // Label 616: @26689
11071 GIM_Try, /*On fail goto*//*Label 617*/ 26723, // Rule ID 2720 //
11072 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11073 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11076 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src
11077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11080 GIR_EraseFromParent, /*InsnID*/0,
11081 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11082 // GIR_Coverage, 2720,
11083 GIR_Done,
11084 // Label 617: @26723
11085 GIM_Try, /*On fail goto*//*Label 618*/ 26762, // Rule ID 2801 //
11086 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11087 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11090 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
11091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11094 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11095 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11096 GIR_EraseFromParent, /*InsnID*/0,
11097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11098 // GIR_Coverage, 2801,
11099 GIR_Done,
11100 // Label 618: @26762
11101 GIM_Try, /*On fail goto*//*Label 619*/ 26801, // Rule ID 2802 //
11102 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11103 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11106 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
11107 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11110 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11111 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11112 GIR_EraseFromParent, /*InsnID*/0,
11113 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11114 // GIR_Coverage, 2802,
11115 GIR_Done,
11116 // Label 619: @26801
11117 GIM_Try, /*On fail goto*//*Label 620*/ 26840, // Rule ID 2803 //
11118 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11119 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11122 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
11123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11126 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11127 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11128 GIR_EraseFromParent, /*InsnID*/0,
11129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11130 // GIR_Coverage, 2803,
11131 GIR_Done,
11132 // Label 620: @26840
11133 GIM_Try, /*On fail goto*//*Label 621*/ 26879, // Rule ID 2804 //
11134 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11135 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11138 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8bf16] }:$src)
11139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11142 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11143 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11144 GIR_EraseFromParent, /*InsnID*/0,
11145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11146 // GIR_Coverage, 2804,
11147 GIR_Done,
11148 // Label 621: @26879
11149 GIM_Try, /*On fail goto*//*Label 622*/ 26918, // Rule ID 2805 //
11150 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11151 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11154 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
11155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11158 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11159 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11160 GIR_EraseFromParent, /*InsnID*/0,
11161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11162 // GIR_Coverage, 2805,
11163 GIR_Done,
11164 // Label 622: @26918
11165 GIM_Try, /*On fail goto*//*Label 623*/ 26957, // Rule ID 2806 //
11166 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11167 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11170 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
11171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11174 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11175 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11176 GIR_EraseFromParent, /*InsnID*/0,
11177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11178 // GIR_Coverage, 2806,
11179 GIR_Done,
11180 // Label 623: @26957
11181 GIM_Try, /*On fail goto*//*Label 624*/ 26996, // Rule ID 2807 //
11182 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11183 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11186 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
11187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11190 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11191 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11192 GIR_EraseFromParent, /*InsnID*/0,
11193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11194 // GIR_Coverage, 2807,
11195 GIR_Done,
11196 // Label 624: @26996
11197 GIM_Try, /*On fail goto*//*Label 625*/ 27035, // Rule ID 2808 //
11198 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11199 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11202 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
11203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
11204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11206 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11207 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11208 GIR_EraseFromParent, /*InsnID*/0,
11209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11210 // GIR_Coverage, 2808,
11211 GIR_Done,
11212 // Label 625: @27035
11213 GIM_Try, /*On fail goto*//*Label 626*/ 27074, // Rule ID 2809 //
11214 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11215 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11218 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
11219 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11222 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11223 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11224 GIR_EraseFromParent, /*InsnID*/0,
11225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11226 // GIR_Coverage, 2809,
11227 GIR_Done,
11228 // Label 626: @27074
11229 GIM_Try, /*On fail goto*//*Label 627*/ 27113, // Rule ID 2810 //
11230 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11231 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11234 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8bf16] }:$src)
11235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11238 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11239 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11240 GIR_EraseFromParent, /*InsnID*/0,
11241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11242 // GIR_Coverage, 2810,
11243 GIR_Done,
11244 // Label 627: @27113
11245 GIM_Try, /*On fail goto*//*Label 628*/ 27152, // Rule ID 2811 //
11246 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11247 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11250 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
11251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
11252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11254 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11255 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11256 GIR_EraseFromParent, /*InsnID*/0,
11257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11258 // GIR_Coverage, 2811,
11259 GIR_Done,
11260 // Label 628: @27152
11261 GIM_Try, /*On fail goto*//*Label 629*/ 27191, // Rule ID 2812 //
11262 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11263 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11266 // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
11267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
11268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11270 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11271 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11272 GIR_EraseFromParent, /*InsnID*/0,
11273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11274 // GIR_Coverage, 2812,
11275 GIR_Done,
11276 // Label 629: @27191
11277 GIM_Try, /*On fail goto*//*Label 630*/ 27225, // Rule ID 5159 //
11278 GIM_CheckFeatures, GIFBS_HasMVEInt,
11279 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11282 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src
11283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11286 GIR_EraseFromParent, /*InsnID*/0,
11287 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11288 // GIR_Coverage, 5159,
11289 GIR_Done,
11290 // Label 630: @27225
11291 GIM_Try, /*On fail goto*//*Label 631*/ 27259, // Rule ID 5160 //
11292 GIM_CheckFeatures, GIFBS_HasMVEInt,
11293 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11296 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src
11297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11300 GIR_EraseFromParent, /*InsnID*/0,
11301 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11302 // GIR_Coverage, 5160,
11303 GIR_Done,
11304 // Label 631: @27259
11305 GIM_Try, /*On fail goto*//*Label 632*/ 27293, // Rule ID 5173 //
11306 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11307 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11310 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src
11311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11314 GIR_EraseFromParent, /*InsnID*/0,
11315 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11316 // GIR_Coverage, 5173,
11317 GIR_Done,
11318 // Label 632: @27293
11319 GIM_Try, /*On fail goto*//*Label 633*/ 27327, // Rule ID 5174 //
11320 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11321 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11324 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src
11325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11328 GIR_EraseFromParent, /*InsnID*/0,
11329 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11330 // GIR_Coverage, 5174,
11331 GIR_Done,
11332 // Label 633: @27327
11333 GIM_Try, /*On fail goto*//*Label 634*/ 27361, // Rule ID 5175 //
11334 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11335 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11338 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src
11339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11342 GIR_EraseFromParent, /*InsnID*/0,
11343 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11344 // GIR_Coverage, 5175,
11345 GIR_Done,
11346 // Label 634: @27361
11347 GIM_Try, /*On fail goto*//*Label 635*/ 27395, // Rule ID 5176 //
11348 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11349 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11352 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src
11353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11356 GIR_EraseFromParent, /*InsnID*/0,
11357 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11358 // GIR_Coverage, 5176,
11359 GIR_Done,
11360 // Label 635: @27395
11361 GIM_Try, /*On fail goto*//*Label 636*/ 27429, // Rule ID 5177 //
11362 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11363 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11366 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src
11367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11370 GIR_EraseFromParent, /*InsnID*/0,
11371 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11372 // GIR_Coverage, 5177,
11373 GIR_Done,
11374 // Label 636: @27429
11375 GIM_Try, /*On fail goto*//*Label 637*/ 27463, // Rule ID 5178 //
11376 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11377 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11380 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src
11381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11384 GIR_EraseFromParent, /*InsnID*/0,
11385 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11386 // GIR_Coverage, 5178,
11387 GIR_Done,
11388 // Label 637: @27463
11389 GIM_Try, /*On fail goto*//*Label 638*/ 27497, // Rule ID 5179 //
11390 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11391 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11394 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src
11395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11398 GIR_EraseFromParent, /*InsnID*/0,
11399 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11400 // GIR_Coverage, 5179,
11401 GIR_Done,
11402 // Label 638: @27497
11403 GIM_Try, /*On fail goto*//*Label 639*/ 27531, // Rule ID 5180 //
11404 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11405 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11408 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src
11409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11412 GIR_EraseFromParent, /*InsnID*/0,
11413 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11414 // GIR_Coverage, 5180,
11415 GIR_Done,
11416 // Label 639: @27531
11417 GIM_Try, /*On fail goto*//*Label 640*/ 27565, // Rule ID 5181 //
11418 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11419 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11422 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src
11423 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11426 GIR_EraseFromParent, /*InsnID*/0,
11427 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11428 // GIR_Coverage, 5181,
11429 GIR_Done,
11430 // Label 640: @27565
11431 GIM_Try, /*On fail goto*//*Label 641*/ 27599, // Rule ID 5182 //
11432 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
11433 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11436 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src
11437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11440 GIR_EraseFromParent, /*InsnID*/0,
11441 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
11442 // GIR_Coverage, 5182,
11443 GIR_Done,
11444 // Label 641: @27599
11445 GIM_Try, /*On fail goto*//*Label 642*/ 27652, // Rule ID 5209 //
11446 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11447 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11450 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
11451 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11452 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11453 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
11455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11457 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11458 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11459 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11460 GIR_EraseFromParent, /*InsnID*/0,
11461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11462 // GIR_Coverage, 5209,
11463 GIR_Done,
11464 // Label 642: @27652
11465 GIM_Try, /*On fail goto*//*Label 643*/ 27705, // Rule ID 5210 //
11466 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11467 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11470 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
11471 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11472 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11473 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
11475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11477 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11478 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11479 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11480 GIR_EraseFromParent, /*InsnID*/0,
11481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11482 // GIR_Coverage, 5210,
11483 GIR_Done,
11484 // Label 643: @27705
11485 GIM_Try, /*On fail goto*//*Label 644*/ 27758, // Rule ID 5211 //
11486 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11487 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11490 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
11491 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11492 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11493 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11497 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11498 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11499 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11500 GIR_EraseFromParent, /*InsnID*/0,
11501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11502 // GIR_Coverage, 5211,
11503 GIR_Done,
11504 // Label 644: @27758
11505 GIM_Try, /*On fail goto*//*Label 645*/ 27811, // Rule ID 5212 //
11506 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11507 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11510 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
11511 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11512 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11513 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11514 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11517 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11518 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11519 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11520 GIR_EraseFromParent, /*InsnID*/0,
11521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11522 // GIR_Coverage, 5212,
11523 GIR_Done,
11524 // Label 645: @27811
11525 GIM_Try, /*On fail goto*//*Label 646*/ 27864, // Rule ID 5213 //
11526 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11527 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11530 // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
11531 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11532 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11533 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
11535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11537 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11538 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11539 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11540 GIR_EraseFromParent, /*InsnID*/0,
11541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11542 // GIR_Coverage, 5213,
11543 GIR_Done,
11544 // Label 646: @27864
11545 GIM_Try, /*On fail goto*//*Label 647*/ 27917, // Rule ID 5214 //
11546 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11547 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11550 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
11551 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11553 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
11555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11557 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11558 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11559 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11560 GIR_EraseFromParent, /*InsnID*/0,
11561 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11562 // GIR_Coverage, 5214,
11563 GIR_Done,
11564 // Label 647: @27917
11565 GIM_Try, /*On fail goto*//*Label 648*/ 27970, // Rule ID 5215 //
11566 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11567 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11570 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
11571 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11572 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11573 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_32,
11575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11577 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11578 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11579 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11580 GIR_EraseFromParent, /*InsnID*/0,
11581 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11582 // GIR_Coverage, 5215,
11583 GIR_Done,
11584 // Label 648: @27970
11585 GIM_Try, /*On fail goto*//*Label 649*/ 28023, // Rule ID 5216 //
11586 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11587 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11590 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
11591 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11592 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11593 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11597 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11598 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11599 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11600 GIR_EraseFromParent, /*InsnID*/0,
11601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11602 // GIR_Coverage, 5216,
11603 GIR_Done,
11604 // Label 649: @28023
11605 GIM_Try, /*On fail goto*//*Label 650*/ 28076, // Rule ID 5217 //
11606 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11607 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11610 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
11611 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11612 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11613 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
11615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11617 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11618 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11619 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11620 GIR_EraseFromParent, /*InsnID*/0,
11621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11622 // GIR_Coverage, 5217,
11623 GIR_Done,
11624 // Label 650: @28076
11625 GIM_Try, /*On fail goto*//*Label 651*/ 28129, // Rule ID 5218 //
11626 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
11627 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
11629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
11630 // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
11631 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11632 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
11633 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
11634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
11635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
11636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11637 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11638 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11639 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
11640 GIR_EraseFromParent, /*InsnID*/0,
11641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11642 // GIR_Coverage, 5218,
11643 GIR_Done,
11644 // Label 651: @28129
11645 GIM_Reject,
11646 // Label 462: @28130
11647 GIM_Try, /*On fail goto*//*Label 652*/ 28164, // Rule ID 2690 //
11648 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11649 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11652 // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src
11653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11656 GIR_EraseFromParent, /*InsnID*/0,
11657 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11658 // GIR_Coverage, 2690,
11659 GIR_Done,
11660 // Label 652: @28164
11661 GIM_Try, /*On fail goto*//*Label 653*/ 28198, // Rule ID 2691 //
11662 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11663 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11666 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src
11667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11670 GIR_EraseFromParent, /*InsnID*/0,
11671 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11672 // GIR_Coverage, 2691,
11673 GIR_Done,
11674 // Label 653: @28198
11675 GIM_Try, /*On fail goto*//*Label 654*/ 28232, // Rule ID 2692 //
11676 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11677 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11680 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src
11681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11684 GIR_EraseFromParent, /*InsnID*/0,
11685 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11686 // GIR_Coverage, 2692,
11687 GIR_Done,
11688 // Label 654: @28232
11689 GIM_Try, /*On fail goto*//*Label 655*/ 28266, // Rule ID 2693 //
11690 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11691 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11694 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src
11695 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11698 GIR_EraseFromParent, /*InsnID*/0,
11699 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11700 // GIR_Coverage, 2693,
11701 GIR_Done,
11702 // Label 655: @28266
11703 GIM_Try, /*On fail goto*//*Label 656*/ 28300, // Rule ID 2694 //
11704 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11705 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
11706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11708 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src
11709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11712 GIR_EraseFromParent, /*InsnID*/0,
11713 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11714 // GIR_Coverage, 2694,
11715 GIR_Done,
11716 // Label 656: @28300
11717 GIM_Try, /*On fail goto*//*Label 657*/ 28334, // Rule ID 2695 //
11718 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11719 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
11720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11722 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) => DPR:{ *:[v8i8] }:$src
11723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11726 GIR_EraseFromParent, /*InsnID*/0,
11727 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11728 // GIR_Coverage, 2695,
11729 GIR_Done,
11730 // Label 657: @28334
11731 GIM_Try, /*On fail goto*//*Label 658*/ 28368, // Rule ID 2696 //
11732 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11733 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
11734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11736 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src
11737 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11740 GIR_EraseFromParent, /*InsnID*/0,
11741 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::DPRRegClassID,
11742 // GIR_Coverage, 2696,
11743 GIR_Done,
11744 // Label 658: @28368
11745 GIM_Try, /*On fail goto*//*Label 659*/ 28407, // Rule ID 2782 //
11746 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11747 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11750 // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
11751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
11752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11754 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11755 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11756 GIR_EraseFromParent, /*InsnID*/0,
11757 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11758 // GIR_Coverage, 2782,
11759 GIR_Done,
11760 // Label 659: @28407
11761 GIM_Try, /*On fail goto*//*Label 660*/ 28446, // Rule ID 2783 //
11762 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11763 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
11764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11766 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
11767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
11768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11770 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11771 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11772 GIR_EraseFromParent, /*InsnID*/0,
11773 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11774 // GIR_Coverage, 2783,
11775 GIR_Done,
11776 // Label 660: @28446
11777 GIM_Try, /*On fail goto*//*Label 661*/ 28485, // Rule ID 2784 //
11778 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11779 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11782 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
11783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
11784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11786 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11787 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11788 GIR_EraseFromParent, /*InsnID*/0,
11789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11790 // GIR_Coverage, 2784,
11791 GIR_Done,
11792 // Label 661: @28485
11793 GIM_Try, /*On fail goto*//*Label 662*/ 28524, // Rule ID 2785 //
11794 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11795 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
11796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11798 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
11799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
11800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11802 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11803 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11804 GIR_EraseFromParent, /*InsnID*/0,
11805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11806 // GIR_Coverage, 2785,
11807 GIR_Done,
11808 // Label 662: @28524
11809 GIM_Try, /*On fail goto*//*Label 663*/ 28563, // Rule ID 2786 //
11810 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11811 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
11812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11814 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
11815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
11816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11818 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11819 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11820 GIR_EraseFromParent, /*InsnID*/0,
11821 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11822 // GIR_Coverage, 2786,
11823 GIR_Done,
11824 // Label 663: @28563
11825 GIM_Try, /*On fail goto*//*Label 664*/ 28602, // Rule ID 2787 //
11826 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11827 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
11828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11830 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4bf16] }:$src)
11831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
11832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11834 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11835 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11836 GIR_EraseFromParent, /*InsnID*/0,
11837 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11838 // GIR_Coverage, 2787,
11839 GIR_Done,
11840 // Label 664: @28602
11841 GIM_Try, /*On fail goto*//*Label 665*/ 28641, // Rule ID 2788 //
11842 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
11843 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
11844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
11846 // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
11847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
11848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11850 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11851 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
11852 GIR_EraseFromParent, /*InsnID*/0,
11853 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11854 // GIR_Coverage, 2788,
11855 GIR_Done,
11856 // Label 665: @28641
11857 GIM_Reject,
11858 // Label 463: @28642
11859 GIM_Try, /*On fail goto*//*Label 666*/ 28676, // Rule ID 2647 //
11860 GIM_CheckFeatures, GIFBS_HasNEON,
11861 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11864 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src
11865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11868 GIR_EraseFromParent, /*InsnID*/0,
11869 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11870 // GIR_Coverage, 2647,
11871 GIR_Done,
11872 // Label 666: @28676
11873 GIM_Try, /*On fail goto*//*Label 667*/ 28710, // Rule ID 2648 //
11874 GIM_CheckFeatures, GIFBS_HasNEON,
11875 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11878 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src
11879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11882 GIR_EraseFromParent, /*InsnID*/0,
11883 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11884 // GIR_Coverage, 2648,
11885 GIR_Done,
11886 // Label 667: @28710
11887 GIM_Try, /*On fail goto*//*Label 668*/ 28744, // Rule ID 2649 //
11888 GIM_CheckFeatures, GIFBS_HasNEON,
11889 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11892 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v8i16] }:$src
11893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11896 GIR_EraseFromParent, /*InsnID*/0,
11897 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11898 // GIR_Coverage, 2649,
11899 GIR_Done,
11900 // Label 668: @28744
11901 GIM_Try, /*On fail goto*//*Label 669*/ 28778, // Rule ID 2650 //
11902 GIM_CheckFeatures, GIFBS_HasNEON,
11903 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
11904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11906 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8bf16] }:$src
11907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11910 GIR_EraseFromParent, /*InsnID*/0,
11911 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11912 // GIR_Coverage, 2650,
11913 GIR_Done,
11914 // Label 669: @28778
11915 GIM_Try, /*On fail goto*//*Label 670*/ 28812, // Rule ID 2721 //
11916 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11917 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11920 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src
11921 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11924 GIR_EraseFromParent, /*InsnID*/0,
11925 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11926 // GIR_Coverage, 2721,
11927 GIR_Done,
11928 // Label 670: @28812
11929 GIM_Try, /*On fail goto*//*Label 671*/ 28846, // Rule ID 2722 //
11930 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11931 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11934 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src
11935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11938 GIR_EraseFromParent, /*InsnID*/0,
11939 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11940 // GIR_Coverage, 2722,
11941 GIR_Done,
11942 // Label 671: @28846
11943 GIM_Try, /*On fail goto*//*Label 672*/ 28880, // Rule ID 2723 //
11944 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11945 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11948 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src
11949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11952 GIR_EraseFromParent, /*InsnID*/0,
11953 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11954 // GIR_Coverage, 2723,
11955 GIR_Done,
11956 // Label 672: @28880
11957 GIM_Try, /*On fail goto*//*Label 673*/ 28914, // Rule ID 2724 //
11958 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11959 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
11960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11962 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src
11963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11966 GIR_EraseFromParent, /*InsnID*/0,
11967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11968 // GIR_Coverage, 2724,
11969 GIR_Done,
11970 // Label 673: @28914
11971 GIM_Try, /*On fail goto*//*Label 674*/ 28948, // Rule ID 2725 //
11972 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11973 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
11974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11976 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src
11977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11980 GIR_EraseFromParent, /*InsnID*/0,
11981 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11982 // GIR_Coverage, 2725,
11983 GIR_Done,
11984 // Label 674: @28948
11985 GIM_Try, /*On fail goto*//*Label 675*/ 28982, // Rule ID 2726 //
11986 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
11987 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
11988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
11990 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8bf16] }:$src
11991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
11993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
11994 GIR_EraseFromParent, /*InsnID*/0,
11995 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
11996 // GIR_Coverage, 2726,
11997 GIR_Done,
11998 // Label 675: @28982
11999 GIM_Try, /*On fail goto*//*Label 676*/ 29016, // Rule ID 2727 //
12000 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12001 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12004 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8bf16] }:$src
12005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12008 GIR_EraseFromParent, /*InsnID*/0,
12009 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12010 // GIR_Coverage, 2727,
12011 GIR_Done,
12012 // Label 676: @29016
12013 GIM_Try, /*On fail goto*//*Label 677*/ 29050, // Rule ID 2728 //
12014 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12015 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12018 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8bf16] }:$src
12019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12022 GIR_EraseFromParent, /*InsnID*/0,
12023 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12024 // GIR_Coverage, 2728,
12025 GIR_Done,
12026 // Label 677: @29050
12027 GIM_Try, /*On fail goto*//*Label 678*/ 29084, // Rule ID 2729 //
12028 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12029 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12032 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8bf16] }:$src
12033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12036 GIR_EraseFromParent, /*InsnID*/0,
12037 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12038 // GIR_Coverage, 2729,
12039 GIR_Done,
12040 // Label 678: @29084
12041 GIM_Try, /*On fail goto*//*Label 679*/ 29118, // Rule ID 2730 //
12042 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12043 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12046 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8bf16] }:$src
12047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12050 GIR_EraseFromParent, /*InsnID*/0,
12051 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12052 // GIR_Coverage, 2730,
12053 GIR_Done,
12054 // Label 679: @29118
12055 GIM_Try, /*On fail goto*//*Label 680*/ 29152, // Rule ID 2731 //
12056 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12057 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12060 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src
12061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12064 GIR_EraseFromParent, /*InsnID*/0,
12065 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12066 // GIR_Coverage, 2731,
12067 GIR_Done,
12068 // Label 680: @29152
12069 GIM_Try, /*On fail goto*//*Label 681*/ 29186, // Rule ID 2732 //
12070 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12071 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12074 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src
12075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12078 GIR_EraseFromParent, /*InsnID*/0,
12079 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12080 // GIR_Coverage, 2732,
12081 GIR_Done,
12082 // Label 681: @29186
12083 GIM_Try, /*On fail goto*//*Label 682*/ 29220, // Rule ID 2733 //
12084 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12085 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12088 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src
12089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12092 GIR_EraseFromParent, /*InsnID*/0,
12093 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12094 // GIR_Coverage, 2733,
12095 GIR_Done,
12096 // Label 682: @29220
12097 GIM_Try, /*On fail goto*//*Label 683*/ 29254, // Rule ID 2734 //
12098 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12099 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12102 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src
12103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12106 GIR_EraseFromParent, /*InsnID*/0,
12107 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12108 // GIR_Coverage, 2734,
12109 GIR_Done,
12110 // Label 683: @29254
12111 GIM_Try, /*On fail goto*//*Label 684*/ 29288, // Rule ID 2735 //
12112 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12113 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12116 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src
12117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12120 GIR_EraseFromParent, /*InsnID*/0,
12121 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12122 // GIR_Coverage, 2735,
12123 GIR_Done,
12124 // Label 684: @29288
12125 GIM_Try, /*On fail goto*//*Label 685*/ 29327, // Rule ID 2813 //
12126 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12127 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12130 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
12131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12134 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12135 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12136 GIR_EraseFromParent, /*InsnID*/0,
12137 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12138 // GIR_Coverage, 2813,
12139 GIR_Done,
12140 // Label 685: @29327
12141 GIM_Try, /*On fail goto*//*Label 686*/ 29366, // Rule ID 2814 //
12142 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12146 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
12147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12150 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12151 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12152 GIR_EraseFromParent, /*InsnID*/0,
12153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12154 // GIR_Coverage, 2814,
12155 GIR_Done,
12156 // Label 686: @29366
12157 GIM_Try, /*On fail goto*//*Label 687*/ 29405, // Rule ID 2815 //
12158 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12159 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12162 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
12163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12166 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12167 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12168 GIR_EraseFromParent, /*InsnID*/0,
12169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12170 // GIR_Coverage, 2815,
12171 GIR_Done,
12172 // Label 687: @29405
12173 GIM_Try, /*On fail goto*//*Label 688*/ 29444, // Rule ID 2816 //
12174 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12175 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12178 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
12179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12182 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12183 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12184 GIR_EraseFromParent, /*InsnID*/0,
12185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12186 // GIR_Coverage, 2816,
12187 GIR_Done,
12188 // Label 688: @29444
12189 GIM_Try, /*On fail goto*//*Label 689*/ 29483, // Rule ID 2817 //
12190 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12194 // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
12195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12198 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12199 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12200 GIR_EraseFromParent, /*InsnID*/0,
12201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12202 // GIR_Coverage, 2817,
12203 GIR_Done,
12204 // Label 689: @29483
12205 GIM_Try, /*On fail goto*//*Label 690*/ 29522, // Rule ID 2818 //
12206 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12207 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12210 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2f64] }:$src)
12211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12214 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12215 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12216 GIR_EraseFromParent, /*InsnID*/0,
12217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12218 // GIR_Coverage, 2818,
12219 GIR_Done,
12220 // Label 690: @29522
12221 GIM_Try, /*On fail goto*//*Label 691*/ 29561, // Rule ID 2819 //
12222 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12223 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12226 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8bf16] } QPR:{ *:[v2i64] }:$src)
12227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12230 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12231 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12232 GIR_EraseFromParent, /*InsnID*/0,
12233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12234 // GIR_Coverage, 2819,
12235 GIR_Done,
12236 // Label 691: @29561
12237 GIM_Try, /*On fail goto*//*Label 692*/ 29600, // Rule ID 2820 //
12238 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12239 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12242 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4f32] }:$src)
12243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12246 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12247 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12248 GIR_EraseFromParent, /*InsnID*/0,
12249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12250 // GIR_Coverage, 2820,
12251 GIR_Done,
12252 // Label 692: @29600
12253 GIM_Try, /*On fail goto*//*Label 693*/ 29639, // Rule ID 2821 //
12254 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12255 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12258 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8bf16] } QPR:{ *:[v4i32] }:$src)
12259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12262 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12263 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12264 GIR_EraseFromParent, /*InsnID*/0,
12265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12266 // GIR_Coverage, 2821,
12267 GIR_Done,
12268 // Label 693: @29639
12269 GIM_Try, /*On fail goto*//*Label 694*/ 29678, // Rule ID 2822 //
12270 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12271 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12274 // (bitconvert:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8bf16] } QPR:{ *:[v16i8] }:$src)
12275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12278 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12279 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12280 GIR_EraseFromParent, /*InsnID*/0,
12281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12282 // GIR_Coverage, 2822,
12283 GIR_Done,
12284 // Label 694: @29678
12285 GIM_Try, /*On fail goto*//*Label 695*/ 29717, // Rule ID 2823 //
12286 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12287 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12290 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
12291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12294 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12295 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12296 GIR_EraseFromParent, /*InsnID*/0,
12297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12298 // GIR_Coverage, 2823,
12299 GIR_Done,
12300 // Label 695: @29717
12301 GIM_Try, /*On fail goto*//*Label 696*/ 29756, // Rule ID 2824 //
12302 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12303 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12306 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
12307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
12308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12310 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12311 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12312 GIR_EraseFromParent, /*InsnID*/0,
12313 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12314 // GIR_Coverage, 2824,
12315 GIR_Done,
12316 // Label 696: @29756
12317 GIM_Try, /*On fail goto*//*Label 697*/ 29795, // Rule ID 2825 //
12318 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12319 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12322 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
12323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12326 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12327 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12328 GIR_EraseFromParent, /*InsnID*/0,
12329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12330 // GIR_Coverage, 2825,
12331 GIR_Done,
12332 // Label 697: @29795
12333 GIM_Try, /*On fail goto*//*Label 698*/ 29834, // Rule ID 2826 //
12334 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12335 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12338 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
12339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
12340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12342 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12343 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12344 GIR_EraseFromParent, /*InsnID*/0,
12345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12346 // GIR_Coverage, 2826,
12347 GIR_Done,
12348 // Label 698: @29834
12349 GIM_Try, /*On fail goto*//*Label 699*/ 29873, // Rule ID 2827 //
12350 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12351 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12354 // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
12355 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12358 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12359 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12360 GIR_EraseFromParent, /*InsnID*/0,
12361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12362 // GIR_Coverage, 2827,
12363 GIR_Done,
12364 // Label 699: @29873
12365 GIM_Try, /*On fail goto*//*Label 700*/ 29907, // Rule ID 5161 //
12366 GIM_CheckFeatures, GIFBS_HasMVEInt,
12367 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12370 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src
12371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12374 GIR_EraseFromParent, /*InsnID*/0,
12375 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12376 // GIR_Coverage, 5161,
12377 GIR_Done,
12378 // Label 700: @29907
12379 GIM_Try, /*On fail goto*//*Label 701*/ 29941, // Rule ID 5162 //
12380 GIM_CheckFeatures, GIFBS_HasMVEInt,
12381 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12384 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src
12385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12388 GIR_EraseFromParent, /*InsnID*/0,
12389 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12390 // GIR_Coverage, 5162,
12391 GIR_Done,
12392 // Label 701: @29941
12393 GIM_Try, /*On fail goto*//*Label 702*/ 29975, // Rule ID 5183 //
12394 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12395 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12398 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src
12399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12402 GIR_EraseFromParent, /*InsnID*/0,
12403 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12404 // GIR_Coverage, 5183,
12405 GIR_Done,
12406 // Label 702: @29975
12407 GIM_Try, /*On fail goto*//*Label 703*/ 30009, // Rule ID 5184 //
12408 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12409 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12412 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src
12413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12416 GIR_EraseFromParent, /*InsnID*/0,
12417 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12418 // GIR_Coverage, 5184,
12419 GIR_Done,
12420 // Label 703: @30009
12421 GIM_Try, /*On fail goto*//*Label 704*/ 30043, // Rule ID 5185 //
12422 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12423 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12426 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src
12427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12430 GIR_EraseFromParent, /*InsnID*/0,
12431 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12432 // GIR_Coverage, 5185,
12433 GIR_Done,
12434 // Label 704: @30043
12435 GIM_Try, /*On fail goto*//*Label 705*/ 30077, // Rule ID 5186 //
12436 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12437 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12440 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src
12441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12444 GIR_EraseFromParent, /*InsnID*/0,
12445 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12446 // GIR_Coverage, 5186,
12447 GIR_Done,
12448 // Label 705: @30077
12449 GIM_Try, /*On fail goto*//*Label 706*/ 30111, // Rule ID 5187 //
12450 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12451 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12454 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src
12455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12458 GIR_EraseFromParent, /*InsnID*/0,
12459 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12460 // GIR_Coverage, 5187,
12461 GIR_Done,
12462 // Label 706: @30111
12463 GIM_Try, /*On fail goto*//*Label 707*/ 30145, // Rule ID 5188 //
12464 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12465 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12468 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src
12469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12472 GIR_EraseFromParent, /*InsnID*/0,
12473 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12474 // GIR_Coverage, 5188,
12475 GIR_Done,
12476 // Label 707: @30145
12477 GIM_Try, /*On fail goto*//*Label 708*/ 30179, // Rule ID 5189 //
12478 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12479 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12482 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src
12483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12486 GIR_EraseFromParent, /*InsnID*/0,
12487 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12488 // GIR_Coverage, 5189,
12489 GIR_Done,
12490 // Label 708: @30179
12491 GIM_Try, /*On fail goto*//*Label 709*/ 30213, // Rule ID 5190 //
12492 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12493 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12496 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src
12497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12500 GIR_EraseFromParent, /*InsnID*/0,
12501 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12502 // GIR_Coverage, 5190,
12503 GIR_Done,
12504 // Label 709: @30213
12505 GIM_Try, /*On fail goto*//*Label 710*/ 30247, // Rule ID 5191 //
12506 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12507 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12510 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src
12511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12514 GIR_EraseFromParent, /*InsnID*/0,
12515 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12516 // GIR_Coverage, 5191,
12517 GIR_Done,
12518 // Label 710: @30247
12519 GIM_Try, /*On fail goto*//*Label 711*/ 30281, // Rule ID 5192 //
12520 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12521 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12524 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src
12525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12528 GIR_EraseFromParent, /*InsnID*/0,
12529 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12530 // GIR_Coverage, 5192,
12531 GIR_Done,
12532 // Label 711: @30281
12533 GIM_Try, /*On fail goto*//*Label 712*/ 30334, // Rule ID 5219 //
12534 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12535 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12538 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
12539 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12540 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12541 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12542 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
12543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12545 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12546 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12547 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12548 GIR_EraseFromParent, /*InsnID*/0,
12549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12550 // GIR_Coverage, 5219,
12551 GIR_Done,
12552 // Label 712: @30334
12553 GIM_Try, /*On fail goto*//*Label 713*/ 30387, // Rule ID 5220 //
12554 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12555 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12558 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
12559 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12560 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12561 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
12563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12565 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12566 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12567 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12568 GIR_EraseFromParent, /*InsnID*/0,
12569 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12570 // GIR_Coverage, 5220,
12571 GIR_Done,
12572 // Label 713: @30387
12573 GIM_Try, /*On fail goto*//*Label 714*/ 30440, // Rule ID 5221 //
12574 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12575 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12578 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
12579 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12580 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12581 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12585 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12586 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12587 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12588 GIR_EraseFromParent, /*InsnID*/0,
12589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12590 // GIR_Coverage, 5221,
12591 GIR_Done,
12592 // Label 714: @30440
12593 GIM_Try, /*On fail goto*//*Label 715*/ 30493, // Rule ID 5222 //
12594 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12595 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12598 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
12599 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12600 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12601 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12605 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12606 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12607 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12608 GIR_EraseFromParent, /*InsnID*/0,
12609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12610 // GIR_Coverage, 5222,
12611 GIR_Done,
12612 // Label 715: @30493
12613 GIM_Try, /*On fail goto*//*Label 716*/ 30546, // Rule ID 5223 //
12614 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12615 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12618 // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
12619 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12620 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12621 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
12623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12625 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12626 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12627 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12628 GIR_EraseFromParent, /*InsnID*/0,
12629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12630 // GIR_Coverage, 5223,
12631 GIR_Done,
12632 // Label 716: @30546
12633 GIM_Try, /*On fail goto*//*Label 717*/ 30599, // Rule ID 5224 //
12634 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12635 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12638 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
12639 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12640 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12641 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
12643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12645 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12646 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12647 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12648 GIR_EraseFromParent, /*InsnID*/0,
12649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12650 // GIR_Coverage, 5224,
12651 GIR_Done,
12652 // Label 717: @30599
12653 GIM_Try, /*On fail goto*//*Label 718*/ 30652, // Rule ID 5225 //
12654 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12655 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12658 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
12659 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12660 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12661 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_16,
12663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12665 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12666 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12667 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12668 GIR_EraseFromParent, /*InsnID*/0,
12669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12670 // GIR_Coverage, 5225,
12671 GIR_Done,
12672 // Label 718: @30652
12673 GIM_Try, /*On fail goto*//*Label 719*/ 30705, // Rule ID 5226 //
12674 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12675 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12678 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
12679 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12680 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12681 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12685 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12686 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12687 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12688 GIR_EraseFromParent, /*InsnID*/0,
12689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12690 // GIR_Coverage, 5226,
12691 GIR_Done,
12692 // Label 719: @30705
12693 GIM_Try, /*On fail goto*//*Label 720*/ 30758, // Rule ID 5227 //
12694 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12695 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12698 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
12699 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_16,
12703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12705 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12706 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12707 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12708 GIR_EraseFromParent, /*InsnID*/0,
12709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12710 // GIR_Coverage, 5227,
12711 GIR_Done,
12712 // Label 720: @30758
12713 GIM_Try, /*On fail goto*//*Label 721*/ 30811, // Rule ID 5228 //
12714 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
12715 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
12716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12718 // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
12719 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12720 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
12721 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
12722 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
12723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
12724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12725 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
12726 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12727 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
12728 GIR_EraseFromParent, /*InsnID*/0,
12729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12730 // GIR_Coverage, 5228,
12731 GIR_Done,
12732 // Label 721: @30811
12733 GIM_Reject,
12734 // Label 464: @30812
12735 GIM_Try, /*On fail goto*//*Label 722*/ 30846, // Rule ID 2736 //
12736 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12740 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src
12741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12744 GIR_EraseFromParent, /*InsnID*/0,
12745 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12746 // GIR_Coverage, 2736,
12747 GIR_Done,
12748 // Label 722: @30846
12749 GIM_Try, /*On fail goto*//*Label 723*/ 30880, // Rule ID 2737 //
12750 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12751 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12754 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src
12755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12758 GIR_EraseFromParent, /*InsnID*/0,
12759 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12760 // GIR_Coverage, 2737,
12761 GIR_Done,
12762 // Label 723: @30880
12763 GIM_Try, /*On fail goto*//*Label 724*/ 30914, // Rule ID 2738 //
12764 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12765 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12768 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src
12769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12772 GIR_EraseFromParent, /*InsnID*/0,
12773 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12774 // GIR_Coverage, 2738,
12775 GIR_Done,
12776 // Label 724: @30914
12777 GIM_Try, /*On fail goto*//*Label 725*/ 30948, // Rule ID 2739 //
12778 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12779 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12782 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src
12783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12786 GIR_EraseFromParent, /*InsnID*/0,
12787 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12788 // GIR_Coverage, 2739,
12789 GIR_Done,
12790 // Label 725: @30948
12791 GIM_Try, /*On fail goto*//*Label 726*/ 30982, // Rule ID 2740 //
12792 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12793 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12796 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src
12797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12800 GIR_EraseFromParent, /*InsnID*/0,
12801 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12802 // GIR_Coverage, 2740,
12803 GIR_Done,
12804 // Label 726: @30982
12805 GIM_Try, /*On fail goto*//*Label 727*/ 31016, // Rule ID 2741 //
12806 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12807 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12810 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) => QPR:{ *:[v16i8] }:$src
12811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12814 GIR_EraseFromParent, /*InsnID*/0,
12815 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12816 // GIR_Coverage, 2741,
12817 GIR_Done,
12818 // Label 727: @31016
12819 GIM_Try, /*On fail goto*//*Label 728*/ 31050, // Rule ID 2742 //
12820 GIM_CheckFeatures, GIFBS_HasNEON_IsLE,
12821 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12824 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src
12825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12828 GIR_EraseFromParent, /*InsnID*/0,
12829 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::QPRRegClassID,
12830 // GIR_Coverage, 2742,
12831 GIR_Done,
12832 // Label 728: @31050
12833 GIM_Try, /*On fail goto*//*Label 729*/ 31089, // Rule ID 2828 //
12834 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12835 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12838 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
12839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
12840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12842 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12843 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12844 GIR_EraseFromParent, /*InsnID*/0,
12845 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12846 // GIR_Coverage, 2828,
12847 GIR_Done,
12848 // Label 729: @31089
12849 GIM_Try, /*On fail goto*//*Label 730*/ 31128, // Rule ID 2829 //
12850 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12851 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12854 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
12855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
12856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12858 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12859 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12860 GIR_EraseFromParent, /*InsnID*/0,
12861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12862 // GIR_Coverage, 2829,
12863 GIR_Done,
12864 // Label 730: @31128
12865 GIM_Try, /*On fail goto*//*Label 731*/ 31167, // Rule ID 2830 //
12866 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12870 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
12871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
12872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12874 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12875 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12876 GIR_EraseFromParent, /*InsnID*/0,
12877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12878 // GIR_Coverage, 2830,
12879 GIR_Done,
12880 // Label 731: @31167
12881 GIM_Try, /*On fail goto*//*Label 732*/ 31206, // Rule ID 2831 //
12882 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12883 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12886 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
12887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
12888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12890 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12891 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12892 GIR_EraseFromParent, /*InsnID*/0,
12893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12894 // GIR_Coverage, 2831,
12895 GIR_Done,
12896 // Label 732: @31206
12897 GIM_Try, /*On fail goto*//*Label 733*/ 31245, // Rule ID 2832 //
12898 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12899 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12902 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
12903 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12906 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12907 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12908 GIR_EraseFromParent, /*InsnID*/0,
12909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12910 // GIR_Coverage, 2832,
12911 GIR_Done,
12912 // Label 733: @31245
12913 GIM_Try, /*On fail goto*//*Label 734*/ 31284, // Rule ID 2833 //
12914 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12915 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12918 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8bf16] }:$src)
12919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12922 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12923 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12924 GIR_EraseFromParent, /*InsnID*/0,
12925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12926 // GIR_Coverage, 2833,
12927 GIR_Done,
12928 // Label 734: @31284
12929 GIM_Try, /*On fail goto*//*Label 735*/ 31323, // Rule ID 2834 //
12930 GIM_CheckFeatures, GIFBS_HasNEON_IsBE,
12931 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
12932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
12933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
12934 // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
12935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
12936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
12937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12938 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12939 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
12940 GIR_EraseFromParent, /*InsnID*/0,
12941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12942 // GIR_Coverage, 2834,
12943 GIR_Done,
12944 // Label 735: @31323
12945 GIM_Try, /*On fail goto*//*Label 736*/ 31357, // Rule ID 5193 //
12946 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12950 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src
12951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12954 GIR_EraseFromParent, /*InsnID*/0,
12955 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12956 // GIR_Coverage, 5193,
12957 GIR_Done,
12958 // Label 736: @31357
12959 GIM_Try, /*On fail goto*//*Label 737*/ 31391, // Rule ID 5194 //
12960 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12961 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
12962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12964 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src
12965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12968 GIR_EraseFromParent, /*InsnID*/0,
12969 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12970 // GIR_Coverage, 5194,
12971 GIR_Done,
12972 // Label 737: @31391
12973 GIM_Try, /*On fail goto*//*Label 738*/ 31425, // Rule ID 5195 //
12974 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12975 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12978 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src
12979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12982 GIR_EraseFromParent, /*InsnID*/0,
12983 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12984 // GIR_Coverage, 5195,
12985 GIR_Done,
12986 // Label 738: @31425
12987 GIM_Try, /*On fail goto*//*Label 739*/ 31459, // Rule ID 5196 //
12988 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
12989 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
12990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
12991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
12992 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src
12993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
12995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
12996 GIR_EraseFromParent, /*InsnID*/0,
12997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
12998 // GIR_Coverage, 5196,
12999 GIR_Done,
13000 // Label 739: @31459
13001 GIM_Try, /*On fail goto*//*Label 740*/ 31493, // Rule ID 5197 //
13002 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13003 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13006 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src
13007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13010 GIR_EraseFromParent, /*InsnID*/0,
13011 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13012 // GIR_Coverage, 5197,
13013 GIR_Done,
13014 // Label 740: @31493
13015 GIM_Try, /*On fail goto*//*Label 741*/ 31527, // Rule ID 5198 //
13016 GIM_CheckFeatures, GIFBS_HasMVEInt_IsLE,
13017 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13020 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src
13021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
13023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13024 GIR_EraseFromParent, /*InsnID*/0,
13025 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::MQPRRegClassID,
13026 // GIR_Coverage, 5198,
13027 GIR_Done,
13028 // Label 741: @31527
13029 GIM_Try, /*On fail goto*//*Label 742*/ 31580, // Rule ID 5229 //
13030 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13031 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13034 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
13035 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13036 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13037 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
13039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13041 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13042 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13043 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13044 GIR_EraseFromParent, /*InsnID*/0,
13045 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13046 // GIR_Coverage, 5229,
13047 GIR_Done,
13048 // Label 742: @31580
13049 GIM_Try, /*On fail goto*//*Label 743*/ 31633, // Rule ID 5230 //
13050 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13051 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
13052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13054 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
13055 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13056 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13057 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV64_8,
13059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13061 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13062 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13063 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13064 GIR_EraseFromParent, /*InsnID*/0,
13065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13066 // GIR_Coverage, 5230,
13067 GIR_Done,
13068 // Label 743: @31633
13069 GIM_Try, /*On fail goto*//*Label 744*/ 31686, // Rule ID 5231 //
13070 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13071 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13074 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
13075 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13076 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13077 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
13079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13081 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13082 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13083 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13084 GIR_EraseFromParent, /*InsnID*/0,
13085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13086 // GIR_Coverage, 5231,
13087 GIR_Done,
13088 // Label 744: @31686
13089 GIM_Try, /*On fail goto*//*Label 745*/ 31739, // Rule ID 5232 //
13090 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13091 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13094 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
13095 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13096 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13097 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
13099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13101 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13102 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13103 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13104 GIR_EraseFromParent, /*InsnID*/0,
13105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13106 // GIR_Coverage, 5232,
13107 GIR_Done,
13108 // Label 745: @31739
13109 GIM_Try, /*On fail goto*//*Label 746*/ 31792, // Rule ID 5233 //
13110 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13111 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13114 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
13115 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13116 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13117 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
13119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13121 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13122 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13123 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13124 GIR_EraseFromParent, /*InsnID*/0,
13125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13126 // GIR_Coverage, 5233,
13127 GIR_Done,
13128 // Label 746: @31792
13129 GIM_Try, /*On fail goto*//*Label 747*/ 31845, // Rule ID 5234 //
13130 GIM_CheckFeatures, GIFBS_HasMVEInt_IsBE,
13131 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13134 // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
13135 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13137 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
13139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
13141 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13142 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13143 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13144 GIR_EraseFromParent, /*InsnID*/0,
13145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13146 // GIR_Coverage, 5234,
13147 GIR_Done,
13148 // Label 747: @31845
13149 GIM_Reject,
13150 // Label 465: @31846
13151 GIM_Reject,
13152 // Label 10: @31847
13153 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 753*/ 32093,
13154 /*GILLT_s16*//*Label 748*/ 31865,
13155 /*GILLT_s32*//*Label 749*/ 31905,
13156 /*GILLT_s64*//*Label 750*/ 31945, 0, 0, 0, 0,
13157 /*GILLT_v4s32*//*Label 751*/ 31985, 0, 0, 0,
13158 /*GILLT_v8s16*//*Label 752*/ 32039,
13159 // Label 748: @31865
13160 GIM_Try, /*On fail goto*//*Label 754*/ 31904, // Rule ID 679 //
13161 GIM_CheckFeatures, GIFBS_HasFullFP16,
13162 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
13163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
13164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
13165 // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZH,
13167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
13169 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13170 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13171 GIR_EraseFromParent, /*InsnID*/0,
13172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13173 // GIR_Coverage, 679,
13174 GIR_Done,
13175 // Label 754: @31904
13176 GIM_Reject,
13177 // Label 749: @31905
13178 GIM_Try, /*On fail goto*//*Label 755*/ 31944, // Rule ID 680 //
13179 GIM_CheckFeatures, GIFBS_HasFPARMv8,
13180 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
13183 // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZS,
13185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
13187 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13188 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13189 GIR_EraseFromParent, /*InsnID*/0,
13190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13191 // GIR_Coverage, 680,
13192 GIR_Done,
13193 // Label 755: @31944
13194 GIM_Reject,
13195 // Label 750: @31945
13196 GIM_Try, /*On fail goto*//*Label 756*/ 31984, // Rule ID 681 //
13197 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
13198 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
13201 // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13202 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZD,
13203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
13204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
13205 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13206 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13207 GIR_EraseFromParent, /*InsnID*/0,
13208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13209 // GIR_Coverage, 681,
13210 GIR_Done,
13211 // Label 756: @31984
13212 GIM_Reject,
13213 // Label 751: @31985
13214 GIM_Try, /*On fail goto*//*Label 757*/ 32038, // Rule ID 3936 //
13215 GIM_CheckFeatures, GIFBS_HasMVEFloat,
13216 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13219 // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13220 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13221 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13222 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32Z,
13224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13226 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13227 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13228 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13229 GIR_EraseFromParent, /*InsnID*/0,
13230 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13231 // GIR_Coverage, 3936,
13232 GIR_Done,
13233 // Label 757: @32038
13234 GIM_Reject,
13235 // Label 752: @32039
13236 GIM_Try, /*On fail goto*//*Label 758*/ 32092, // Rule ID 3924 //
13237 GIM_CheckFeatures, GIFBS_HasMVEFloat,
13238 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13241 // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13244 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16Z,
13246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13248 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13249 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13250 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13251 GIR_EraseFromParent, /*InsnID*/0,
13252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13253 // GIR_Coverage, 3924,
13254 GIR_Done,
13255 // Label 758: @32092
13256 GIM_Reject,
13257 // Label 753: @32093
13258 GIM_Reject,
13259 // Label 11: @32094
13260 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 764*/ 32292,
13261 /*GILLT_s16*//*Label 759*/ 32112,
13262 /*GILLT_s32*//*Label 760*/ 32136,
13263 /*GILLT_s64*//*Label 761*/ 32160, 0, 0, 0, 0,
13264 /*GILLT_v4s32*//*Label 762*/ 32184, 0, 0, 0,
13265 /*GILLT_v8s16*//*Label 763*/ 32238,
13266 // Label 759: @32112
13267 GIM_Try, /*On fail goto*//*Label 765*/ 32135, // Rule ID 688 //
13268 GIM_CheckFeatures, GIFBS_HasFullFP16,
13269 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
13270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
13271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
13272 // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13273 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAH,
13274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13275 // GIR_Coverage, 688,
13276 GIR_Done,
13277 // Label 765: @32135
13278 GIM_Reject,
13279 // Label 760: @32136
13280 GIM_Try, /*On fail goto*//*Label 766*/ 32159, // Rule ID 689 //
13281 GIM_CheckFeatures, GIFBS_HasFPARMv8,
13282 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
13283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
13285 // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13286 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAS,
13287 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13288 // GIR_Coverage, 689,
13289 GIR_Done,
13290 // Label 766: @32159
13291 GIM_Reject,
13292 // Label 761: @32160
13293 GIM_Try, /*On fail goto*//*Label 767*/ 32183, // Rule ID 690 //
13294 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
13295 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
13296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
13298 // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13299 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTAD,
13300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13301 // GIR_Coverage, 690,
13302 GIR_Done,
13303 // Label 767: @32183
13304 GIM_Reject,
13305 // Label 762: @32184
13306 GIM_Try, /*On fail goto*//*Label 768*/ 32237, // Rule ID 3934 //
13307 GIM_CheckFeatures, GIFBS_HasMVEFloat,
13308 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
13309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13311 // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13312 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13313 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13314 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13315 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32A,
13316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13318 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13319 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13320 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13321 GIR_EraseFromParent, /*InsnID*/0,
13322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13323 // GIR_Coverage, 3934,
13324 GIR_Done,
13325 // Label 768: @32237
13326 GIM_Reject,
13327 // Label 763: @32238
13328 GIM_Try, /*On fail goto*//*Label 769*/ 32291, // Rule ID 3922 //
13329 GIM_CheckFeatures, GIFBS_HasMVEFloat,
13330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
13331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
13332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
13333 // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13334 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13335 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
13336 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
13337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16A,
13338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
13339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
13340 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13341 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13342 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
13343 GIR_EraseFromParent, /*InsnID*/0,
13344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13345 // GIR_Coverage, 3922,
13346 GIR_Done,
13347 // Label 769: @32291
13348 GIM_Reject,
13349 // Label 764: @32292
13350 GIM_Reject,
13351 // Label 12: @32293
13352 GIM_Try, /*On fail goto*//*Label 770*/ 38420,
13353 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
13354 GIM_Try, /*On fail goto*//*Label 771*/ 32348, // Rule ID 1870 //
13355 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
13356 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
13357 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13358 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
13360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
13361 // (intrinsic_wo_chain:{ *:[i32] } 2343:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
13362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
13363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
13365 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13366 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13367 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13368 GIR_EraseFromParent, /*InsnID*/0,
13369 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13370 // GIR_Coverage, 1870,
13371 GIR_Done,
13372 // Label 771: @32348
13373 GIM_Try, /*On fail goto*//*Label 772*/ 32398, // Rule ID 2103 //
13374 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13375 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
13376 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13377 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13380 // (intrinsic_wo_chain:{ *:[i32] } 2343:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
13381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
13382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
13384 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
13385 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13386 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13387 GIR_EraseFromParent, /*InsnID*/0,
13388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13389 // GIR_Coverage, 2103,
13390 GIR_Done,
13391 // Label 772: @32398
13392 GIM_Try, /*On fail goto*//*Label 773*/ 32438, // Rule ID 691 //
13393 GIM_CheckFeatures, GIFBS_HasFullFP16,
13394 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13395 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
13396 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
13397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
13398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
13399 // (intrinsic_wo_chain:{ *:[f16] } 2229:{ *:[iPTR] }, HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNH,
13401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
13403 GIR_EraseFromParent, /*InsnID*/0,
13404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13405 // GIR_Coverage, 691,
13406 GIR_Done,
13407 // Label 773: @32438
13408 GIM_Try, /*On fail goto*//*Label 774*/ 32478, // Rule ID 692 //
13409 GIM_CheckFeatures, GIFBS_HasFPARMv8,
13410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13412 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
13415 // (intrinsic_wo_chain:{ *:[f32] } 2229:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13416 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNS,
13417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
13419 GIR_EraseFromParent, /*InsnID*/0,
13420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13421 // GIR_Coverage, 692,
13422 GIR_Done,
13423 // Label 774: @32478
13424 GIM_Try, /*On fail goto*//*Label 775*/ 32518, // Rule ID 693 //
13425 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
13426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
13427 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
13428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13431 // (intrinsic_wo_chain:{ *:[f64] } 2229:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTND,
13433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
13434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
13435 GIR_EraseFromParent, /*InsnID*/0,
13436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13437 // GIR_Coverage, 693,
13438 GIR_Done,
13439 // Label 775: @32518
13440 GIM_Try, /*On fail goto*//*Label 776*/ 32565, // Rule ID 707 //
13441 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
13442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
13443 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13447 // (intrinsic_wo_chain:{ *:[f32] } 2344:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
13448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRD,
13449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
13451 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13452 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13453 GIR_EraseFromParent, /*InsnID*/0,
13454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13455 // GIR_Coverage, 707,
13456 GIR_Done,
13457 // Label 776: @32565
13458 GIM_Try, /*On fail goto*//*Label 777*/ 32612, // Rule ID 708 //
13459 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
13460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
13461 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13462 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
13465 // (intrinsic_wo_chain:{ *:[f32] } 2344:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRS,
13467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
13469 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13470 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13471 GIR_EraseFromParent, /*InsnID*/0,
13472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13473 // GIR_Coverage, 708,
13474 GIR_Done,
13475 // Label 777: @32612
13476 GIM_Try, /*On fail goto*//*Label 778*/ 32659, // Rule ID 709 //
13477 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
13478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
13479 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13480 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13483 // (intrinsic_wo_chain:{ *:[f32] } 2345:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
13484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRD,
13485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
13487 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13488 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13489 GIR_EraseFromParent, /*InsnID*/0,
13490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13491 // GIR_Coverage, 709,
13492 GIR_Done,
13493 // Label 778: @32659
13494 GIM_Try, /*On fail goto*//*Label 779*/ 32706, // Rule ID 710 //
13495 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
13496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
13497 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13498 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
13500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
13501 // (intrinsic_wo_chain:{ *:[f32] } 2345:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRS,
13503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
13504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
13505 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13506 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13507 GIR_EraseFromParent, /*InsnID*/0,
13508 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13509 // GIR_Coverage, 710,
13510 GIR_Done,
13511 // Label 779: @32706
13512 GIM_Try, /*On fail goto*//*Label 780*/ 32753, // Rule ID 1258 //
13513 GIM_CheckFeatures, GIFBS_HasNEON,
13514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
13515 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13516 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13519 // (intrinsic_wo_chain:{ *:[v4i16] } 2197:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
13520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i8,
13521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13523 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13524 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13525 GIR_EraseFromParent, /*InsnID*/0,
13526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13527 // GIR_Coverage, 1258,
13528 GIR_Done,
13529 // Label 780: @32753
13530 GIM_Try, /*On fail goto*//*Label 781*/ 32800, // Rule ID 1259 //
13531 GIM_CheckFeatures, GIFBS_HasNEON,
13532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
13533 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13534 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13537 // (intrinsic_wo_chain:{ *:[v2i32] } 2197:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
13538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i16,
13539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13541 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13542 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13543 GIR_EraseFromParent, /*InsnID*/0,
13544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13545 // GIR_Coverage, 1259,
13546 GIR_Done,
13547 // Label 781: @32800
13548 GIM_Try, /*On fail goto*//*Label 782*/ 32847, // Rule ID 1260 //
13549 GIM_CheckFeatures, GIFBS_HasNEON,
13550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
13551 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
13552 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13555 // (intrinsic_wo_chain:{ *:[v1i64] } 2197:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
13556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv2i32,
13557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13559 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13560 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13561 GIR_EraseFromParent, /*InsnID*/0,
13562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13563 // GIR_Coverage, 1260,
13564 GIR_Done,
13565 // Label 782: @32847
13566 GIM_Try, /*On fail goto*//*Label 783*/ 32894, // Rule ID 1261 //
13567 GIM_CheckFeatures, GIFBS_HasNEON,
13568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
13569 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13570 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13573 // (intrinsic_wo_chain:{ *:[v8i16] } 2197:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
13574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv16i8,
13575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13577 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13578 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13579 GIR_EraseFromParent, /*InsnID*/0,
13580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13581 // GIR_Coverage, 1261,
13582 GIR_Done,
13583 // Label 783: @32894
13584 GIM_Try, /*On fail goto*//*Label 784*/ 32941, // Rule ID 1262 //
13585 GIM_CheckFeatures, GIFBS_HasNEON,
13586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
13587 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13588 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13591 // (intrinsic_wo_chain:{ *:[v4i32] } 2197:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
13592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i16,
13593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13595 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13596 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13597 GIR_EraseFromParent, /*InsnID*/0,
13598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13599 // GIR_Coverage, 1262,
13600 GIR_Done,
13601 // Label 784: @32941
13602 GIM_Try, /*On fail goto*//*Label 785*/ 32988, // Rule ID 1263 //
13603 GIM_CheckFeatures, GIFBS_HasNEON,
13604 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
13605 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
13606 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13609 // (intrinsic_wo_chain:{ *:[v2i64] } 2197:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
13610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i32,
13611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13613 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13614 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13615 GIR_EraseFromParent, /*InsnID*/0,
13616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13617 // GIR_Coverage, 1263,
13618 GIR_Done,
13619 // Label 785: @32988
13620 GIM_Try, /*On fail goto*//*Label 786*/ 33035, // Rule ID 1264 //
13621 GIM_CheckFeatures, GIFBS_HasNEON,
13622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
13623 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13627 // (intrinsic_wo_chain:{ *:[v4i16] } 2198:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
13628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i8,
13629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13631 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13632 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13633 GIR_EraseFromParent, /*InsnID*/0,
13634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13635 // GIR_Coverage, 1264,
13636 GIR_Done,
13637 // Label 786: @33035
13638 GIM_Try, /*On fail goto*//*Label 787*/ 33082, // Rule ID 1265 //
13639 GIM_CheckFeatures, GIFBS_HasNEON,
13640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
13641 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13642 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13645 // (intrinsic_wo_chain:{ *:[v2i32] } 2198:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
13646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i16,
13647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13649 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13650 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13651 GIR_EraseFromParent, /*InsnID*/0,
13652 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13653 // GIR_Coverage, 1265,
13654 GIR_Done,
13655 // Label 787: @33082
13656 GIM_Try, /*On fail goto*//*Label 788*/ 33129, // Rule ID 1266 //
13657 GIM_CheckFeatures, GIFBS_HasNEON,
13658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
13659 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
13660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13663 // (intrinsic_wo_chain:{ *:[v1i64] } 2198:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
13664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv2i32,
13665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13667 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13668 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13669 GIR_EraseFromParent, /*InsnID*/0,
13670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13671 // GIR_Coverage, 1266,
13672 GIR_Done,
13673 // Label 788: @33129
13674 GIM_Try, /*On fail goto*//*Label 789*/ 33176, // Rule ID 1267 //
13675 GIM_CheckFeatures, GIFBS_HasNEON,
13676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
13677 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13678 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13681 // (intrinsic_wo_chain:{ *:[v8i16] } 2198:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
13682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv16i8,
13683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13685 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13686 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13687 GIR_EraseFromParent, /*InsnID*/0,
13688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13689 // GIR_Coverage, 1267,
13690 GIR_Done,
13691 // Label 789: @33176
13692 GIM_Try, /*On fail goto*//*Label 790*/ 33223, // Rule ID 1268 //
13693 GIM_CheckFeatures, GIFBS_HasNEON,
13694 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
13695 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13696 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13699 // (intrinsic_wo_chain:{ *:[v4i32] } 2198:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
13700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i16,
13701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13703 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13704 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13705 GIR_EraseFromParent, /*InsnID*/0,
13706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13707 // GIR_Coverage, 1268,
13708 GIR_Done,
13709 // Label 790: @33223
13710 GIM_Try, /*On fail goto*//*Label 791*/ 33270, // Rule ID 1269 //
13711 GIM_CheckFeatures, GIFBS_HasNEON,
13712 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
13713 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
13714 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13717 // (intrinsic_wo_chain:{ *:[v2i64] } 2198:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
13718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i32,
13719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13721 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13722 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13723 GIR_EraseFromParent, /*InsnID*/0,
13724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13725 // GIR_Coverage, 1269,
13726 GIR_Done,
13727 // Label 791: @33270
13728 GIM_Try, /*On fail goto*//*Label 792*/ 33317, // Rule ID 1298 //
13729 GIM_CheckFeatures, GIFBS_HasNEON,
13730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
13731 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13732 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13735 // (intrinsic_wo_chain:{ *:[v2i32] } 2223:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
13736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEd,
13737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13739 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13740 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13741 GIR_EraseFromParent, /*InsnID*/0,
13742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13743 // GIR_Coverage, 1298,
13744 GIR_Done,
13745 // Label 792: @33317
13746 GIM_Try, /*On fail goto*//*Label 793*/ 33364, // Rule ID 1299 //
13747 GIM_CheckFeatures, GIFBS_HasNEON,
13748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
13749 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13750 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13753 // (intrinsic_wo_chain:{ *:[v4i32] } 2223:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
13754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEq,
13755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13757 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13758 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13759 GIR_EraseFromParent, /*InsnID*/0,
13760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13761 // GIR_Coverage, 1299,
13762 GIR_Done,
13763 // Label 793: @33364
13764 GIM_Try, /*On fail goto*//*Label 794*/ 33411, // Rule ID 1300 //
13765 GIM_CheckFeatures, GIFBS_HasNEON,
13766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
13767 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13768 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13771 // (intrinsic_wo_chain:{ *:[v2f32] } 2223:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfd,
13773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13775 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13776 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13777 GIR_EraseFromParent, /*InsnID*/0,
13778 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13779 // GIR_Coverage, 1300,
13780 GIR_Done,
13781 // Label 794: @33411
13782 GIM_Try, /*On fail goto*//*Label 795*/ 33458, // Rule ID 1301 //
13783 GIM_CheckFeatures, GIFBS_HasNEON,
13784 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
13785 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13786 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13789 // (intrinsic_wo_chain:{ *:[v4f32] } 2223:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfq,
13791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13793 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13794 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13795 GIR_EraseFromParent, /*InsnID*/0,
13796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13797 // GIR_Coverage, 1301,
13798 GIR_Done,
13799 // Label 795: @33458
13800 GIM_Try, /*On fail goto*//*Label 796*/ 33505, // Rule ID 1302 //
13801 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
13802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
13803 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13807 // (intrinsic_wo_chain:{ *:[v4f16] } 2223:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhd,
13809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13811 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13812 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13813 GIR_EraseFromParent, /*InsnID*/0,
13814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13815 // GIR_Coverage, 1302,
13816 GIR_Done,
13817 // Label 796: @33505
13818 GIM_Try, /*On fail goto*//*Label 797*/ 33552, // Rule ID 1303 //
13819 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
13820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
13821 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13822 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13825 // (intrinsic_wo_chain:{ *:[v8f16] } 2223:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhq,
13827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13829 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13830 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13831 GIR_EraseFromParent, /*InsnID*/0,
13832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13833 // GIR_Coverage, 1303,
13834 GIR_Done,
13835 // Label 797: @33552
13836 GIM_Try, /*On fail goto*//*Label 798*/ 33599, // Rule ID 1308 //
13837 GIM_CheckFeatures, GIFBS_HasNEON,
13838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
13839 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13840 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13843 // (intrinsic_wo_chain:{ *:[v2i32] } 2236:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
13844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEd,
13845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13847 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13848 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13849 GIR_EraseFromParent, /*InsnID*/0,
13850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13851 // GIR_Coverage, 1308,
13852 GIR_Done,
13853 // Label 798: @33599
13854 GIM_Try, /*On fail goto*//*Label 799*/ 33646, // Rule ID 1309 //
13855 GIM_CheckFeatures, GIFBS_HasNEON,
13856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
13857 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13861 // (intrinsic_wo_chain:{ *:[v4i32] } 2236:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
13862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEq,
13863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13865 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13866 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13867 GIR_EraseFromParent, /*InsnID*/0,
13868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13869 // GIR_Coverage, 1309,
13870 GIR_Done,
13871 // Label 799: @33646
13872 GIM_Try, /*On fail goto*//*Label 800*/ 33693, // Rule ID 1310 //
13873 GIM_CheckFeatures, GIFBS_HasNEON,
13874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
13875 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13876 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13879 // (intrinsic_wo_chain:{ *:[v2f32] } 2236:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfd,
13881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13883 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13884 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13885 GIR_EraseFromParent, /*InsnID*/0,
13886 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13887 // GIR_Coverage, 1310,
13888 GIR_Done,
13889 // Label 800: @33693
13890 GIM_Try, /*On fail goto*//*Label 801*/ 33740, // Rule ID 1311 //
13891 GIM_CheckFeatures, GIFBS_HasNEON,
13892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
13893 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13894 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13897 // (intrinsic_wo_chain:{ *:[v4f32] } 2236:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfq,
13899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13901 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13902 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13903 GIR_EraseFromParent, /*InsnID*/0,
13904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13905 // GIR_Coverage, 1311,
13906 GIR_Done,
13907 // Label 801: @33740
13908 GIM_Try, /*On fail goto*//*Label 802*/ 33787, // Rule ID 1312 //
13909 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
13910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
13911 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13912 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13915 // (intrinsic_wo_chain:{ *:[v4f16] } 2236:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhd,
13917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13919 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13920 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13921 GIR_EraseFromParent, /*InsnID*/0,
13922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13923 // GIR_Coverage, 1312,
13924 GIR_Done,
13925 // Label 802: @33787
13926 GIM_Try, /*On fail goto*//*Label 803*/ 33834, // Rule ID 1313 //
13927 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
13928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
13929 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13930 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13933 // (intrinsic_wo_chain:{ *:[v8f16] } 2236:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhq,
13935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13937 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13938 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13939 GIR_EraseFromParent, /*InsnID*/0,
13940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13941 // GIR_Coverage, 1313,
13942 GIR_Done,
13943 // Label 803: @33834
13944 GIM_Try, /*On fail goto*//*Label 804*/ 33881, // Rule ID 1534 //
13945 GIM_CheckFeatures, GIFBS_HasNEON,
13946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
13947 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
13948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13951 // (intrinsic_wo_chain:{ *:[v8i8] } 2203:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
13952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i8,
13953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13955 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13956 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13957 GIR_EraseFromParent, /*InsnID*/0,
13958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13959 // GIR_Coverage, 1534,
13960 GIR_Done,
13961 // Label 804: @33881
13962 GIM_Try, /*On fail goto*//*Label 805*/ 33928, // Rule ID 1535 //
13963 GIM_CheckFeatures, GIFBS_HasNEON,
13964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
13965 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13966 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13969 // (intrinsic_wo_chain:{ *:[v4i16] } 2203:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
13970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i16,
13971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13973 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13974 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13975 GIR_EraseFromParent, /*InsnID*/0,
13976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13977 // GIR_Coverage, 1535,
13978 GIR_Done,
13979 // Label 805: @33928
13980 GIM_Try, /*On fail goto*//*Label 806*/ 33975, // Rule ID 1536 //
13981 GIM_CheckFeatures, GIFBS_HasNEON,
13982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
13983 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13984 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13987 // (intrinsic_wo_chain:{ *:[v2i32] } 2203:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
13988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv2i32,
13989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
13991 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13992 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
13993 GIR_EraseFromParent, /*InsnID*/0,
13994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13995 // GIR_Coverage, 1536,
13996 GIR_Done,
13997 // Label 806: @33975
13998 GIM_Try, /*On fail goto*//*Label 807*/ 34022, // Rule ID 1537 //
13999 GIM_CheckFeatures, GIFBS_HasNEON,
14000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14001 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14005 // (intrinsic_wo_chain:{ *:[v16i8] } 2203:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv16i8,
14007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14009 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14010 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14011 GIR_EraseFromParent, /*InsnID*/0,
14012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14013 // GIR_Coverage, 1537,
14014 GIR_Done,
14015 // Label 807: @34022
14016 GIM_Try, /*On fail goto*//*Label 808*/ 34069, // Rule ID 1538 //
14017 GIM_CheckFeatures, GIFBS_HasNEON,
14018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14019 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14020 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14023 // (intrinsic_wo_chain:{ *:[v8i16] } 2203:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i16,
14025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14027 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14028 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14029 GIR_EraseFromParent, /*InsnID*/0,
14030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14031 // GIR_Coverage, 1538,
14032 GIR_Done,
14033 // Label 808: @34069
14034 GIM_Try, /*On fail goto*//*Label 809*/ 34116, // Rule ID 1539 //
14035 GIM_CheckFeatures, GIFBS_HasNEON,
14036 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
14037 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14038 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14041 // (intrinsic_wo_chain:{ *:[v4i32] } 2203:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i32,
14043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14045 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14046 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14047 GIR_EraseFromParent, /*InsnID*/0,
14048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14049 // GIR_Coverage, 1539,
14050 GIR_Done,
14051 // Label 809: @34116
14052 GIM_Try, /*On fail goto*//*Label 810*/ 34163, // Rule ID 1550 //
14053 GIM_CheckFeatures, GIFBS_HasNEON,
14054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14055 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14056 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14059 // (intrinsic_wo_chain:{ *:[v8i8] } 2209:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i8,
14061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14063 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14064 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14065 GIR_EraseFromParent, /*InsnID*/0,
14066 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14067 // GIR_Coverage, 1550,
14068 GIR_Done,
14069 // Label 810: @34163
14070 GIM_Try, /*On fail goto*//*Label 811*/ 34210, // Rule ID 1551 //
14071 GIM_CheckFeatures, GIFBS_HasNEON,
14072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14073 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14074 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14077 // (intrinsic_wo_chain:{ *:[v4i16] } 2209:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i16,
14079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14081 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14082 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14083 GIR_EraseFromParent, /*InsnID*/0,
14084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14085 // GIR_Coverage, 1551,
14086 GIR_Done,
14087 // Label 811: @34210
14088 GIM_Try, /*On fail goto*//*Label 812*/ 34257, // Rule ID 1552 //
14089 GIM_CheckFeatures, GIFBS_HasNEON,
14090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14091 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14092 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14095 // (intrinsic_wo_chain:{ *:[v2i32] } 2209:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv2i32,
14097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14099 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14100 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14101 GIR_EraseFromParent, /*InsnID*/0,
14102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14103 // GIR_Coverage, 1552,
14104 GIR_Done,
14105 // Label 812: @34257
14106 GIM_Try, /*On fail goto*//*Label 813*/ 34304, // Rule ID 1553 //
14107 GIM_CheckFeatures, GIFBS_HasNEON,
14108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14109 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14110 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14113 // (intrinsic_wo_chain:{ *:[v16i8] } 2209:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv16i8,
14115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14117 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14118 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14119 GIR_EraseFromParent, /*InsnID*/0,
14120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14121 // GIR_Coverage, 1553,
14122 GIR_Done,
14123 // Label 813: @34304
14124 GIM_Try, /*On fail goto*//*Label 814*/ 34351, // Rule ID 1554 //
14125 GIM_CheckFeatures, GIFBS_HasNEON,
14126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14127 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14131 // (intrinsic_wo_chain:{ *:[v8i16] } 2209:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i16,
14133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14135 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14136 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14137 GIR_EraseFromParent, /*InsnID*/0,
14138 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14139 // GIR_Coverage, 1554,
14140 GIR_Done,
14141 // Label 814: @34351
14142 GIM_Try, /*On fail goto*//*Label 815*/ 34398, // Rule ID 1555 //
14143 GIM_CheckFeatures, GIFBS_HasNEON,
14144 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
14145 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14146 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14149 // (intrinsic_wo_chain:{ *:[v4i32] } 2209:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14150 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i32,
14151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14153 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14154 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14155 GIR_EraseFromParent, /*InsnID*/0,
14156 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14157 // GIR_Coverage, 1555,
14158 GIR_Done,
14159 // Label 815: @34398
14160 GIM_Try, /*On fail goto*//*Label 816*/ 34445, // Rule ID 1556 //
14161 GIM_CheckFeatures, GIFBS_HasNEON,
14162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14163 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14164 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14167 // (intrinsic_wo_chain:{ *:[v8i8] } 2150:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i8,
14169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14171 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14172 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14173 GIR_EraseFromParent, /*InsnID*/0,
14174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14175 // GIR_Coverage, 1556,
14176 GIR_Done,
14177 // Label 816: @34445
14178 GIM_Try, /*On fail goto*//*Label 817*/ 34492, // Rule ID 1557 //
14179 GIM_CheckFeatures, GIFBS_HasNEON,
14180 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14181 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14182 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14185 // (intrinsic_wo_chain:{ *:[v4i16] } 2150:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i16,
14187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14189 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14190 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14191 GIR_EraseFromParent, /*InsnID*/0,
14192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14193 // GIR_Coverage, 1557,
14194 GIR_Done,
14195 // Label 817: @34492
14196 GIM_Try, /*On fail goto*//*Label 818*/ 34539, // Rule ID 1558 //
14197 GIM_CheckFeatures, GIFBS_HasNEON,
14198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14199 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14200 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14203 // (intrinsic_wo_chain:{ *:[v2i32] } 2150:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv2i32,
14205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14207 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14208 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14209 GIR_EraseFromParent, /*InsnID*/0,
14210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14211 // GIR_Coverage, 1558,
14212 GIR_Done,
14213 // Label 818: @34539
14214 GIM_Try, /*On fail goto*//*Label 819*/ 34586, // Rule ID 1559 //
14215 GIM_CheckFeatures, GIFBS_HasNEON,
14216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14217 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14218 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14221 // (intrinsic_wo_chain:{ *:[v16i8] } 2150:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv16i8,
14223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14225 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14226 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14227 GIR_EraseFromParent, /*InsnID*/0,
14228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14229 // GIR_Coverage, 1559,
14230 GIR_Done,
14231 // Label 819: @34586
14232 GIM_Try, /*On fail goto*//*Label 820*/ 34633, // Rule ID 1560 //
14233 GIM_CheckFeatures, GIFBS_HasNEON,
14234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14239 // (intrinsic_wo_chain:{ *:[v8i16] } 2150:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i16,
14241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14243 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14244 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14245 GIR_EraseFromParent, /*InsnID*/0,
14246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14247 // GIR_Coverage, 1560,
14248 GIR_Done,
14249 // Label 820: @34633
14250 GIM_Try, /*On fail goto*//*Label 821*/ 34680, // Rule ID 1561 //
14251 GIM_CheckFeatures, GIFBS_HasNEON,
14252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
14253 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14254 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14257 // (intrinsic_wo_chain:{ *:[v4i32] } 2150:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i32,
14259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14261 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14262 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14263 GIR_EraseFromParent, /*InsnID*/0,
14264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14265 // GIR_Coverage, 1561,
14266 GIR_Done,
14267 // Label 821: @34680
14268 GIM_Try, /*On fail goto*//*Label 822*/ 34727, // Rule ID 1605 //
14269 GIM_CheckFeatures, GIFBS_HasNEON,
14270 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
14271 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14272 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14275 // (intrinsic_wo_chain:{ *:[v8i8] } 2206:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv8i8,
14277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14279 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14280 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14281 GIR_EraseFromParent, /*InsnID*/0,
14282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14283 // GIR_Coverage, 1605,
14284 GIR_Done,
14285 // Label 822: @34727
14286 GIM_Try, /*On fail goto*//*Label 823*/ 34774, // Rule ID 1606 //
14287 GIM_CheckFeatures, GIFBS_HasNEON,
14288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
14289 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14290 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14293 // (intrinsic_wo_chain:{ *:[v4i16] } 2206:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14294 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv4i16,
14295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14297 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14298 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14299 GIR_EraseFromParent, /*InsnID*/0,
14300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14301 // GIR_Coverage, 1606,
14302 GIR_Done,
14303 // Label 823: @34774
14304 GIM_Try, /*On fail goto*//*Label 824*/ 34821, // Rule ID 1607 //
14305 GIM_CheckFeatures, GIFBS_HasNEON,
14306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
14307 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14308 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14311 // (intrinsic_wo_chain:{ *:[v2i32] } 2206:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv2i32,
14313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14315 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14316 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14317 GIR_EraseFromParent, /*InsnID*/0,
14318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14319 // GIR_Coverage, 1607,
14320 GIR_Done,
14321 // Label 824: @34821
14322 GIM_Try, /*On fail goto*//*Label 825*/ 34868, // Rule ID 1608 //
14323 GIM_CheckFeatures, GIFBS_HasNEON,
14324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
14325 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14326 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14329 // (intrinsic_wo_chain:{ *:[v8i8] } 2208:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv8i8,
14331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14333 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14334 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14335 GIR_EraseFromParent, /*InsnID*/0,
14336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14337 // GIR_Coverage, 1608,
14338 GIR_Done,
14339 // Label 825: @34868
14340 GIM_Try, /*On fail goto*//*Label 826*/ 34915, // Rule ID 1609 //
14341 GIM_CheckFeatures, GIFBS_HasNEON,
14342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
14343 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14344 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14347 // (intrinsic_wo_chain:{ *:[v4i16] } 2208:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv4i16,
14349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14351 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14352 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14353 GIR_EraseFromParent, /*InsnID*/0,
14354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14355 // GIR_Coverage, 1609,
14356 GIR_Done,
14357 // Label 826: @34915
14358 GIM_Try, /*On fail goto*//*Label 827*/ 34962, // Rule ID 1610 //
14359 GIM_CheckFeatures, GIFBS_HasNEON,
14360 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
14361 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14362 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14365 // (intrinsic_wo_chain:{ *:[v2i32] } 2208:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv2i32,
14367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14369 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14370 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14371 GIR_EraseFromParent, /*InsnID*/0,
14372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14373 // GIR_Coverage, 1610,
14374 GIR_Done,
14375 // Label 827: @34962
14376 GIM_Try, /*On fail goto*//*Label 828*/ 35009, // Rule ID 1611 //
14377 GIM_CheckFeatures, GIFBS_HasNEON,
14378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
14379 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14380 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14383 // (intrinsic_wo_chain:{ *:[v8i8] } 2207:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv8i8,
14385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14387 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14388 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14389 GIR_EraseFromParent, /*InsnID*/0,
14390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14391 // GIR_Coverage, 1611,
14392 GIR_Done,
14393 // Label 828: @35009
14394 GIM_Try, /*On fail goto*//*Label 829*/ 35056, // Rule ID 1612 //
14395 GIM_CheckFeatures, GIFBS_HasNEON,
14396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
14397 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14401 // (intrinsic_wo_chain:{ *:[v4i16] } 2207:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv4i16,
14403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14405 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14406 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14407 GIR_EraseFromParent, /*InsnID*/0,
14408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14409 // GIR_Coverage, 1612,
14410 GIR_Done,
14411 // Label 829: @35056
14412 GIM_Try, /*On fail goto*//*Label 830*/ 35103, // Rule ID 1613 //
14413 GIM_CheckFeatures, GIFBS_HasNEON,
14414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
14415 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14419 // (intrinsic_wo_chain:{ *:[v2i32] } 2207:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv2i32,
14421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14423 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14424 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14425 GIR_EraseFromParent, /*InsnID*/0,
14426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14427 // GIR_Coverage, 1613,
14428 GIR_Done,
14429 // Label 830: @35103
14430 GIM_Try, /*On fail goto*//*Label 831*/ 35143, // Rule ID 1636 //
14431 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
14433 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14434 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14437 // (intrinsic_wo_chain:{ *:[v2i32] } 2151:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDf,
14439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14441 GIR_EraseFromParent, /*InsnID*/0,
14442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14443 // GIR_Coverage, 1636,
14444 GIR_Done,
14445 // Label 831: @35143
14446 GIM_Try, /*On fail goto*//*Label 832*/ 35183, // Rule ID 1637 //
14447 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14448 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
14449 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14450 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14453 // (intrinsic_wo_chain:{ *:[v4i32] } 2151:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQf,
14455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14457 GIR_EraseFromParent, /*InsnID*/0,
14458 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14459 // GIR_Coverage, 1637,
14460 GIR_Done,
14461 // Label 832: @35183
14462 GIM_Try, /*On fail goto*//*Label 833*/ 35223, // Rule ID 1638 //
14463 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14464 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
14465 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14466 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14469 // (intrinsic_wo_chain:{ *:[v2i32] } 2152:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDf,
14471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14473 GIR_EraseFromParent, /*InsnID*/0,
14474 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14475 // GIR_Coverage, 1638,
14476 GIR_Done,
14477 // Label 833: @35223
14478 GIM_Try, /*On fail goto*//*Label 834*/ 35263, // Rule ID 1639 //
14479 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14480 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
14481 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14482 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14485 // (intrinsic_wo_chain:{ *:[v4i32] } 2152:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQf,
14487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14489 GIR_EraseFromParent, /*InsnID*/0,
14490 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14491 // GIR_Coverage, 1639,
14492 GIR_Done,
14493 // Label 834: @35263
14494 GIM_Try, /*On fail goto*//*Label 835*/ 35303, // Rule ID 1640 //
14495 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
14497 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14498 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14501 // (intrinsic_wo_chain:{ *:[v4i16] } 2151:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDh,
14503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14505 GIR_EraseFromParent, /*InsnID*/0,
14506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14507 // GIR_Coverage, 1640,
14508 GIR_Done,
14509 // Label 835: @35303
14510 GIM_Try, /*On fail goto*//*Label 836*/ 35343, // Rule ID 1641 //
14511 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14512 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
14513 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14514 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14517 // (intrinsic_wo_chain:{ *:[v8i16] } 2151:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQh,
14519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14521 GIR_EraseFromParent, /*InsnID*/0,
14522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14523 // GIR_Coverage, 1641,
14524 GIR_Done,
14525 // Label 836: @35343
14526 GIM_Try, /*On fail goto*//*Label 837*/ 35383, // Rule ID 1642 //
14527 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14528 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
14529 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14530 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14533 // (intrinsic_wo_chain:{ *:[v4i16] } 2152:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDh,
14535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14537 GIR_EraseFromParent, /*InsnID*/0,
14538 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14539 // GIR_Coverage, 1642,
14540 GIR_Done,
14541 // Label 837: @35383
14542 GIM_Try, /*On fail goto*//*Label 838*/ 35423, // Rule ID 1643 //
14543 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14544 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
14545 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14546 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14549 // (intrinsic_wo_chain:{ *:[v8i16] } 2152:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQh,
14551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14553 GIR_EraseFromParent, /*InsnID*/0,
14554 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14555 // GIR_Coverage, 1643,
14556 GIR_Done,
14557 // Label 838: @35423
14558 GIM_Try, /*On fail goto*//*Label 839*/ 35463, // Rule ID 1644 //
14559 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14560 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
14561 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14562 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14565 // (intrinsic_wo_chain:{ *:[v2i32] } 2163:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDf,
14567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14569 GIR_EraseFromParent, /*InsnID*/0,
14570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14571 // GIR_Coverage, 1644,
14572 GIR_Done,
14573 // Label 839: @35463
14574 GIM_Try, /*On fail goto*//*Label 840*/ 35503, // Rule ID 1645 //
14575 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
14577 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14578 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14581 // (intrinsic_wo_chain:{ *:[v4i32] } 2163:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQf,
14583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14585 GIR_EraseFromParent, /*InsnID*/0,
14586 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14587 // GIR_Coverage, 1645,
14588 GIR_Done,
14589 // Label 840: @35503
14590 GIM_Try, /*On fail goto*//*Label 841*/ 35543, // Rule ID 1646 //
14591 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
14593 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14594 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14597 // (intrinsic_wo_chain:{ *:[v2i32] } 2164:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDf,
14599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14601 GIR_EraseFromParent, /*InsnID*/0,
14602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14603 // GIR_Coverage, 1646,
14604 GIR_Done,
14605 // Label 841: @35543
14606 GIM_Try, /*On fail goto*//*Label 842*/ 35583, // Rule ID 1647 //
14607 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14608 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
14609 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14610 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14613 // (intrinsic_wo_chain:{ *:[v4i32] } 2164:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14614 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQf,
14615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14617 GIR_EraseFromParent, /*InsnID*/0,
14618 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14619 // GIR_Coverage, 1647,
14620 GIR_Done,
14621 // Label 842: @35583
14622 GIM_Try, /*On fail goto*//*Label 843*/ 35623, // Rule ID 1648 //
14623 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14624 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
14625 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14626 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14629 // (intrinsic_wo_chain:{ *:[v4i16] } 2163:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDh,
14631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14633 GIR_EraseFromParent, /*InsnID*/0,
14634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14635 // GIR_Coverage, 1648,
14636 GIR_Done,
14637 // Label 843: @35623
14638 GIM_Try, /*On fail goto*//*Label 844*/ 35663, // Rule ID 1649 //
14639 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
14641 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14642 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14645 // (intrinsic_wo_chain:{ *:[v8i16] } 2163:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQh,
14647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14649 GIR_EraseFromParent, /*InsnID*/0,
14650 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14651 // GIR_Coverage, 1649,
14652 GIR_Done,
14653 // Label 844: @35663
14654 GIM_Try, /*On fail goto*//*Label 845*/ 35703, // Rule ID 1650 //
14655 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14656 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
14657 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14658 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14661 // (intrinsic_wo_chain:{ *:[v4i16] } 2164:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDh,
14663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14665 GIR_EraseFromParent, /*InsnID*/0,
14666 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14667 // GIR_Coverage, 1650,
14668 GIR_Done,
14669 // Label 845: @35703
14670 GIM_Try, /*On fail goto*//*Label 846*/ 35743, // Rule ID 1651 //
14671 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14672 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
14673 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14674 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14677 // (intrinsic_wo_chain:{ *:[v8i16] } 2164:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQh,
14679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14681 GIR_EraseFromParent, /*InsnID*/0,
14682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14683 // GIR_Coverage, 1651,
14684 GIR_Done,
14685 // Label 846: @35743
14686 GIM_Try, /*On fail goto*//*Label 847*/ 35783, // Rule ID 1652 //
14687 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14688 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
14689 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14690 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14693 // (intrinsic_wo_chain:{ *:[v2i32] } 2165:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDf,
14695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14697 GIR_EraseFromParent, /*InsnID*/0,
14698 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14699 // GIR_Coverage, 1652,
14700 GIR_Done,
14701 // Label 847: @35783
14702 GIM_Try, /*On fail goto*//*Label 848*/ 35823, // Rule ID 1653 //
14703 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
14705 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14706 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14709 // (intrinsic_wo_chain:{ *:[v4i32] } 2165:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14710 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQf,
14711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14713 GIR_EraseFromParent, /*InsnID*/0,
14714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14715 // GIR_Coverage, 1653,
14716 GIR_Done,
14717 // Label 848: @35823
14718 GIM_Try, /*On fail goto*//*Label 849*/ 35863, // Rule ID 1654 //
14719 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14720 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
14721 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14722 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14725 // (intrinsic_wo_chain:{ *:[v2i32] } 2166:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDf,
14727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14729 GIR_EraseFromParent, /*InsnID*/0,
14730 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14731 // GIR_Coverage, 1654,
14732 GIR_Done,
14733 // Label 849: @35863
14734 GIM_Try, /*On fail goto*//*Label 850*/ 35903, // Rule ID 1655 //
14735 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14736 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
14737 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14738 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14741 // (intrinsic_wo_chain:{ *:[v4i32] } 2166:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQf,
14743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14745 GIR_EraseFromParent, /*InsnID*/0,
14746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14747 // GIR_Coverage, 1655,
14748 GIR_Done,
14749 // Label 850: @35903
14750 GIM_Try, /*On fail goto*//*Label 851*/ 35943, // Rule ID 1656 //
14751 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
14753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14757 // (intrinsic_wo_chain:{ *:[v4i16] } 2165:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDh,
14759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14761 GIR_EraseFromParent, /*InsnID*/0,
14762 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14763 // GIR_Coverage, 1656,
14764 GIR_Done,
14765 // Label 851: @35943
14766 GIM_Try, /*On fail goto*//*Label 852*/ 35983, // Rule ID 1657 //
14767 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
14769 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14770 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14773 // (intrinsic_wo_chain:{ *:[v8i16] } 2165:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14774 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQh,
14775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14777 GIR_EraseFromParent, /*InsnID*/0,
14778 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14779 // GIR_Coverage, 1657,
14780 GIR_Done,
14781 // Label 852: @35983
14782 GIM_Try, /*On fail goto*//*Label 853*/ 36023, // Rule ID 1658 //
14783 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14784 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
14785 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14786 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14789 // (intrinsic_wo_chain:{ *:[v4i16] } 2166:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDh,
14791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14793 GIR_EraseFromParent, /*InsnID*/0,
14794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14795 // GIR_Coverage, 1658,
14796 GIR_Done,
14797 // Label 853: @36023
14798 GIM_Try, /*On fail goto*//*Label 854*/ 36063, // Rule ID 1659 //
14799 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14800 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
14801 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14802 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14805 // (intrinsic_wo_chain:{ *:[v8i16] } 2166:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQh,
14807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14809 GIR_EraseFromParent, /*InsnID*/0,
14810 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14811 // GIR_Coverage, 1659,
14812 GIR_Done,
14813 // Label 854: @36063
14814 GIM_Try, /*On fail goto*//*Label 855*/ 36103, // Rule ID 1660 //
14815 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14816 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
14817 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14818 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14821 // (intrinsic_wo_chain:{ *:[v2i32] } 2161:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDf,
14823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14825 GIR_EraseFromParent, /*InsnID*/0,
14826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14827 // GIR_Coverage, 1660,
14828 GIR_Done,
14829 // Label 855: @36103
14830 GIM_Try, /*On fail goto*//*Label 856*/ 36143, // Rule ID 1661 //
14831 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
14833 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14834 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14837 // (intrinsic_wo_chain:{ *:[v4i32] } 2161:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQf,
14839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14841 GIR_EraseFromParent, /*InsnID*/0,
14842 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14843 // GIR_Coverage, 1661,
14844 GIR_Done,
14845 // Label 856: @36143
14846 GIM_Try, /*On fail goto*//*Label 857*/ 36183, // Rule ID 1662 //
14847 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
14849 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14850 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14853 // (intrinsic_wo_chain:{ *:[v2i32] } 2162:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
14854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDf,
14855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14857 GIR_EraseFromParent, /*InsnID*/0,
14858 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14859 // GIR_Coverage, 1662,
14860 GIR_Done,
14861 // Label 857: @36183
14862 GIM_Try, /*On fail goto*//*Label 858*/ 36223, // Rule ID 1663 //
14863 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14864 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
14865 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14866 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14869 // (intrinsic_wo_chain:{ *:[v4i32] } 2162:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
14870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQf,
14871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14873 GIR_EraseFromParent, /*InsnID*/0,
14874 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14875 // GIR_Coverage, 1663,
14876 GIR_Done,
14877 // Label 858: @36223
14878 GIM_Try, /*On fail goto*//*Label 859*/ 36263, // Rule ID 1664 //
14879 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14880 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
14881 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14882 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14885 // (intrinsic_wo_chain:{ *:[v4i16] } 2161:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDh,
14887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14889 GIR_EraseFromParent, /*InsnID*/0,
14890 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14891 // GIR_Coverage, 1664,
14892 GIR_Done,
14893 // Label 859: @36263
14894 GIM_Try, /*On fail goto*//*Label 860*/ 36303, // Rule ID 1665 //
14895 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14896 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
14897 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14898 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14901 // (intrinsic_wo_chain:{ *:[v8i16] } 2161:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQh,
14903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14905 GIR_EraseFromParent, /*InsnID*/0,
14906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14907 // GIR_Coverage, 1665,
14908 GIR_Done,
14909 // Label 860: @36303
14910 GIM_Try, /*On fail goto*//*Label 861*/ 36343, // Rule ID 1666 //
14911 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
14913 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14914 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14917 // (intrinsic_wo_chain:{ *:[v4i16] } 2162:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
14918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDh,
14919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14921 GIR_EraseFromParent, /*InsnID*/0,
14922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14923 // GIR_Coverage, 1666,
14924 GIR_Done,
14925 // Label 861: @36343
14926 GIM_Try, /*On fail goto*//*Label 862*/ 36383, // Rule ID 1667 //
14927 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
14928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
14929 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14930 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14933 // (intrinsic_wo_chain:{ *:[v8i16] } 2162:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
14934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQh,
14935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14937 GIR_EraseFromParent, /*InsnID*/0,
14938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14939 // GIR_Coverage, 1667,
14940 GIR_Done,
14941 // Label 862: @36383
14942 GIM_Try, /*On fail goto*//*Label 863*/ 36430, // Rule ID 1684 //
14943 GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
14944 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2hf,
14945 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14946 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14949 // (intrinsic_wo_chain:{ *:[v4i16] } 2157:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
14950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h,
14951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14953 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14954 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14955 GIR_EraseFromParent, /*InsnID*/0,
14956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14957 // GIR_Coverage, 1684,
14958 GIR_Done,
14959 // Label 863: @36430
14960 GIM_Try, /*On fail goto*//*Label 864*/ 36477, // Rule ID 1685 //
14961 GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
14962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvthf2fp,
14963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14967 // (intrinsic_wo_chain:{ *:[v4f32] } 2160:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
14968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f,
14969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14971 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14972 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
14973 GIR_EraseFromParent, /*InsnID*/0,
14974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14975 // GIR_Coverage, 1685,
14976 GIR_Done,
14977 // Label 864: @36477
14978 GIM_Try, /*On fail goto*//*Label 865*/ 36517, // Rule ID 1707 //
14979 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14980 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
14981 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14982 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14985 // (intrinsic_wo_chain:{ *:[v2f32] } 2229:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDf,
14987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
14989 GIR_EraseFromParent, /*InsnID*/0,
14990 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14991 // GIR_Coverage, 1707,
14992 GIR_Done,
14993 // Label 865: @36517
14994 GIM_Try, /*On fail goto*//*Label 866*/ 36557, // Rule ID 1708 //
14995 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
14996 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
14997 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14998 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15001 // (intrinsic_wo_chain:{ *:[v4f32] } 2229:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15002 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQf,
15003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15005 GIR_EraseFromParent, /*InsnID*/0,
15006 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15007 // GIR_Coverage, 1708,
15008 GIR_Done,
15009 // Label 866: @36557
15010 GIM_Try, /*On fail goto*//*Label 867*/ 36597, // Rule ID 1709 //
15011 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15012 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
15013 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15014 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15017 // (intrinsic_wo_chain:{ *:[v4f16] } 2229:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDh,
15019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15021 GIR_EraseFromParent, /*InsnID*/0,
15022 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15023 // GIR_Coverage, 1709,
15024 GIR_Done,
15025 // Label 867: @36597
15026 GIM_Try, /*On fail goto*//*Label 868*/ 36637, // Rule ID 1710 //
15027 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
15029 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15030 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15033 // (intrinsic_wo_chain:{ *:[v8f16] } 2229:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQh,
15035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15037 GIR_EraseFromParent, /*InsnID*/0,
15038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15039 // GIR_Coverage, 1710,
15040 GIR_Done,
15041 // Label 868: @36637
15042 GIM_Try, /*On fail goto*//*Label 869*/ 36677, // Rule ID 1711 //
15043 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15045 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15046 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15049 // (intrinsic_wo_chain:{ *:[v2f32] } 2231:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15050 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDf,
15051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15053 GIR_EraseFromParent, /*InsnID*/0,
15054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15055 // GIR_Coverage, 1711,
15056 GIR_Done,
15057 // Label 869: @36677
15058 GIM_Try, /*On fail goto*//*Label 870*/ 36717, // Rule ID 1712 //
15059 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15061 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15062 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15065 // (intrinsic_wo_chain:{ *:[v4f32] } 2231:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQf,
15067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15069 GIR_EraseFromParent, /*InsnID*/0,
15070 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15071 // GIR_Coverage, 1712,
15072 GIR_Done,
15073 // Label 870: @36717
15074 GIM_Try, /*On fail goto*//*Label 871*/ 36757, // Rule ID 1713 //
15075 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15076 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15077 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15078 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15081 // (intrinsic_wo_chain:{ *:[v4f16] } 2231:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDh,
15083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15085 GIR_EraseFromParent, /*InsnID*/0,
15086 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15087 // GIR_Coverage, 1713,
15088 GIR_Done,
15089 // Label 871: @36757
15090 GIM_Try, /*On fail goto*//*Label 872*/ 36797, // Rule ID 1714 //
15091 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
15093 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15094 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15097 // (intrinsic_wo_chain:{ *:[v8f16] } 2231:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQh,
15099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15101 GIR_EraseFromParent, /*InsnID*/0,
15102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15103 // GIR_Coverage, 1714,
15104 GIR_Done,
15105 // Label 872: @36797
15106 GIM_Try, /*On fail goto*//*Label 873*/ 36837, // Rule ID 1715 //
15107 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15109 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15110 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15113 // (intrinsic_wo_chain:{ *:[v2f32] } 2227:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDf,
15115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15117 GIR_EraseFromParent, /*InsnID*/0,
15118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15119 // GIR_Coverage, 1715,
15120 GIR_Done,
15121 // Label 873: @36837
15122 GIM_Try, /*On fail goto*//*Label 874*/ 36877, // Rule ID 1716 //
15123 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15124 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15125 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15126 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15129 // (intrinsic_wo_chain:{ *:[v4f32] } 2227:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQf,
15131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15133 GIR_EraseFromParent, /*InsnID*/0,
15134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15135 // GIR_Coverage, 1716,
15136 GIR_Done,
15137 // Label 874: @36877
15138 GIM_Try, /*On fail goto*//*Label 875*/ 36917, // Rule ID 1717 //
15139 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15140 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15141 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15142 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15145 // (intrinsic_wo_chain:{ *:[v4f16] } 2227:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDh,
15147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15149 GIR_EraseFromParent, /*InsnID*/0,
15150 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15151 // GIR_Coverage, 1717,
15152 GIR_Done,
15153 // Label 875: @36917
15154 GIM_Try, /*On fail goto*//*Label 876*/ 36957, // Rule ID 1718 //
15155 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
15157 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15158 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15161 // (intrinsic_wo_chain:{ *:[v8f16] } 2227:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQh,
15163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15165 GIR_EraseFromParent, /*InsnID*/0,
15166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15167 // GIR_Coverage, 1718,
15168 GIR_Done,
15169 // Label 876: @36957
15170 GIM_Try, /*On fail goto*//*Label 877*/ 36997, // Rule ID 1719 //
15171 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15173 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15177 // (intrinsic_wo_chain:{ *:[v2f32] } 2232:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDf,
15179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15181 GIR_EraseFromParent, /*InsnID*/0,
15182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15183 // GIR_Coverage, 1719,
15184 GIR_Done,
15185 // Label 877: @36997
15186 GIM_Try, /*On fail goto*//*Label 878*/ 37037, // Rule ID 1720 //
15187 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15189 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15190 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15193 // (intrinsic_wo_chain:{ *:[v4f32] } 2232:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQf,
15195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15197 GIR_EraseFromParent, /*InsnID*/0,
15198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15199 // GIR_Coverage, 1720,
15200 GIR_Done,
15201 // Label 878: @37037
15202 GIM_Try, /*On fail goto*//*Label 879*/ 37077, // Rule ID 1721 //
15203 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15204 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15205 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15206 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15209 // (intrinsic_wo_chain:{ *:[v4f16] } 2232:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDh,
15211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15213 GIR_EraseFromParent, /*InsnID*/0,
15214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15215 // GIR_Coverage, 1721,
15216 GIR_Done,
15217 // Label 879: @37077
15218 GIM_Try, /*On fail goto*//*Label 880*/ 37117, // Rule ID 1722 //
15219 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15220 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
15221 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15225 // (intrinsic_wo_chain:{ *:[v8f16] } 2232:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQh,
15227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15229 GIR_EraseFromParent, /*InsnID*/0,
15230 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15231 // GIR_Coverage, 1722,
15232 GIR_Done,
15233 // Label 880: @37117
15234 GIM_Try, /*On fail goto*//*Label 881*/ 37157, // Rule ID 1723 //
15235 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15237 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15238 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15241 // (intrinsic_wo_chain:{ *:[v2f32] } 2228:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDf,
15243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15245 GIR_EraseFromParent, /*InsnID*/0,
15246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15247 // GIR_Coverage, 1723,
15248 GIR_Done,
15249 // Label 881: @37157
15250 GIM_Try, /*On fail goto*//*Label 882*/ 37197, // Rule ID 1724 //
15251 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15253 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15254 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15257 // (intrinsic_wo_chain:{ *:[v4f32] } 2228:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQf,
15259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15261 GIR_EraseFromParent, /*InsnID*/0,
15262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15263 // GIR_Coverage, 1724,
15264 GIR_Done,
15265 // Label 882: @37197
15266 GIM_Try, /*On fail goto*//*Label 883*/ 37237, // Rule ID 1725 //
15267 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15268 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15269 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15270 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15273 // (intrinsic_wo_chain:{ *:[v4f16] } 2228:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDh,
15275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15277 GIR_EraseFromParent, /*InsnID*/0,
15278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15279 // GIR_Coverage, 1725,
15280 GIR_Done,
15281 // Label 883: @37237
15282 GIM_Try, /*On fail goto*//*Label 884*/ 37277, // Rule ID 1726 //
15283 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15284 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
15285 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15286 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15289 // (intrinsic_wo_chain:{ *:[v8f16] } 2228:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQh,
15291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15293 GIR_EraseFromParent, /*InsnID*/0,
15294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15295 // GIR_Coverage, 1726,
15296 GIR_Done,
15297 // Label 884: @37277
15298 GIM_Try, /*On fail goto*//*Label 885*/ 37317, // Rule ID 1727 //
15299 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15300 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15301 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15302 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15305 // (intrinsic_wo_chain:{ *:[v2f32] } 2230:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDf,
15307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15309 GIR_EraseFromParent, /*InsnID*/0,
15310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15311 // GIR_Coverage, 1727,
15312 GIR_Done,
15313 // Label 885: @37317
15314 GIM_Try, /*On fail goto*//*Label 886*/ 37357, // Rule ID 1728 //
15315 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
15316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15317 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15318 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15321 // (intrinsic_wo_chain:{ *:[v4f32] } 2230:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQf,
15323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15325 GIR_EraseFromParent, /*InsnID*/0,
15326 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15327 // GIR_Coverage, 1728,
15328 GIR_Done,
15329 // Label 886: @37357
15330 GIM_Try, /*On fail goto*//*Label 887*/ 37397, // Rule ID 1729 //
15331 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15332 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15333 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15334 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15337 // (intrinsic_wo_chain:{ *:[v4f16] } 2230:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDh,
15339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15341 GIR_EraseFromParent, /*InsnID*/0,
15342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15343 // GIR_Coverage, 1729,
15344 GIR_Done,
15345 // Label 887: @37397
15346 GIM_Try, /*On fail goto*//*Label 888*/ 37437, // Rule ID 1730 //
15347 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
15348 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
15349 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15350 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15353 // (intrinsic_wo_chain:{ *:[v8f16] } 2230:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQh,
15355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15357 GIR_EraseFromParent, /*InsnID*/0,
15358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15359 // GIR_Coverage, 1730,
15360 GIR_Done,
15361 // Label 888: @37437
15362 GIM_Try, /*On fail goto*//*Label 889*/ 37477, // Rule ID 1733 //
15363 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
15364 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesimc,
15365 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15369 // (intrinsic_wo_chain:{ *:[v16i8] } 2120:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15370 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESIMC,
15371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15373 GIR_EraseFromParent, /*InsnID*/0,
15374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15375 // GIR_Coverage, 1733,
15376 GIR_Done,
15377 // Label 889: @37477
15378 GIM_Try, /*On fail goto*//*Label 890*/ 37517, // Rule ID 1734 //
15379 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
15380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesmc,
15381 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15385 // (intrinsic_wo_chain:{ *:[v16i8] } 2121:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESMC,
15387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
15389 GIR_EraseFromParent, /*InsnID*/0,
15390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15391 // GIR_Coverage, 1734,
15392 GIR_Done,
15393 // Label 890: @37517
15394 GIM_Try, /*On fail goto*//*Label 891*/ 37567, // Rule ID 1865 //
15395 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
15396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
15397 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
15401 // (intrinsic_wo_chain:{ *:[i32] } 2318:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
15402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTB16,
15403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
15405 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15406 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15407 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15408 GIR_EraseFromParent, /*InsnID*/0,
15409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15410 // GIR_Coverage, 1865,
15411 GIR_Done,
15412 // Label 891: @37567
15413 GIM_Try, /*On fail goto*//*Label 892*/ 37617, // Rule ID 2092 //
15414 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15415 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
15416 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15417 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15420 // (intrinsic_wo_chain:{ *:[i32] } 2318:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
15421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTB16,
15422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15424 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15425 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15426 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15427 GIR_EraseFromParent, /*InsnID*/0,
15428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15429 // GIR_Coverage, 2092,
15430 GIR_Done,
15431 // Label 892: @37617
15432 GIM_Try, /*On fail goto*//*Label 893*/ 37678, // Rule ID 3614 //
15433 GIM_CheckFeatures, GIFBS_HasMVEInt,
15434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcls,
15435 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15436 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
15438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
15439 // (intrinsic_wo_chain:{ *:[v16i8] } 2002:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
15440 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15441 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
15442 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
15443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLSs8,
15444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
15445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
15446 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15447 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15448 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15449 GIR_EraseFromParent, /*InsnID*/0,
15450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15451 // GIR_Coverage, 3614,
15452 GIR_Done,
15453 // Label 893: @37678
15454 GIM_Try, /*On fail goto*//*Label 894*/ 37739, // Rule ID 3616 //
15455 GIM_CheckFeatures, GIFBS_HasMVEInt,
15456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcls,
15457 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15458 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
15460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
15461 // (intrinsic_wo_chain:{ *:[v8i16] } 2002:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
15462 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15463 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
15464 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
15465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLSs16,
15466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
15467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
15468 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15469 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15470 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15471 GIR_EraseFromParent, /*InsnID*/0,
15472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15473 // GIR_Coverage, 3616,
15474 GIR_Done,
15475 // Label 894: @37739
15476 GIM_Try, /*On fail goto*//*Label 895*/ 37800, // Rule ID 3618 //
15477 GIM_CheckFeatures, GIFBS_HasMVEInt,
15478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcls,
15479 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15480 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
15482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
15483 // (intrinsic_wo_chain:{ *:[v4i32] } 2002:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
15484 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15485 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
15486 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
15487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLSs32,
15488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
15489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
15490 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15491 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15492 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15493 GIR_EraseFromParent, /*InsnID*/0,
15494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15495 // GIR_Coverage, 3618,
15496 GIR_Done,
15497 // Label 895: @37800
15498 GIM_Try, /*On fail goto*//*Label 896*/ 37861, // Rule ID 3918 //
15499 GIM_CheckFeatures, GIFBS_HasMVEFloat,
15500 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrintn,
15501 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15502 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
15504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
15505 // (intrinsic_wo_chain:{ *:[v8f16] } 2084:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15506 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15507 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
15508 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
15509 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16N,
15510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
15511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
15512 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15513 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15514 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15515 GIR_EraseFromParent, /*InsnID*/0,
15516 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15517 // GIR_Coverage, 3918,
15518 GIR_Done,
15519 // Label 896: @37861
15520 GIM_Try, /*On fail goto*//*Label 897*/ 37922, // Rule ID 3930 //
15521 GIM_CheckFeatures, GIFBS_HasMVEFloat,
15522 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrintn,
15523 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15524 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
15526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
15527 // (intrinsic_wo_chain:{ *:[v4f32] } 2084:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15528 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15529 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
15530 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
15531 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32N,
15532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
15533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
15534 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15535 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15536 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15537 GIR_EraseFromParent, /*InsnID*/0,
15538 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15539 // GIR_Coverage, 3930,
15540 GIR_Done,
15541 // Label 897: @37922
15542 GIM_Try, /*On fail goto*//*Label 898*/ 37969, // Rule ID 4744 //
15543 GIM_CheckFeatures, GIFBS_HasMVEInt,
15544 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp8,
15545 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s1,
15546 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
15548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15549 // (intrinsic_wo_chain:{ *:[v16i1] } 2010:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
15550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP8,
15551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
15552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15553 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15554 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15555 GIR_EraseFromParent, /*InsnID*/0,
15556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15557 // GIR_Coverage, 4744,
15558 GIR_Done,
15559 // Label 898: @37969
15560 GIM_Try, /*On fail goto*//*Label 899*/ 38016, // Rule ID 4746 //
15561 GIM_CheckFeatures, GIFBS_HasMVEInt,
15562 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp16,
15563 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s1,
15564 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
15566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15567 // (intrinsic_wo_chain:{ *:[v8i1] } 2007:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
15568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP16,
15569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
15570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15571 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15572 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15573 GIR_EraseFromParent, /*InsnID*/0,
15574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15575 // GIR_Coverage, 4746,
15576 GIR_Done,
15577 // Label 899: @38016
15578 GIM_Try, /*On fail goto*//*Label 900*/ 38063, // Rule ID 4748 //
15579 GIM_CheckFeatures, GIFBS_HasMVEInt,
15580 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp32,
15581 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1,
15582 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
15584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15585 // (intrinsic_wo_chain:{ *:[v4i1] } 2008:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
15586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP32,
15587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
15588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15589 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15590 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15591 GIR_EraseFromParent, /*InsnID*/0,
15592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15593 // GIR_Coverage, 4748,
15594 GIR_Done,
15595 // Label 900: @38063
15596 GIM_Try, /*On fail goto*//*Label 901*/ 38110, // Rule ID 4750 //
15597 GIM_CheckFeatures, GIFBS_HasMVEInt,
15598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vctp64,
15599 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s1,
15600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
15602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15603 // (intrinsic_wo_chain:{ *:[v4i1] } 2009:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
15604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCTP64,
15605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
15606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15607 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15608 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15609 GIR_EraseFromParent, /*InsnID*/0,
15610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15611 // GIR_Coverage, 4750,
15612 GIR_Done,
15613 // Label 901: @38110
15614 GIM_Try, /*On fail goto*//*Label 902*/ 38157, // Rule ID 615 //
15615 GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
15616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tt,
15617 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15619 // MIs[0] Rn
15620 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
15621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15622 // (intrinsic_wo_chain:{ *:[i32] } 1892:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
15623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TT,
15624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
15625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15626 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15627 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15628 GIR_EraseFromParent, /*InsnID*/0,
15629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15630 // GIR_Coverage, 615,
15631 GIR_Done,
15632 // Label 902: @38157
15633 GIM_Try, /*On fail goto*//*Label 903*/ 38204, // Rule ID 616 //
15634 GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
15635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttt,
15636 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15638 // MIs[0] Rn
15639 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
15640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15641 // (intrinsic_wo_chain:{ *:[i32] } 1895:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
15642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTT,
15643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
15644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15645 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15646 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15647 GIR_EraseFromParent, /*InsnID*/0,
15648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15649 // GIR_Coverage, 616,
15650 GIR_Done,
15651 // Label 903: @38204
15652 GIM_Try, /*On fail goto*//*Label 904*/ 38251, // Rule ID 617 //
15653 GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
15654 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_tta,
15655 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15657 // MIs[0] Rn
15658 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
15659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15660 // (intrinsic_wo_chain:{ *:[i32] } 1893:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
15661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTA,
15662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
15663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15664 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15665 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15666 GIR_EraseFromParent, /*InsnID*/0,
15667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15668 // GIR_Coverage, 617,
15669 GIR_Done,
15670 // Label 904: @38251
15671 GIM_Try, /*On fail goto*//*Label 905*/ 38298, // Rule ID 618 //
15672 GIM_CheckFeatures, GIFBS_Has8MSecExt_IsThumb,
15673 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_cmse_ttat,
15674 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15676 // MIs[0] Rn
15677 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
15678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15679 // (intrinsic_wo_chain:{ *:[i32] } 1894:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
15680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2TTAT,
15681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
15682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15683 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15684 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15685 GIR_EraseFromParent, /*InsnID*/0,
15686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15687 // GIR_Coverage, 618,
15688 GIR_Done,
15689 // Label 905: @38298
15690 GIM_Try, /*On fail goto*//*Label 906*/ 38419, // Rule ID 2608 //
15691 GIM_CheckFeatures, GIFBS_HasNEON,
15692 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1h,
15693 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15694 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
15696 // (intrinsic_wo_chain:{ *:[i32] } 2128:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
15697 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15698 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
15699 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
15700 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
15701 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
15702 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
15703 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15704 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
15705 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
15706 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
15707 GIR_AddImm, /*InsnID*/3, /*Imm*/0,
15708 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
15709 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
15710 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
15711 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
15712 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::SHA1H,
15713 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
15714 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
15715 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15716 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
15717 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
15718 GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, ARM::ssub_0,
15719 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::SPRRegClassID,
15720 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::MQPRRegClassID,
15721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
15722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
15723 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
15724 GIR_EraseFromParent, /*InsnID*/0,
15725 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
15726 // GIR_Coverage, 2608,
15727 GIR_Done,
15728 // Label 906: @38419
15729 GIM_Reject,
15730 // Label 770: @38420
15731 GIM_Try, /*On fail goto*//*Label 907*/ 60945,
15732 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
15733 GIM_Try, /*On fail goto*//*Label 908*/ 38487, // Rule ID 2110 //
15734 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15735 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
15736 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15737 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15738 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15742 // (intrinsic_wo_chain:{ *:[i32] } 2342:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
15743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB16,
15744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
15746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15747 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
15748 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15749 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15750 GIR_EraseFromParent, /*InsnID*/0,
15751 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15752 // GIR_Coverage, 2110,
15753 GIR_Done,
15754 // Label 908: @38487
15755 GIM_Try, /*On fail goto*//*Label 909*/ 38585, // Rule ID 1902 //
15756 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
15757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
15758 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15759 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15760 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15762 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15763 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
15764 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15765 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15766 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
15767 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15768 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
15769 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
15770 // MIs[2] Operand 1
15771 // No operand predicates
15772 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
15773 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15774 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
15775 // MIs[3] Operand 1
15776 // No operand predicates
15777 GIM_CheckIsSafeToFold, /*InsnID*/1,
15778 GIM_CheckIsSafeToFold, /*InsnID*/2,
15779 GIM_CheckIsSafeToFold, /*InsnID*/3,
15780 // (intrinsic_wo_chain:{ *:[i32] } 2337:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
15781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
15782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15783 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
15784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
15785 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
15786 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15787 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15788 GIR_EraseFromParent, /*InsnID*/0,
15789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15790 // GIR_Coverage, 1902,
15791 GIR_Done,
15792 // Label 909: @38585
15793 GIM_Try, /*On fail goto*//*Label 910*/ 38683, // Rule ID 2146 //
15794 GIM_CheckFeatures, GIFBS_IsThumb2,
15795 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
15796 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15797 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15798 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15800 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15801 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
15802 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15803 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15804 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
15805 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15806 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
15807 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
15808 // MIs[2] Operand 1
15809 // No operand predicates
15810 GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
15811 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
15812 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
15813 // MIs[3] Operand 1
15814 // No operand predicates
15815 GIM_CheckIsSafeToFold, /*InsnID*/1,
15816 GIM_CheckIsSafeToFold, /*InsnID*/2,
15817 GIM_CheckIsSafeToFold, /*InsnID*/3,
15818 // (intrinsic_wo_chain:{ *:[i32] } 2337:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
15819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
15820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15821 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
15822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
15823 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
15824 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15825 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15826 GIR_EraseFromParent, /*InsnID*/0,
15827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15828 // GIR_Coverage, 2146,
15829 GIR_Done,
15830 // Label 910: @38683
15831 GIM_Try, /*On fail goto*//*Label 911*/ 38767, // Rule ID 5303 //
15832 GIM_CheckFeatures, GIFBS_IsARM,
15833 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
15834 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15835 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15836 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15838 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15839 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
15840 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
15841 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
15842 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15843 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15844 // MIs[1] Rn
15845 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
15846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15847 GIM_CheckIsSafeToFold, /*InsnID*/1,
15848 // (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
15849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
15850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15853 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15854 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15855 GIR_EraseFromParent, /*InsnID*/0,
15856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15857 // GIR_Coverage, 5303,
15858 GIR_Done,
15859 // Label 911: @38767
15860 GIM_Try, /*On fail goto*//*Label 912*/ 38851, // Rule ID 5560 //
15861 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15862 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
15863 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15864 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15865 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15867 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15868 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
15869 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
15870 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
15871 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15872 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15873 // MIs[1] Rn
15874 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
15875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
15876 GIM_CheckIsSafeToFold, /*InsnID*/1,
15877 // (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
15878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
15879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
15881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15882 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15883 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15884 GIR_EraseFromParent, /*InsnID*/0,
15885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15886 // GIR_Coverage, 5560,
15887 GIR_Done,
15888 // Label 912: @38851
15889 GIM_Try, /*On fail goto*//*Label 913*/ 38935, // Rule ID 109 //
15890 GIM_CheckFeatures, GIFBS_IsARM,
15891 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
15892 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15893 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15894 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15897 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
15898 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
15899 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
15900 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
15901 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15902 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15903 // MIs[1] Rn
15904 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
15905 GIM_CheckIsSafeToFold, /*InsnID*/1,
15906 // (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
15907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
15908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
15910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15911 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15912 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15913 GIR_EraseFromParent, /*InsnID*/0,
15914 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15915 // GIR_Coverage, 109,
15916 GIR_Done,
15917 // Label 913: @38935
15918 GIM_Try, /*On fail goto*//*Label 914*/ 39019, // Rule ID 110 //
15919 GIM_CheckFeatures, GIFBS_IsARM,
15920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
15921 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15922 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15923 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15926 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
15927 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
15928 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
15929 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
15930 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15931 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15932 // MIs[1] Rn
15933 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
15934 GIM_CheckIsSafeToFold, /*InsnID*/1,
15935 // (intrinsic_wo_chain:{ *:[i32] } 2265:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
15936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
15937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
15939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15940 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15942 GIR_EraseFromParent, /*InsnID*/0,
15943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15944 // GIR_Coverage, 110,
15945 GIR_Done,
15946 // Label 914: @39019
15947 GIM_Try, /*On fail goto*//*Label 915*/ 39103, // Rule ID 2128 //
15948 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
15950 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15952 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15955 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
15956 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
15957 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
15958 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
15959 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15960 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15961 // MIs[1] Rn
15962 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
15963 GIM_CheckIsSafeToFold, /*InsnID*/1,
15964 // (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
15965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
15966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
15968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15969 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15970 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
15971 GIR_EraseFromParent, /*InsnID*/0,
15972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15973 // GIR_Coverage, 2128,
15974 GIR_Done,
15975 // Label 915: @39103
15976 GIM_Try, /*On fail goto*//*Label 916*/ 39187, // Rule ID 2129 //
15977 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
15978 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
15979 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
15980 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
15981 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
15982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
15983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
15985 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
15986 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
15987 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
15988 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15989 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
15990 // MIs[1] Rn
15991 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
15992 GIM_CheckIsSafeToFold, /*InsnID*/1,
15993 // (intrinsic_wo_chain:{ *:[i32] } 2265:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
15994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
15995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
15996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
15997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
15998 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15999 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16000 GIR_EraseFromParent, /*InsnID*/0,
16001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16002 // GIR_Coverage, 2129,
16003 GIR_Done,
16004 // Label 916: @39187
16005 GIM_Try, /*On fail goto*//*Label 917*/ 39256, // Rule ID 4004 //
16006 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16007 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16008 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16009 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16010 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16012 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16014 // (intrinsic_wo_chain:{ *:[v8i16] } 2018:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16015 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16016 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16017 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16a,
16019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16021 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16022 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16023 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16024 GIR_EraseFromParent, /*InsnID*/0,
16025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16026 // GIR_Coverage, 4004,
16027 GIR_Done,
16028 // Label 917: @39256
16029 GIM_Try, /*On fail goto*//*Label 918*/ 39325, // Rule ID 4006 //
16030 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16031 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16032 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16033 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16034 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16036 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16038 // (intrinsic_wo_chain:{ *:[v8i16] } 2022:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16039 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16040 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16041 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16n,
16043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16045 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16046 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16047 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16048 GIR_EraseFromParent, /*InsnID*/0,
16049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16050 // GIR_Coverage, 4006,
16051 GIR_Done,
16052 // Label 918: @39325
16053 GIM_Try, /*On fail goto*//*Label 919*/ 39394, // Rule ID 4008 //
16054 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16055 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16056 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16057 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16058 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16060 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16062 // (intrinsic_wo_chain:{ *:[v8i16] } 2024:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16063 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16064 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16065 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16p,
16067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16069 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16070 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16071 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16072 GIR_EraseFromParent, /*InsnID*/0,
16073 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16074 // GIR_Coverage, 4008,
16075 GIR_Done,
16076 // Label 919: @39394
16077 GIM_Try, /*On fail goto*//*Label 920*/ 39463, // Rule ID 4010 //
16078 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16079 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16080 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16081 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16082 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16084 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16086 // (intrinsic_wo_chain:{ *:[v8i16] } 2020:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16087 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16088 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16089 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16m,
16091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16093 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16094 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16095 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16096 GIR_EraseFromParent, /*InsnID*/0,
16097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16098 // GIR_Coverage, 4010,
16099 GIR_Done,
16100 // Label 920: @39463
16101 GIM_Try, /*On fail goto*//*Label 921*/ 39532, // Rule ID 4012 //
16102 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16104 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16105 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16106 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16108 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16110 // (intrinsic_wo_chain:{ *:[v8i16] } 2018:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16111 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16112 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16113 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16a,
16115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16117 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16118 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16119 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16120 GIR_EraseFromParent, /*InsnID*/0,
16121 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16122 // GIR_Coverage, 4012,
16123 GIR_Done,
16124 // Label 921: @39532
16125 GIM_Try, /*On fail goto*//*Label 922*/ 39601, // Rule ID 4014 //
16126 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16128 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16129 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16130 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16132 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16134 // (intrinsic_wo_chain:{ *:[v8i16] } 2022:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16135 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16137 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16n,
16139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16141 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16142 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16143 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16144 GIR_EraseFromParent, /*InsnID*/0,
16145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16146 // GIR_Coverage, 4014,
16147 GIR_Done,
16148 // Label 922: @39601
16149 GIM_Try, /*On fail goto*//*Label 923*/ 39670, // Rule ID 4016 //
16150 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16152 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16154 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16156 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16158 // (intrinsic_wo_chain:{ *:[v8i16] } 2024:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16159 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16160 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16161 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16p,
16163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16165 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16166 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16167 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16168 GIR_EraseFromParent, /*InsnID*/0,
16169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16170 // GIR_Coverage, 4016,
16171 GIR_Done,
16172 // Label 923: @39670
16173 GIM_Try, /*On fail goto*//*Label 924*/ 39739, // Rule ID 4018 //
16174 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16175 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16176 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16177 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16178 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16180 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16182 // (intrinsic_wo_chain:{ *:[v8i16] } 2020:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16183 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16184 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16185 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16m,
16187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16189 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16190 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16191 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16192 GIR_EraseFromParent, /*InsnID*/0,
16193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16194 // GIR_Coverage, 4018,
16195 GIR_Done,
16196 // Label 924: @39739
16197 GIM_Try, /*On fail goto*//*Label 925*/ 39808, // Rule ID 4020 //
16198 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16199 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16200 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16201 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16202 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16204 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16206 // (intrinsic_wo_chain:{ *:[v4i32] } 2018:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16207 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16208 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16209 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32a,
16211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16213 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16214 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16215 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16216 GIR_EraseFromParent, /*InsnID*/0,
16217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16218 // GIR_Coverage, 4020,
16219 GIR_Done,
16220 // Label 925: @39808
16221 GIM_Try, /*On fail goto*//*Label 926*/ 39877, // Rule ID 4022 //
16222 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16223 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16224 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16225 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16226 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16228 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16230 // (intrinsic_wo_chain:{ *:[v4i32] } 2022:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16231 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16232 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16233 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32n,
16235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16237 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16238 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16239 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16240 GIR_EraseFromParent, /*InsnID*/0,
16241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16242 // GIR_Coverage, 4022,
16243 GIR_Done,
16244 // Label 926: @39877
16245 GIM_Try, /*On fail goto*//*Label 927*/ 39946, // Rule ID 4024 //
16246 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16248 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16249 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16250 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16252 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16254 // (intrinsic_wo_chain:{ *:[v4i32] } 2024:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16255 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16256 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16257 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32p,
16259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16261 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16262 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16263 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16264 GIR_EraseFromParent, /*InsnID*/0,
16265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16266 // GIR_Coverage, 4024,
16267 GIR_Done,
16268 // Label 927: @39946
16269 GIM_Try, /*On fail goto*//*Label 928*/ 40015, // Rule ID 4026 //
16270 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16271 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16272 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16273 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16274 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16276 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
16277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16278 // (intrinsic_wo_chain:{ *:[v4i32] } 2020:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16279 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16280 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16281 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32m,
16283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16285 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16286 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16287 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16288 GIR_EraseFromParent, /*InsnID*/0,
16289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16290 // GIR_Coverage, 4026,
16291 GIR_Done,
16292 // Label 928: @40015
16293 GIM_Try, /*On fail goto*//*Label 929*/ 40084, // Rule ID 4028 //
16294 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16295 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvta,
16296 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16297 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16298 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16300 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16302 // (intrinsic_wo_chain:{ *:[v4i32] } 2018:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16303 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16304 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16305 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32a,
16307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16309 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16310 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16311 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16312 GIR_EraseFromParent, /*InsnID*/0,
16313 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16314 // GIR_Coverage, 4028,
16315 GIR_Done,
16316 // Label 929: @40084
16317 GIM_Try, /*On fail goto*//*Label 930*/ 40153, // Rule ID 4030 //
16318 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16319 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtn,
16320 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16321 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16322 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16324 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16326 // (intrinsic_wo_chain:{ *:[v4i32] } 2022:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16327 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16328 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16329 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32n,
16331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16333 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16334 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16335 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16336 GIR_EraseFromParent, /*InsnID*/0,
16337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16338 // GIR_Coverage, 4030,
16339 GIR_Done,
16340 // Label 930: @40153
16341 GIM_Try, /*On fail goto*//*Label 931*/ 40222, // Rule ID 4032 //
16342 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16343 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtp,
16344 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16345 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16346 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16348 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16350 // (intrinsic_wo_chain:{ *:[v4i32] } 2024:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16351 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16352 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16353 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32p,
16355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16357 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16358 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16359 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16360 GIR_EraseFromParent, /*InsnID*/0,
16361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16362 // GIR_Coverage, 4032,
16363 GIR_Done,
16364 // Label 931: @40222
16365 GIM_Try, /*On fail goto*//*Label 932*/ 40291, // Rule ID 4034 //
16366 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16367 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvtm,
16368 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16369 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16370 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16372 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
16373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
16374 // (intrinsic_wo_chain:{ *:[v4i32] } 2020:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16375 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16376 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16377 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32m,
16379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // in
16381 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16382 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16383 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16384 GIR_EraseFromParent, /*InsnID*/0,
16385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16386 // GIR_Coverage, 4034,
16387 GIR_Done,
16388 // Label 932: @40291
16389 GIM_Try, /*On fail goto*//*Label 933*/ 40360, // Rule ID 4452 //
16390 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16391 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_widen,
16392 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16393 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16394 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16397 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
16398 // (intrinsic_wo_chain:{ *:[v4f32] } 2016:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
16399 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16400 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16401 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32f16bh,
16403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
16405 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16406 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16407 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16408 GIR_EraseFromParent, /*InsnID*/0,
16409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16410 // GIR_Coverage, 4452,
16411 GIR_Done,
16412 // Label 933: @40360
16413 GIM_Try, /*On fail goto*//*Label 934*/ 40429, // Rule ID 4458 //
16414 GIM_CheckFeatures, GIFBS_HasMVEFloat,
16415 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_widen,
16416 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16417 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16418 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16421 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
16422 // (intrinsic_wo_chain:{ *:[v4f32] } 2016:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
16423 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16424 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16425 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32f16th,
16427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
16429 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16430 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16431 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16432 GIR_EraseFromParent, /*InsnID*/0,
16433 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16434 // GIR_Coverage, 4458,
16435 GIR_Done,
16436 // Label 934: @40429
16437 GIM_Try, /*On fail goto*//*Label 935*/ 40498, // Rule ID 1895 //
16438 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
16439 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
16440 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16441 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16442 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16445 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16446 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16447 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16448 // MIs[1] Operand 1
16449 // No operand predicates
16450 GIM_CheckIsSafeToFold, /*InsnID*/1,
16451 // (intrinsic_wo_chain:{ *:[i32] } 2337:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
16452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
16453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16454 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
16455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
16456 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16457 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16458 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16459 GIR_EraseFromParent, /*InsnID*/0,
16460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16461 // GIR_Coverage, 1895,
16462 GIR_Done,
16463 // Label 935: @40498
16464 GIM_Try, /*On fail goto*//*Label 936*/ 40564, // Rule ID 1899 //
16465 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
16466 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
16467 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16468 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16469 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
16471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
16472 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16473 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16474 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
16475 // MIs[1] Operand 1
16476 // No operand predicates
16477 GIM_CheckIsSafeToFold, /*InsnID*/1,
16478 // (intrinsic_wo_chain:{ *:[i32] } 2338:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
16479 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16,
16480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16481 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
16482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
16483 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16484 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16485 GIR_EraseFromParent, /*InsnID*/0,
16486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16487 // GIR_Coverage, 1899,
16488 GIR_Done,
16489 // Label 936: @40564
16490 GIM_Try, /*On fail goto*//*Label 937*/ 40633, // Rule ID 2141 //
16491 GIM_CheckFeatures, GIFBS_IsThumb2,
16492 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
16493 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16494 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16495 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
16498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16499 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16500 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16501 // MIs[1] Operand 1
16502 // No operand predicates
16503 GIM_CheckIsSafeToFold, /*InsnID*/1,
16504 // (intrinsic_wo_chain:{ *:[i32] } 2337:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
16505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
16506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16507 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
16508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
16509 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16510 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16511 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16512 GIR_EraseFromParent, /*InsnID*/0,
16513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16514 // GIR_Coverage, 2141,
16515 GIR_Done,
16516 // Label 937: @40633
16517 GIM_Try, /*On fail goto*//*Label 938*/ 40699, // Rule ID 2143 //
16518 GIM_CheckFeatures, GIFBS_IsThumb2,
16519 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
16520 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
16521 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
16522 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
16524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
16525 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16526 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16527 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
16528 // MIs[1] Operand 1
16529 // No operand predicates
16530 GIM_CheckIsSafeToFold, /*InsnID*/1,
16531 // (intrinsic_wo_chain:{ *:[i32] } 2338:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
16532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16,
16533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
16534 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
16535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
16536 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16537 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16538 GIR_EraseFromParent, /*InsnID*/0,
16539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16540 // GIR_Coverage, 2143,
16541 GIR_Done,
16542 // Label 938: @40699
16543 GIM_Try, /*On fail goto*//*Label 939*/ 40777, // Rule ID 3882 //
16544 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
16545 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16546 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16547 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16550 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16551 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16552 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
16553 // MIs[1] Operand 1
16554 // No operand predicates
16555 GIM_CheckIsSafeToFold, /*InsnID*/1,
16556 // (intrinsic_wo_chain:{ *:[v16i8] } 2077:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
16557 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16558 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16559 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms8,
16561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
16563 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16564 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16565 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16566 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16567 GIR_EraseFromParent, /*InsnID*/0,
16568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16569 // GIR_Coverage, 3882,
16570 GIR_Done,
16571 // Label 939: @40777
16572 GIM_Try, /*On fail goto*//*Label 940*/ 40855, // Rule ID 3884 //
16573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
16574 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16576 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16579 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16580 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16581 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
16582 // MIs[1] Operand 1
16583 // No operand predicates
16584 GIM_CheckIsSafeToFold, /*InsnID*/1,
16585 // (intrinsic_wo_chain:{ *:[v8i16] } 2077:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
16586 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16587 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16588 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms16,
16590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
16592 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16593 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16594 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16595 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16596 GIR_EraseFromParent, /*InsnID*/0,
16597 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16598 // GIR_Coverage, 3884,
16599 GIR_Done,
16600 // Label 940: @40855
16601 GIM_Try, /*On fail goto*//*Label 941*/ 40933, // Rule ID 3886 //
16602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshlu_imm,
16603 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16605 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
16607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
16608 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16609 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16610 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
16611 // MIs[1] Operand 1
16612 // No operand predicates
16613 GIM_CheckIsSafeToFold, /*InsnID*/1,
16614 // (intrinsic_wo_chain:{ *:[v4i32] } 2077:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
16615 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16616 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
16617 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
16618 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLU_imms32,
16619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
16620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
16621 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16622 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
16623 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16624 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
16625 GIR_EraseFromParent, /*InsnID*/0,
16626 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16627 // GIR_Coverage, 3886,
16628 GIR_Done,
16629 // Label 941: @40933
16630 GIM_Try, /*On fail goto*//*Label 942*/ 40996, // Rule ID 1668 //
16631 GIM_CheckFeatures, GIFBS_HasNEON,
16632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
16633 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16634 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16635 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16638 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16639 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16640 // MIs[1] Operand 1
16641 // No operand predicates
16642 GIM_CheckIsSafeToFold, /*InsnID*/1,
16643 // (intrinsic_wo_chain:{ *:[v2i32] } 2155:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd,
16645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16647 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16648 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16649 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16650 GIR_EraseFromParent, /*InsnID*/0,
16651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16652 // GIR_Coverage, 1668,
16653 GIR_Done,
16654 // Label 942: @40996
16655 GIM_Try, /*On fail goto*//*Label 943*/ 41059, // Rule ID 1669 //
16656 GIM_CheckFeatures, GIFBS_HasNEON,
16657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
16658 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16659 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16660 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16663 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16664 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16665 // MIs[1] Operand 1
16666 // No operand predicates
16667 GIM_CheckIsSafeToFold, /*InsnID*/1,
16668 // (intrinsic_wo_chain:{ *:[v2i32] } 2156:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud,
16670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16672 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16673 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16674 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16675 GIR_EraseFromParent, /*InsnID*/0,
16676 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16677 // GIR_Coverage, 1669,
16678 GIR_Done,
16679 // Label 943: @41059
16680 GIM_Try, /*On fail goto*//*Label 944*/ 41122, // Rule ID 1670 //
16681 GIM_CheckFeatures, GIFBS_HasNEON,
16682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
16683 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16684 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16685 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16688 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16689 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16690 // MIs[1] Operand 1
16691 // No operand predicates
16692 GIM_CheckIsSafeToFold, /*InsnID*/1,
16693 // (intrinsic_wo_chain:{ *:[v2f32] } 2158:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd,
16695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16697 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16698 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16699 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16700 GIR_EraseFromParent, /*InsnID*/0,
16701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16702 // GIR_Coverage, 1670,
16703 GIR_Done,
16704 // Label 944: @41122
16705 GIM_Try, /*On fail goto*//*Label 945*/ 41185, // Rule ID 1671 //
16706 GIM_CheckFeatures, GIFBS_HasNEON,
16707 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
16708 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16709 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16710 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16713 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16714 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16715 // MIs[1] Operand 1
16716 // No operand predicates
16717 GIM_CheckIsSafeToFold, /*InsnID*/1,
16718 // (intrinsic_wo_chain:{ *:[v2f32] } 2159:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd,
16720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16722 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16723 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16724 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16725 GIR_EraseFromParent, /*InsnID*/0,
16726 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16727 // GIR_Coverage, 1671,
16728 GIR_Done,
16729 // Label 945: @41185
16730 GIM_Try, /*On fail goto*//*Label 946*/ 41248, // Rule ID 1672 //
16731 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16732 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
16733 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16734 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16735 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16738 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16739 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16740 // MIs[1] Operand 1
16741 // No operand predicates
16742 GIM_CheckIsSafeToFold, /*InsnID*/1,
16743 // (intrinsic_wo_chain:{ *:[v4i16] } 2155:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd,
16745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16747 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16748 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16749 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16750 GIR_EraseFromParent, /*InsnID*/0,
16751 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16752 // GIR_Coverage, 1672,
16753 GIR_Done,
16754 // Label 946: @41248
16755 GIM_Try, /*On fail goto*//*Label 947*/ 41311, // Rule ID 1673 //
16756 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16757 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
16758 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16759 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16760 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16764 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16765 // MIs[1] Operand 1
16766 // No operand predicates
16767 GIM_CheckIsSafeToFold, /*InsnID*/1,
16768 // (intrinsic_wo_chain:{ *:[v4i16] } 2156:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud,
16770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16772 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16773 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16774 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16775 GIR_EraseFromParent, /*InsnID*/0,
16776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16777 // GIR_Coverage, 1673,
16778 GIR_Done,
16779 // Label 947: @41311
16780 GIM_Try, /*On fail goto*//*Label 948*/ 41374, // Rule ID 1674 //
16781 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16782 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
16783 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16784 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16785 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16789 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16790 // MIs[1] Operand 1
16791 // No operand predicates
16792 GIM_CheckIsSafeToFold, /*InsnID*/1,
16793 // (intrinsic_wo_chain:{ *:[v4f16] } 2158:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd,
16795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16797 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16798 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16799 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16800 GIR_EraseFromParent, /*InsnID*/0,
16801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16802 // GIR_Coverage, 1674,
16803 GIR_Done,
16804 // Label 948: @41374
16805 GIM_Try, /*On fail goto*//*Label 949*/ 41437, // Rule ID 1675 //
16806 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16807 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
16808 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16809 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16810 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16813 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16814 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16815 // MIs[1] Operand 1
16816 // No operand predicates
16817 GIM_CheckIsSafeToFold, /*InsnID*/1,
16818 // (intrinsic_wo_chain:{ *:[v4f16] } 2159:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd,
16820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16822 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16823 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16824 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16825 GIR_EraseFromParent, /*InsnID*/0,
16826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16827 // GIR_Coverage, 1675,
16828 GIR_Done,
16829 // Label 949: @41437
16830 GIM_Try, /*On fail goto*//*Label 950*/ 41500, // Rule ID 1676 //
16831 GIM_CheckFeatures, GIFBS_HasNEON,
16832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
16833 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16834 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16835 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16838 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16839 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16840 // MIs[1] Operand 1
16841 // No operand predicates
16842 GIM_CheckIsSafeToFold, /*InsnID*/1,
16843 // (intrinsic_wo_chain:{ *:[v4i32] } 2155:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq,
16845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16847 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16848 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16849 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16850 GIR_EraseFromParent, /*InsnID*/0,
16851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16852 // GIR_Coverage, 1676,
16853 GIR_Done,
16854 // Label 950: @41500
16855 GIM_Try, /*On fail goto*//*Label 951*/ 41563, // Rule ID 1677 //
16856 GIM_CheckFeatures, GIFBS_HasNEON,
16857 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
16858 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16859 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16860 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16863 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16864 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16865 // MIs[1] Operand 1
16866 // No operand predicates
16867 GIM_CheckIsSafeToFold, /*InsnID*/1,
16868 // (intrinsic_wo_chain:{ *:[v4i32] } 2156:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq,
16870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16872 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16873 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16874 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16875 GIR_EraseFromParent, /*InsnID*/0,
16876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16877 // GIR_Coverage, 1677,
16878 GIR_Done,
16879 // Label 951: @41563
16880 GIM_Try, /*On fail goto*//*Label 952*/ 41626, // Rule ID 1678 //
16881 GIM_CheckFeatures, GIFBS_HasNEON,
16882 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
16883 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16884 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16885 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16889 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16890 // MIs[1] Operand 1
16891 // No operand predicates
16892 GIM_CheckIsSafeToFold, /*InsnID*/1,
16893 // (intrinsic_wo_chain:{ *:[v4f32] } 2158:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq,
16895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16897 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16898 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16899 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16900 GIR_EraseFromParent, /*InsnID*/0,
16901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16902 // GIR_Coverage, 1678,
16903 GIR_Done,
16904 // Label 952: @41626
16905 GIM_Try, /*On fail goto*//*Label 953*/ 41689, // Rule ID 1679 //
16906 GIM_CheckFeatures, GIFBS_HasNEON,
16907 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
16908 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16909 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16910 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16914 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16915 // MIs[1] Operand 1
16916 // No operand predicates
16917 GIM_CheckIsSafeToFold, /*InsnID*/1,
16918 // (intrinsic_wo_chain:{ *:[v4f32] } 2159:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq,
16920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16922 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16923 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16924 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16925 GIR_EraseFromParent, /*InsnID*/0,
16926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16927 // GIR_Coverage, 1679,
16928 GIR_Done,
16929 // Label 953: @41689
16930 GIM_Try, /*On fail goto*//*Label 954*/ 41752, // Rule ID 1680 //
16931 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
16933 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16934 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16935 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16938 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16939 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16940 // MIs[1] Operand 1
16941 // No operand predicates
16942 GIM_CheckIsSafeToFold, /*InsnID*/1,
16943 // (intrinsic_wo_chain:{ *:[v8i16] } 2155:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq,
16945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16947 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16948 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16949 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16950 GIR_EraseFromParent, /*InsnID*/0,
16951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16952 // GIR_Coverage, 1680,
16953 GIR_Done,
16954 // Label 954: @41752
16955 GIM_Try, /*On fail goto*//*Label 955*/ 41815, // Rule ID 1681 //
16956 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16957 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
16958 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16959 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16960 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16963 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16964 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16965 // MIs[1] Operand 1
16966 // No operand predicates
16967 GIM_CheckIsSafeToFold, /*InsnID*/1,
16968 // (intrinsic_wo_chain:{ *:[v8i16] } 2156:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16969 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq,
16970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16972 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16973 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16974 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
16975 GIR_EraseFromParent, /*InsnID*/0,
16976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16977 // GIR_Coverage, 1681,
16978 GIR_Done,
16979 // Label 955: @41815
16980 GIM_Try, /*On fail goto*//*Label 956*/ 41878, // Rule ID 1682 //
16981 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
16983 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16984 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16985 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
16986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16988 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16989 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
16990 // MIs[1] Operand 1
16991 // No operand predicates
16992 GIM_CheckIsSafeToFold, /*InsnID*/1,
16993 // (intrinsic_wo_chain:{ *:[v8f16] } 2158:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
16994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq,
16995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16997 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
16998 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16999 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17000 GIR_EraseFromParent, /*InsnID*/0,
17001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17002 // GIR_Coverage, 1682,
17003 GIR_Done,
17004 // Label 956: @41878
17005 GIM_Try, /*On fail goto*//*Label 957*/ 41941, // Rule ID 1683 //
17006 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
17007 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
17008 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17009 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17010 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17013 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17014 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17015 // MIs[1] Operand 1
17016 // No operand predicates
17017 GIM_CheckIsSafeToFold, /*InsnID*/1,
17018 // (intrinsic_wo_chain:{ *:[v8f16] } 2159:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq,
17020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17022 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17023 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17024 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17025 GIR_EraseFromParent, /*InsnID*/0,
17026 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17027 // GIR_Coverage, 1683,
17028 GIR_Done,
17029 // Label 957: @41941
17030 GIM_Try, /*On fail goto*//*Label 958*/ 42004, // Rule ID 1746 //
17031 GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17032 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqshl,
17033 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17034 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17035 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17038 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17039 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17040 // MIs[1] Operand 1
17041 // No operand predicates
17042 GIM_CheckIsSafeToFold, /*InsnID*/1,
17043 // (intrinsic_wo_chain:{ *:[i32] } 1982:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQSHL,
17045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17047 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17048 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17049 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17050 GIR_EraseFromParent, /*InsnID*/0,
17051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17052 // GIR_Coverage, 1746,
17053 GIR_Done,
17054 // Label 958: @42004
17055 GIM_Try, /*On fail goto*//*Label 959*/ 42067, // Rule ID 1747 //
17056 GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_srshr,
17058 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17060 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17063 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17064 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17065 // MIs[1] Operand 1
17066 // No operand predicates
17067 GIM_CheckIsSafeToFold, /*InsnID*/1,
17068 // (intrinsic_wo_chain:{ *:[i32] } 1984:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SRSHR,
17070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17072 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17073 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17074 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17075 GIR_EraseFromParent, /*InsnID*/0,
17076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17077 // GIR_Coverage, 1747,
17078 GIR_Done,
17079 // Label 959: @42067
17080 GIM_Try, /*On fail goto*//*Label 960*/ 42130, // Rule ID 1748 //
17081 GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqshl,
17083 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17085 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17088 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17089 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17090 // MIs[1] Operand 1
17091 // No operand predicates
17092 GIM_CheckIsSafeToFold, /*InsnID*/1,
17093 // (intrinsic_wo_chain:{ *:[i32] } 1989:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQSHL,
17095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17097 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17098 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17099 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17100 GIR_EraseFromParent, /*InsnID*/0,
17101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17102 // GIR_Coverage, 1748,
17103 GIR_Done,
17104 // Label 960: @42130
17105 GIM_Try, /*On fail goto*//*Label 961*/ 42193, // Rule ID 1749 //
17106 GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
17107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_urshr,
17108 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17109 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17110 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17113 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17114 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
17115 // MIs[1] Operand 1
17116 // No operand predicates
17117 GIM_CheckIsSafeToFold, /*InsnID*/1,
17118 // (intrinsic_wo_chain:{ *:[i32] } 1991:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17119 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_URSHR,
17120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
17121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
17122 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17123 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17124 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17125 GIR_EraseFromParent, /*InsnID*/0,
17126 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17127 // GIR_Coverage, 1749,
17128 GIR_Done,
17129 // Label 961: @42193
17130 GIM_Try, /*On fail goto*//*Label 962*/ 42252, // Rule ID 105 //
17131 GIM_CheckFeatures, GIFBS_IsARM,
17132 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
17133 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17134 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17135 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17139 // (intrinsic_wo_chain:{ *:[i32] } 2262:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8,
17141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17144 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17145 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17146 GIR_EraseFromParent, /*InsnID*/0,
17147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17148 // GIR_Coverage, 105,
17149 GIR_Done,
17150 // Label 962: @42252
17151 GIM_Try, /*On fail goto*//*Label 963*/ 42311, // Rule ID 106 //
17152 GIM_CheckFeatures, GIFBS_IsARM,
17153 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
17154 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17155 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17156 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17160 // (intrinsic_wo_chain:{ *:[i32] } 2261:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16,
17162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17165 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17166 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17167 GIR_EraseFromParent, /*InsnID*/0,
17168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17169 // GIR_Coverage, 106,
17170 GIR_Done,
17171 // Label 963: @42311
17172 GIM_Try, /*On fail goto*//*Label 964*/ 42370, // Rule ID 107 //
17173 GIM_CheckFeatures, GIFBS_IsARM,
17174 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
17175 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17176 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17177 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17181 // (intrinsic_wo_chain:{ *:[i32] } 2266:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16,
17183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17186 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17187 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17188 GIR_EraseFromParent, /*InsnID*/0,
17189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17190 // GIR_Coverage, 107,
17191 GIR_Done,
17192 // Label 964: @42370
17193 GIM_Try, /*On fail goto*//*Label 965*/ 42429, // Rule ID 108 //
17194 GIM_CheckFeatures, GIFBS_IsARM,
17195 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
17196 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17197 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17198 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17202 // (intrinsic_wo_chain:{ *:[i32] } 2267:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8,
17204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17207 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17208 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17209 GIR_EraseFromParent, /*InsnID*/0,
17210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17211 // GIR_Coverage, 108,
17212 GIR_Done,
17213 // Label 965: @42429
17214 GIM_Try, /*On fail goto*//*Label 966*/ 42488, // Rule ID 111 //
17215 GIM_CheckFeatures, GIFBS_IsARM,
17216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
17217 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17218 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17219 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17223 // (intrinsic_wo_chain:{ *:[i32] } 2265:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
17225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
17227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
17228 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17229 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17230 GIR_EraseFromParent, /*InsnID*/0,
17231 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17232 // GIR_Coverage, 111,
17233 GIR_Done,
17234 // Label 966: @42488
17235 GIM_Try, /*On fail goto*//*Label 967*/ 42547, // Rule ID 112 //
17236 GIM_CheckFeatures, GIFBS_IsARM,
17237 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
17238 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17239 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17240 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17244 // (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
17246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
17248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
17249 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17250 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17251 GIR_EraseFromParent, /*InsnID*/0,
17252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17253 // GIR_Coverage, 112,
17254 GIR_Done,
17255 // Label 967: @42547
17256 GIM_Try, /*On fail goto*//*Label 968*/ 42606, // Rule ID 113 //
17257 GIM_CheckFeatures, GIFBS_IsARM,
17258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
17259 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17261 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17265 // (intrinsic_wo_chain:{ *:[i32] } 2329:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17266 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16,
17267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17270 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17271 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17272 GIR_EraseFromParent, /*InsnID*/0,
17273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17274 // GIR_Coverage, 113,
17275 GIR_Done,
17276 // Label 968: @42606
17277 GIM_Try, /*On fail goto*//*Label 969*/ 42665, // Rule ID 114 //
17278 GIM_CheckFeatures, GIFBS_IsARM,
17279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
17280 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17281 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17282 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17286 // (intrinsic_wo_chain:{ *:[i32] } 2330:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8,
17288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17291 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17292 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17293 GIR_EraseFromParent, /*InsnID*/0,
17294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17295 // GIR_Coverage, 114,
17296 GIR_Done,
17297 // Label 969: @42665
17298 GIM_Try, /*On fail goto*//*Label 970*/ 42724, // Rule ID 115 //
17299 GIM_CheckFeatures, GIFBS_IsARM,
17300 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
17301 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17302 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17303 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17307 // (intrinsic_wo_chain:{ *:[i32] } 2333:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16,
17309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17312 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17313 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17314 GIR_EraseFromParent, /*InsnID*/0,
17315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17316 // GIR_Coverage, 115,
17317 GIR_Done,
17318 // Label 970: @42724
17319 GIM_Try, /*On fail goto*//*Label 971*/ 42783, // Rule ID 116 //
17320 GIM_CheckFeatures, GIFBS_IsARM,
17321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
17322 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17323 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17324 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17328 // (intrinsic_wo_chain:{ *:[i32] } 2334:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8,
17330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17333 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17334 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17335 GIR_EraseFromParent, /*InsnID*/0,
17336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17337 // GIR_Coverage, 116,
17338 GIR_Done,
17339 // Label 971: @42783
17340 GIM_Try, /*On fail goto*//*Label 972*/ 42842, // Rule ID 117 //
17341 GIM_CheckFeatures, GIFBS_IsARM,
17342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
17343 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17344 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17345 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17349 // (intrinsic_wo_chain:{ *:[i32] } 2263:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX,
17351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17354 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17355 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17356 GIR_EraseFromParent, /*InsnID*/0,
17357 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17358 // GIR_Coverage, 117,
17359 GIR_Done,
17360 // Label 972: @42842
17361 GIM_Try, /*On fail goto*//*Label 973*/ 42901, // Rule ID 118 //
17362 GIM_CheckFeatures, GIFBS_IsARM,
17363 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
17364 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17366 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17370 // (intrinsic_wo_chain:{ *:[i32] } 2264:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX,
17372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17375 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17376 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17377 GIR_EraseFromParent, /*InsnID*/0,
17378 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17379 // GIR_Coverage, 118,
17380 GIR_Done,
17381 // Label 973: @42901
17382 GIM_Try, /*On fail goto*//*Label 974*/ 42960, // Rule ID 119 //
17383 GIM_CheckFeatures, GIFBS_IsARM,
17384 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
17385 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17387 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17391 // (intrinsic_wo_chain:{ *:[i32] } 2331:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX,
17393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17396 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17397 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17398 GIR_EraseFromParent, /*InsnID*/0,
17399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17400 // GIR_Coverage, 119,
17401 GIR_Done,
17402 // Label 974: @42960
17403 GIM_Try, /*On fail goto*//*Label 975*/ 43019, // Rule ID 120 //
17404 GIM_CheckFeatures, GIFBS_IsARM,
17405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
17406 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17407 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17408 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17412 // (intrinsic_wo_chain:{ *:[i32] } 2332:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX,
17414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17417 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17418 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17419 GIR_EraseFromParent, /*InsnID*/0,
17420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17421 // GIR_Coverage, 120,
17422 GIR_Done,
17423 // Label 975: @43019
17424 GIM_Try, /*On fail goto*//*Label 976*/ 43078, // Rule ID 133 //
17425 GIM_CheckFeatures, GIFBS_IsARM,
17426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
17427 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17429 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17433 // (intrinsic_wo_chain:{ *:[i32] } 2275:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17434 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX,
17435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17438 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17439 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17440 GIR_EraseFromParent, /*InsnID*/0,
17441 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17442 // GIR_Coverage, 133,
17443 GIR_Done,
17444 // Label 976: @43078
17445 GIM_Try, /*On fail goto*//*Label 977*/ 43137, // Rule ID 134 //
17446 GIM_CheckFeatures, GIFBS_IsARM,
17447 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
17448 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17449 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17450 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17454 // (intrinsic_wo_chain:{ *:[i32] } 2273:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16,
17456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17459 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17460 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17461 GIR_EraseFromParent, /*InsnID*/0,
17462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17463 // GIR_Coverage, 134,
17464 GIR_Done,
17465 // Label 977: @43137
17466 GIM_Try, /*On fail goto*//*Label 978*/ 43196, // Rule ID 135 //
17467 GIM_CheckFeatures, GIFBS_IsARM,
17468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
17469 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17471 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17475 // (intrinsic_wo_chain:{ *:[i32] } 2274:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8,
17477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17480 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17481 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17482 GIR_EraseFromParent, /*InsnID*/0,
17483 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17484 // GIR_Coverage, 135,
17485 GIR_Done,
17486 // Label 978: @43196
17487 GIM_Try, /*On fail goto*//*Label 979*/ 43255, // Rule ID 136 //
17488 GIM_CheckFeatures, GIFBS_IsARM,
17489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
17490 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17491 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17492 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17496 // (intrinsic_wo_chain:{ *:[i32] } 2276:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX,
17498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17501 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17502 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17503 GIR_EraseFromParent, /*InsnID*/0,
17504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17505 // GIR_Coverage, 136,
17506 GIR_Done,
17507 // Label 979: @43255
17508 GIM_Try, /*On fail goto*//*Label 980*/ 43314, // Rule ID 137 //
17509 GIM_CheckFeatures, GIFBS_IsARM,
17510 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
17511 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17512 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17513 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17517 // (intrinsic_wo_chain:{ *:[i32] } 2277:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16,
17519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17522 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17523 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17524 GIR_EraseFromParent, /*InsnID*/0,
17525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17526 // GIR_Coverage, 137,
17527 GIR_Done,
17528 // Label 980: @43314
17529 GIM_Try, /*On fail goto*//*Label 981*/ 43373, // Rule ID 138 //
17530 GIM_CheckFeatures, GIFBS_IsARM,
17531 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
17532 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17533 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17534 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17538 // (intrinsic_wo_chain:{ *:[i32] } 2278:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8,
17540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17543 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17544 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17545 GIR_EraseFromParent, /*InsnID*/0,
17546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17547 // GIR_Coverage, 138,
17548 GIR_Done,
17549 // Label 981: @43373
17550 GIM_Try, /*On fail goto*//*Label 982*/ 43432, // Rule ID 139 //
17551 GIM_CheckFeatures, GIFBS_IsARM,
17552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
17553 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17555 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17559 // (intrinsic_wo_chain:{ *:[i32] } 2324:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX,
17561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17564 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17565 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17566 GIR_EraseFromParent, /*InsnID*/0,
17567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17568 // GIR_Coverage, 139,
17569 GIR_Done,
17570 // Label 982: @43432
17571 GIM_Try, /*On fail goto*//*Label 983*/ 43491, // Rule ID 140 //
17572 GIM_CheckFeatures, GIFBS_IsARM,
17573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
17574 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17576 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17580 // (intrinsic_wo_chain:{ *:[i32] } 2322:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16,
17582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17585 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17586 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17587 GIR_EraseFromParent, /*InsnID*/0,
17588 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17589 // GIR_Coverage, 140,
17590 GIR_Done,
17591 // Label 983: @43491
17592 GIM_Try, /*On fail goto*//*Label 984*/ 43550, // Rule ID 141 //
17593 GIM_CheckFeatures, GIFBS_IsARM,
17594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
17595 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17596 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17597 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17601 // (intrinsic_wo_chain:{ *:[i32] } 2323:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8,
17603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17606 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17607 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17608 GIR_EraseFromParent, /*InsnID*/0,
17609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17610 // GIR_Coverage, 141,
17611 GIR_Done,
17612 // Label 984: @43550
17613 GIM_Try, /*On fail goto*//*Label 985*/ 43609, // Rule ID 142 //
17614 GIM_CheckFeatures, GIFBS_IsARM,
17615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
17616 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17617 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17618 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17622 // (intrinsic_wo_chain:{ *:[i32] } 2325:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX,
17624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17627 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17628 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17629 GIR_EraseFromParent, /*InsnID*/0,
17630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17631 // GIR_Coverage, 142,
17632 GIR_Done,
17633 // Label 985: @43609
17634 GIM_Try, /*On fail goto*//*Label 986*/ 43668, // Rule ID 143 //
17635 GIM_CheckFeatures, GIFBS_IsARM,
17636 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
17637 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17638 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17639 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17643 // (intrinsic_wo_chain:{ *:[i32] } 2326:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16,
17645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17648 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17649 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17650 GIR_EraseFromParent, /*InsnID*/0,
17651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17652 // GIR_Coverage, 143,
17653 GIR_Done,
17654 // Label 986: @43668
17655 GIM_Try, /*On fail goto*//*Label 987*/ 43727, // Rule ID 144 //
17656 GIM_CheckFeatures, GIFBS_IsARM,
17657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
17658 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17659 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17660 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17664 // (intrinsic_wo_chain:{ *:[i32] } 2327:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8,
17666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17669 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17670 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17671 GIR_EraseFromParent, /*InsnID*/0,
17672 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17673 // GIR_Coverage, 144,
17674 GIR_Done,
17675 // Label 987: @43727
17676 GIM_Try, /*On fail goto*//*Label 988*/ 43786, // Rule ID 145 //
17677 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
17678 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
17679 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17680 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17681 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
17683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
17684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
17685 // (intrinsic_wo_chain:{ *:[i32] } 2335:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
17686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8,
17687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17690 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17691 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17692 GIR_EraseFromParent, /*InsnID*/0,
17693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17694 // GIR_Coverage, 145,
17695 GIR_Done,
17696 // Label 988: @43786
17697 GIM_Try, /*On fail goto*//*Label 989*/ 43838, // Rule ID 204 //
17698 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
17699 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
17700 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17701 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17702 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17706 // (intrinsic_wo_chain:{ *:[i32] } 1896:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B,
17708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17711 GIR_EraseFromParent, /*InsnID*/0,
17712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17713 // GIR_Coverage, 204,
17714 GIR_Done,
17715 // Label 989: @43838
17716 GIM_Try, /*On fail goto*//*Label 990*/ 43890, // Rule ID 205 //
17717 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
17718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
17719 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17720 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17721 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17725 // (intrinsic_wo_chain:{ *:[i32] } 1897:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB,
17727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17730 GIR_EraseFromParent, /*InsnID*/0,
17731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17732 // GIR_Coverage, 205,
17733 GIR_Done,
17734 // Label 990: @43890
17735 GIM_Try, /*On fail goto*//*Label 991*/ 43942, // Rule ID 206 //
17736 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
17737 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
17738 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17739 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17740 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17744 // (intrinsic_wo_chain:{ *:[i32] } 1900:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H,
17746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17749 GIR_EraseFromParent, /*InsnID*/0,
17750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17751 // GIR_Coverage, 206,
17752 GIR_Done,
17753 // Label 991: @43942
17754 GIM_Try, /*On fail goto*//*Label 992*/ 43994, // Rule ID 207 //
17755 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
17756 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
17757 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17758 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17759 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17763 // (intrinsic_wo_chain:{ *:[i32] } 1898:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH,
17765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17768 GIR_EraseFromParent, /*InsnID*/0,
17769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17770 // GIR_Coverage, 207,
17771 GIR_Done,
17772 // Label 992: @43994
17773 GIM_Try, /*On fail goto*//*Label 993*/ 44046, // Rule ID 208 //
17774 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
17775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
17776 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17777 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17778 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17782 // (intrinsic_wo_chain:{ *:[i32] } 1901:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W,
17784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17787 GIR_EraseFromParent, /*InsnID*/0,
17788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17789 // GIR_Coverage, 208,
17790 GIR_Done,
17791 // Label 993: @44046
17792 GIM_Try, /*On fail goto*//*Label 994*/ 44098, // Rule ID 209 //
17793 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
17794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
17795 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17797 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
17801 // (intrinsic_wo_chain:{ *:[i32] } 1899:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW,
17803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17806 GIR_EraseFromParent, /*InsnID*/0,
17807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17808 // GIR_Coverage, 209,
17809 GIR_Done,
17810 // Label 994: @44098
17811 GIM_Try, /*On fail goto*//*Label 995*/ 44157, // Rule ID 439 //
17812 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17813 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
17814 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17815 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17816 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17820 // (intrinsic_wo_chain:{ *:[i32] } 2261:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16,
17822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17825 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17826 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17827 GIR_EraseFromParent, /*InsnID*/0,
17828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17829 // GIR_Coverage, 439,
17830 GIR_Done,
17831 // Label 995: @44157
17832 GIM_Try, /*On fail goto*//*Label 996*/ 44216, // Rule ID 440 //
17833 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
17835 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17836 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17837 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17841 // (intrinsic_wo_chain:{ *:[i32] } 2262:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8,
17843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17846 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17847 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17848 GIR_EraseFromParent, /*InsnID*/0,
17849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17850 // GIR_Coverage, 440,
17851 GIR_Done,
17852 // Label 996: @44216
17853 GIM_Try, /*On fail goto*//*Label 997*/ 44275, // Rule ID 441 //
17854 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
17856 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17857 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17858 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17862 // (intrinsic_wo_chain:{ *:[i32] } 2263:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX,
17864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17867 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17868 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17869 GIR_EraseFromParent, /*InsnID*/0,
17870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17871 // GIR_Coverage, 441,
17872 GIR_Done,
17873 // Label 997: @44275
17874 GIM_Try, /*On fail goto*//*Label 998*/ 44334, // Rule ID 442 //
17875 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
17877 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17878 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17879 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17883 // (intrinsic_wo_chain:{ *:[i32] } 2334:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8,
17885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17888 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17889 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17890 GIR_EraseFromParent, /*InsnID*/0,
17891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17892 // GIR_Coverage, 442,
17893 GIR_Done,
17894 // Label 998: @44334
17895 GIM_Try, /*On fail goto*//*Label 999*/ 44393, // Rule ID 443 //
17896 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17897 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
17898 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17899 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17900 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17904 // (intrinsic_wo_chain:{ *:[i32] } 2264:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX,
17906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17909 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17910 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17911 GIR_EraseFromParent, /*InsnID*/0,
17912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17913 // GIR_Coverage, 443,
17914 GIR_Done,
17915 // Label 999: @44393
17916 GIM_Try, /*On fail goto*//*Label 1000*/ 44452, // Rule ID 444 //
17917 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
17919 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17921 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17925 // (intrinsic_wo_chain:{ *:[i32] } 2266:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16,
17927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17930 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17931 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17932 GIR_EraseFromParent, /*InsnID*/0,
17933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17934 // GIR_Coverage, 444,
17935 GIR_Done,
17936 // Label 1000: @44452
17937 GIM_Try, /*On fail goto*//*Label 1001*/ 44511, // Rule ID 445 //
17938 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
17940 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17941 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17942 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17946 // (intrinsic_wo_chain:{ *:[i32] } 2267:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8,
17948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17951 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17952 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17953 GIR_EraseFromParent, /*InsnID*/0,
17954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17955 // GIR_Coverage, 445,
17956 GIR_Done,
17957 // Label 1001: @44511
17958 GIM_Try, /*On fail goto*//*Label 1002*/ 44570, // Rule ID 446 //
17959 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17960 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
17961 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17963 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17967 // (intrinsic_wo_chain:{ *:[i32] } 2329:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16,
17969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17972 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17973 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17974 GIR_EraseFromParent, /*InsnID*/0,
17975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17976 // GIR_Coverage, 446,
17977 GIR_Done,
17978 // Label 1002: @44570
17979 GIM_Try, /*On fail goto*//*Label 1003*/ 44629, // Rule ID 447 //
17980 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
17981 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
17982 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17983 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17984 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
17986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
17987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
17988 // (intrinsic_wo_chain:{ *:[i32] } 2330:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
17989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8,
17990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
17993 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17994 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
17995 GIR_EraseFromParent, /*InsnID*/0,
17996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17997 // GIR_Coverage, 447,
17998 GIR_Done,
17999 // Label 1003: @44629
18000 GIM_Try, /*On fail goto*//*Label 1004*/ 44688, // Rule ID 448 //
18001 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
18003 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18005 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18009 // (intrinsic_wo_chain:{ *:[i32] } 2331:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX,
18011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18014 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18015 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18016 GIR_EraseFromParent, /*InsnID*/0,
18017 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18018 // GIR_Coverage, 448,
18019 GIR_Done,
18020 // Label 1004: @44688
18021 GIM_Try, /*On fail goto*//*Label 1005*/ 44747, // Rule ID 449 //
18022 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18023 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
18024 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18025 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18026 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18030 // (intrinsic_wo_chain:{ *:[i32] } 2332:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX,
18032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18035 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18036 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18037 GIR_EraseFromParent, /*InsnID*/0,
18038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18039 // GIR_Coverage, 449,
18040 GIR_Done,
18041 // Label 1005: @44747
18042 GIM_Try, /*On fail goto*//*Label 1006*/ 44806, // Rule ID 450 //
18043 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
18045 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18046 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18047 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18051 // (intrinsic_wo_chain:{ *:[i32] } 2333:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16,
18053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18056 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18057 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18058 GIR_EraseFromParent, /*InsnID*/0,
18059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18060 // GIR_Coverage, 450,
18061 GIR_Done,
18062 // Label 1006: @44806
18063 GIM_Try, /*On fail goto*//*Label 1007*/ 44865, // Rule ID 463 //
18064 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18065 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
18066 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18067 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18068 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18072 // (intrinsic_wo_chain:{ *:[i32] } 2275:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX,
18074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18077 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18078 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18079 GIR_EraseFromParent, /*InsnID*/0,
18080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18081 // GIR_Coverage, 463,
18082 GIR_Done,
18083 // Label 1007: @44865
18084 GIM_Try, /*On fail goto*//*Label 1008*/ 44924, // Rule ID 464 //
18085 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18086 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
18087 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18088 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18089 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18093 // (intrinsic_wo_chain:{ *:[i32] } 2273:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18094 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16,
18095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18098 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18099 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18100 GIR_EraseFromParent, /*InsnID*/0,
18101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18102 // GIR_Coverage, 464,
18103 GIR_Done,
18104 // Label 1008: @44924
18105 GIM_Try, /*On fail goto*//*Label 1009*/ 44983, // Rule ID 465 //
18106 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18107 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
18108 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18109 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18110 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18114 // (intrinsic_wo_chain:{ *:[i32] } 2274:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8,
18116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18119 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18120 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18121 GIR_EraseFromParent, /*InsnID*/0,
18122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18123 // GIR_Coverage, 465,
18124 GIR_Done,
18125 // Label 1009: @44983
18126 GIM_Try, /*On fail goto*//*Label 1010*/ 45042, // Rule ID 466 //
18127 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
18129 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18131 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18135 // (intrinsic_wo_chain:{ *:[i32] } 2276:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX,
18137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18140 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18141 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18142 GIR_EraseFromParent, /*InsnID*/0,
18143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18144 // GIR_Coverage, 466,
18145 GIR_Done,
18146 // Label 1010: @45042
18147 GIM_Try, /*On fail goto*//*Label 1011*/ 45101, // Rule ID 467 //
18148 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18149 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
18150 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18151 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18152 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18156 // (intrinsic_wo_chain:{ *:[i32] } 2277:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16,
18158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18161 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18162 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18163 GIR_EraseFromParent, /*InsnID*/0,
18164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18165 // GIR_Coverage, 467,
18166 GIR_Done,
18167 // Label 1011: @45101
18168 GIM_Try, /*On fail goto*//*Label 1012*/ 45160, // Rule ID 468 //
18169 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18170 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
18171 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18173 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18177 // (intrinsic_wo_chain:{ *:[i32] } 2278:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8,
18179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18182 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18183 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18184 GIR_EraseFromParent, /*InsnID*/0,
18185 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18186 // GIR_Coverage, 468,
18187 GIR_Done,
18188 // Label 1012: @45160
18189 GIM_Try, /*On fail goto*//*Label 1013*/ 45219, // Rule ID 469 //
18190 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18191 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
18192 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18193 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18194 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18198 // (intrinsic_wo_chain:{ *:[i32] } 2324:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX,
18200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18203 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18204 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18205 GIR_EraseFromParent, /*InsnID*/0,
18206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18207 // GIR_Coverage, 469,
18208 GIR_Done,
18209 // Label 1013: @45219
18210 GIM_Try, /*On fail goto*//*Label 1014*/ 45278, // Rule ID 470 //
18211 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18212 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
18213 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18214 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18215 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18219 // (intrinsic_wo_chain:{ *:[i32] } 2322:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16,
18221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18224 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18225 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18226 GIR_EraseFromParent, /*InsnID*/0,
18227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18228 // GIR_Coverage, 470,
18229 GIR_Done,
18230 // Label 1014: @45278
18231 GIM_Try, /*On fail goto*//*Label 1015*/ 45337, // Rule ID 471 //
18232 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18233 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
18234 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18235 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18236 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18240 // (intrinsic_wo_chain:{ *:[i32] } 2323:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8,
18242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18245 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18246 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18247 GIR_EraseFromParent, /*InsnID*/0,
18248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18249 // GIR_Coverage, 471,
18250 GIR_Done,
18251 // Label 1015: @45337
18252 GIM_Try, /*On fail goto*//*Label 1016*/ 45396, // Rule ID 472 //
18253 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
18255 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18256 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18257 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18261 // (intrinsic_wo_chain:{ *:[i32] } 2325:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18262 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX,
18263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18266 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18267 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18268 GIR_EraseFromParent, /*InsnID*/0,
18269 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18270 // GIR_Coverage, 472,
18271 GIR_Done,
18272 // Label 1016: @45396
18273 GIM_Try, /*On fail goto*//*Label 1017*/ 45455, // Rule ID 473 //
18274 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18275 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
18276 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18277 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18278 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18282 // (intrinsic_wo_chain:{ *:[i32] } 2326:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16,
18284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18287 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18288 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18289 GIR_EraseFromParent, /*InsnID*/0,
18290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18291 // GIR_Coverage, 473,
18292 GIR_Done,
18293 // Label 1017: @45455
18294 GIM_Try, /*On fail goto*//*Label 1018*/ 45514, // Rule ID 474 //
18295 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18296 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
18297 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18298 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18299 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18303 // (intrinsic_wo_chain:{ *:[i32] } 2327:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8,
18305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18308 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18309 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18310 GIR_EraseFromParent, /*InsnID*/0,
18311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18312 // GIR_Coverage, 474,
18313 GIR_Done,
18314 // Label 1018: @45514
18315 GIM_Try, /*On fail goto*//*Label 1019*/ 45573, // Rule ID 475 //
18316 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
18318 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18319 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18320 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18324 // (intrinsic_wo_chain:{ *:[i32] } 2335:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8,
18326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18329 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18330 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18331 GIR_EraseFromParent, /*InsnID*/0,
18332 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18333 // GIR_Coverage, 475,
18334 GIR_Done,
18335 // Label 1019: @45573
18336 GIM_Try, /*On fail goto*//*Label 1020*/ 45632, // Rule ID 531 //
18337 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
18339 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18340 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18341 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18345 // (intrinsic_wo_chain:{ *:[i32] } 2293:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18346 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD,
18347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18350 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18351 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18352 GIR_EraseFromParent, /*InsnID*/0,
18353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18354 // GIR_Coverage, 531,
18355 GIR_Done,
18356 // Label 1020: @45632
18357 GIM_Try, /*On fail goto*//*Label 1021*/ 45691, // Rule ID 532 //
18358 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18359 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
18360 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18361 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18362 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18366 // (intrinsic_wo_chain:{ *:[i32] } 2294:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX,
18368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18371 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18372 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18373 GIR_EraseFromParent, /*InsnID*/0,
18374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18375 // GIR_Coverage, 532,
18376 GIR_Done,
18377 // Label 1021: @45691
18378 GIM_Try, /*On fail goto*//*Label 1022*/ 45750, // Rule ID 533 //
18379 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
18381 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18383 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18387 // (intrinsic_wo_chain:{ *:[i32] } 2301:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD,
18389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18392 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18393 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18394 GIR_EraseFromParent, /*InsnID*/0,
18395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18396 // GIR_Coverage, 533,
18397 GIR_Done,
18398 // Label 1022: @45750
18399 GIM_Try, /*On fail goto*//*Label 1023*/ 45809, // Rule ID 534 //
18400 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18401 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
18402 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18403 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18404 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18408 // (intrinsic_wo_chain:{ *:[i32] } 2302:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX,
18410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18413 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18414 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18415 GIR_EraseFromParent, /*InsnID*/0,
18416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18417 // GIR_Coverage, 534,
18418 GIR_Done,
18419 // Label 1023: @45809
18420 GIM_Try, /*On fail goto*//*Label 1024*/ 45861, // Rule ID 548 //
18421 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
18422 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
18423 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18424 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18425 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18429 // (intrinsic_wo_chain:{ *:[i32] } 1896:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B,
18431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18434 GIR_EraseFromParent, /*InsnID*/0,
18435 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18436 // GIR_Coverage, 548,
18437 GIR_Done,
18438 // Label 1024: @45861
18439 GIM_Try, /*On fail goto*//*Label 1025*/ 45913, // Rule ID 549 //
18440 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
18441 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
18442 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18444 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18448 // (intrinsic_wo_chain:{ *:[i32] } 1897:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18449 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB,
18450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18453 GIR_EraseFromParent, /*InsnID*/0,
18454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18455 // GIR_Coverage, 549,
18456 GIR_Done,
18457 // Label 1025: @45913
18458 GIM_Try, /*On fail goto*//*Label 1026*/ 45965, // Rule ID 550 //
18459 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
18460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
18461 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18462 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18463 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18467 // (intrinsic_wo_chain:{ *:[i32] } 1900:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18468 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H,
18469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18472 GIR_EraseFromParent, /*InsnID*/0,
18473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18474 // GIR_Coverage, 550,
18475 GIR_Done,
18476 // Label 1026: @45965
18477 GIM_Try, /*On fail goto*//*Label 1027*/ 46017, // Rule ID 551 //
18478 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
18479 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
18480 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18482 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18486 // (intrinsic_wo_chain:{ *:[i32] } 1898:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH,
18488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18491 GIR_EraseFromParent, /*InsnID*/0,
18492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18493 // GIR_Coverage, 551,
18494 GIR_Done,
18495 // Label 1027: @46017
18496 GIM_Try, /*On fail goto*//*Label 1028*/ 46069, // Rule ID 552 //
18497 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
18498 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
18499 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18500 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18501 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18505 // (intrinsic_wo_chain:{ *:[i32] } 1901:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W,
18507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18510 GIR_EraseFromParent, /*InsnID*/0,
18511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18512 // GIR_Coverage, 552,
18513 GIR_Done,
18514 // Label 1028: @46069
18515 GIM_Try, /*On fail goto*//*Label 1029*/ 46121, // Rule ID 553 //
18516 GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
18517 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
18518 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18519 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18520 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18524 // (intrinsic_wo_chain:{ *:[i32] } 1899:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW,
18526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18529 GIR_EraseFromParent, /*InsnID*/0,
18530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18531 // GIR_Coverage, 553,
18532 GIR_Done,
18533 // Label 1029: @46121
18534 GIM_Try, /*On fail goto*//*Label 1030*/ 46180, // Rule ID 806 //
18535 GIM_CheckFeatures, GIFBS_HasNEON,
18536 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
18537 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18538 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18539 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18543 // (intrinsic_wo_chain:{ *:[v4i16] } 2167:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16,
18545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18548 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18549 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18550 GIR_EraseFromParent, /*InsnID*/0,
18551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18552 // GIR_Coverage, 806,
18553 GIR_Done,
18554 // Label 1030: @46180
18555 GIM_Try, /*On fail goto*//*Label 1031*/ 46239, // Rule ID 807 //
18556 GIM_CheckFeatures, GIFBS_HasNEON,
18557 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
18558 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18559 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18560 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18564 // (intrinsic_wo_chain:{ *:[v2i32] } 2167:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32,
18566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18569 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18570 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18571 GIR_EraseFromParent, /*InsnID*/0,
18572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18573 // GIR_Coverage, 807,
18574 GIR_Done,
18575 // Label 1031: @46239
18576 GIM_Try, /*On fail goto*//*Label 1032*/ 46298, // Rule ID 808 //
18577 GIM_CheckFeatures, GIFBS_HasNEON,
18578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
18579 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18580 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18581 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18585 // (intrinsic_wo_chain:{ *:[v8i16] } 2167:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
18586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16,
18587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18590 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18591 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18592 GIR_EraseFromParent, /*InsnID*/0,
18593 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18594 // GIR_Coverage, 808,
18595 GIR_Done,
18596 // Label 1032: @46298
18597 GIM_Try, /*On fail goto*//*Label 1033*/ 46357, // Rule ID 809 //
18598 GIM_CheckFeatures, GIFBS_HasNEON,
18599 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
18600 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18601 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18602 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18606 // (intrinsic_wo_chain:{ *:[v4i32] } 2167:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32,
18608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18611 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18612 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18613 GIR_EraseFromParent, /*InsnID*/0,
18614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18615 // GIR_Coverage, 809,
18616 GIR_Done,
18617 // Label 1033: @46357
18618 GIM_Try, /*On fail goto*//*Label 1034*/ 46416, // Rule ID 810 //
18619 GIM_CheckFeatures, GIFBS_HasNEON,
18620 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
18621 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18622 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18623 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18627 // (intrinsic_wo_chain:{ *:[v8i8] } 2167:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8,
18629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18632 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18633 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18634 GIR_EraseFromParent, /*InsnID*/0,
18635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18636 // GIR_Coverage, 810,
18637 GIR_Done,
18638 // Label 1034: @46416
18639 GIM_Try, /*On fail goto*//*Label 1035*/ 46475, // Rule ID 811 //
18640 GIM_CheckFeatures, GIFBS_HasNEON,
18641 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
18642 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
18643 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
18644 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18648 // (intrinsic_wo_chain:{ *:[v16i8] } 2167:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
18649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8,
18650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18653 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18654 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18655 GIR_EraseFromParent, /*InsnID*/0,
18656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18657 // GIR_Coverage, 811,
18658 GIR_Done,
18659 // Label 1035: @46475
18660 GIM_Try, /*On fail goto*//*Label 1036*/ 46534, // Rule ID 812 //
18661 GIM_CheckFeatures, GIFBS_HasNEON,
18662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
18663 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18664 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18665 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18669 // (intrinsic_wo_chain:{ *:[v4i16] } 2168:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16,
18671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18674 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18675 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18676 GIR_EraseFromParent, /*InsnID*/0,
18677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18678 // GIR_Coverage, 812,
18679 GIR_Done,
18680 // Label 1036: @46534
18681 GIM_Try, /*On fail goto*//*Label 1037*/ 46593, // Rule ID 813 //
18682 GIM_CheckFeatures, GIFBS_HasNEON,
18683 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
18684 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18685 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18686 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18690 // (intrinsic_wo_chain:{ *:[v2i32] } 2168:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32,
18692 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18695 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18696 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18697 GIR_EraseFromParent, /*InsnID*/0,
18698 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18699 // GIR_Coverage, 813,
18700 GIR_Done,
18701 // Label 1037: @46593
18702 GIM_Try, /*On fail goto*//*Label 1038*/ 46652, // Rule ID 814 //
18703 GIM_CheckFeatures, GIFBS_HasNEON,
18704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
18705 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18706 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18707 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18711 // (intrinsic_wo_chain:{ *:[v8i16] } 2168:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
18712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16,
18713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18716 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18717 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18718 GIR_EraseFromParent, /*InsnID*/0,
18719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18720 // GIR_Coverage, 814,
18721 GIR_Done,
18722 // Label 1038: @46652
18723 GIM_Try, /*On fail goto*//*Label 1039*/ 46711, // Rule ID 815 //
18724 GIM_CheckFeatures, GIFBS_HasNEON,
18725 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
18726 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18727 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18728 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18732 // (intrinsic_wo_chain:{ *:[v4i32] } 2168:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32,
18734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18737 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18738 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18739 GIR_EraseFromParent, /*InsnID*/0,
18740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18741 // GIR_Coverage, 815,
18742 GIR_Done,
18743 // Label 1039: @46711
18744 GIM_Try, /*On fail goto*//*Label 1040*/ 46770, // Rule ID 816 //
18745 GIM_CheckFeatures, GIFBS_HasNEON,
18746 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
18747 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18748 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18749 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18753 // (intrinsic_wo_chain:{ *:[v8i8] } 2168:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8,
18755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18758 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18759 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18760 GIR_EraseFromParent, /*InsnID*/0,
18761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18762 // GIR_Coverage, 816,
18763 GIR_Done,
18764 // Label 1040: @46770
18765 GIM_Try, /*On fail goto*//*Label 1041*/ 46829, // Rule ID 817 //
18766 GIM_CheckFeatures, GIFBS_HasNEON,
18767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
18768 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
18769 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
18770 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18774 // (intrinsic_wo_chain:{ *:[v16i8] } 2168:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
18775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8,
18776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18779 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18780 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18781 GIR_EraseFromParent, /*InsnID*/0,
18782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18783 // GIR_Coverage, 817,
18784 GIR_Done,
18785 // Label 1041: @46829
18786 GIM_Try, /*On fail goto*//*Label 1042*/ 46888, // Rule ID 818 //
18787 GIM_CheckFeatures, GIFBS_HasNEON,
18788 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
18789 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18790 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18791 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18795 // (intrinsic_wo_chain:{ *:[v4i16] } 2225:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18796 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16,
18797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18800 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18801 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18802 GIR_EraseFromParent, /*InsnID*/0,
18803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18804 // GIR_Coverage, 818,
18805 GIR_Done,
18806 // Label 1042: @46888
18807 GIM_Try, /*On fail goto*//*Label 1043*/ 46947, // Rule ID 819 //
18808 GIM_CheckFeatures, GIFBS_HasNEON,
18809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
18810 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18812 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18816 // (intrinsic_wo_chain:{ *:[v2i32] } 2225:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32,
18818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18821 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18822 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18823 GIR_EraseFromParent, /*InsnID*/0,
18824 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18825 // GIR_Coverage, 819,
18826 GIR_Done,
18827 // Label 1043: @46947
18828 GIM_Try, /*On fail goto*//*Label 1044*/ 47006, // Rule ID 820 //
18829 GIM_CheckFeatures, GIFBS_HasNEON,
18830 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
18831 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18832 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18833 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18837 // (intrinsic_wo_chain:{ *:[v8i16] } 2225:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
18838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16,
18839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18842 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18843 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18844 GIR_EraseFromParent, /*InsnID*/0,
18845 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18846 // GIR_Coverage, 820,
18847 GIR_Done,
18848 // Label 1044: @47006
18849 GIM_Try, /*On fail goto*//*Label 1045*/ 47065, // Rule ID 821 //
18850 GIM_CheckFeatures, GIFBS_HasNEON,
18851 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
18852 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18853 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18854 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18858 // (intrinsic_wo_chain:{ *:[v4i32] } 2225:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32,
18860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18863 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18864 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18865 GIR_EraseFromParent, /*InsnID*/0,
18866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18867 // GIR_Coverage, 821,
18868 GIR_Done,
18869 // Label 1045: @47065
18870 GIM_Try, /*On fail goto*//*Label 1046*/ 47124, // Rule ID 822 //
18871 GIM_CheckFeatures, GIFBS_HasNEON,
18872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
18873 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18874 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18875 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18879 // (intrinsic_wo_chain:{ *:[v8i8] } 2225:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8,
18881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18884 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18885 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18886 GIR_EraseFromParent, /*InsnID*/0,
18887 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18888 // GIR_Coverage, 822,
18889 GIR_Done,
18890 // Label 1046: @47124
18891 GIM_Try, /*On fail goto*//*Label 1047*/ 47183, // Rule ID 823 //
18892 GIM_CheckFeatures, GIFBS_HasNEON,
18893 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
18894 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
18895 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
18896 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18900 // (intrinsic_wo_chain:{ *:[v16i8] } 2225:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
18901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8,
18902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18905 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18906 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18907 GIR_EraseFromParent, /*InsnID*/0,
18908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18909 // GIR_Coverage, 823,
18910 GIR_Done,
18911 // Label 1047: @47183
18912 GIM_Try, /*On fail goto*//*Label 1048*/ 47242, // Rule ID 824 //
18913 GIM_CheckFeatures, GIFBS_HasNEON,
18914 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
18915 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
18916 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
18917 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
18918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18921 // (intrinsic_wo_chain:{ *:[v4i16] } 2226:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
18922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16,
18923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18926 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18927 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18928 GIR_EraseFromParent, /*InsnID*/0,
18929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18930 // GIR_Coverage, 824,
18931 GIR_Done,
18932 // Label 1048: @47242
18933 GIM_Try, /*On fail goto*//*Label 1049*/ 47301, // Rule ID 825 //
18934 GIM_CheckFeatures, GIFBS_HasNEON,
18935 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
18936 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18937 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18938 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
18939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18942 // (intrinsic_wo_chain:{ *:[v2i32] } 2226:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
18943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32,
18944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18947 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18948 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18949 GIR_EraseFromParent, /*InsnID*/0,
18950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18951 // GIR_Coverage, 825,
18952 GIR_Done,
18953 // Label 1049: @47301
18954 GIM_Try, /*On fail goto*//*Label 1050*/ 47360, // Rule ID 826 //
18955 GIM_CheckFeatures, GIFBS_HasNEON,
18956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
18957 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
18958 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
18959 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
18960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18963 // (intrinsic_wo_chain:{ *:[v8i16] } 2226:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
18964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16,
18965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18968 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18969 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18970 GIR_EraseFromParent, /*InsnID*/0,
18971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18972 // GIR_Coverage, 826,
18973 GIR_Done,
18974 // Label 1050: @47360
18975 GIM_Try, /*On fail goto*//*Label 1051*/ 47419, // Rule ID 827 //
18976 GIM_CheckFeatures, GIFBS_HasNEON,
18977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
18978 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18979 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18980 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18984 // (intrinsic_wo_chain:{ *:[v4i32] } 2226:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32,
18986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
18988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
18989 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18990 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
18991 GIR_EraseFromParent, /*InsnID*/0,
18992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18993 // GIR_Coverage, 827,
18994 GIR_Done,
18995 // Label 1051: @47419
18996 GIM_Try, /*On fail goto*//*Label 1052*/ 47478, // Rule ID 828 //
18997 GIM_CheckFeatures, GIFBS_HasNEON,
18998 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
18999 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19000 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19001 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19005 // (intrinsic_wo_chain:{ *:[v8i8] } 2226:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8,
19007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19010 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19011 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19012 GIR_EraseFromParent, /*InsnID*/0,
19013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19014 // GIR_Coverage, 828,
19015 GIR_Done,
19016 // Label 1052: @47478
19017 GIM_Try, /*On fail goto*//*Label 1053*/ 47537, // Rule ID 829 //
19018 GIM_CheckFeatures, GIFBS_HasNEON,
19019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
19020 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19021 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19022 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19026 // (intrinsic_wo_chain:{ *:[v16i8] } 2226:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8,
19028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19031 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19032 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19033 GIR_EraseFromParent, /*InsnID*/0,
19034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19035 // GIR_Coverage, 829,
19036 GIR_Done,
19037 // Label 1053: @47537
19038 GIM_Try, /*On fail goto*//*Label 1054*/ 47596, // Rule ID 846 //
19039 GIM_CheckFeatures, GIFBS_HasNEON,
19040 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
19041 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19042 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19043 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19047 // (intrinsic_wo_chain:{ *:[v8i8] } 2222:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8,
19049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19052 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19053 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19054 GIR_EraseFromParent, /*InsnID*/0,
19055 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19056 // GIR_Coverage, 846,
19057 GIR_Done,
19058 // Label 1054: @47596
19059 GIM_Try, /*On fail goto*//*Label 1055*/ 47655, // Rule ID 847 //
19060 GIM_CheckFeatures, GIFBS_HasNEON,
19061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
19062 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19063 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19064 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19068 // (intrinsic_wo_chain:{ *:[v4i16] } 2222:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16,
19070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19073 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19074 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19075 GIR_EraseFromParent, /*InsnID*/0,
19076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19077 // GIR_Coverage, 847,
19078 GIR_Done,
19079 // Label 1055: @47655
19080 GIM_Try, /*On fail goto*//*Label 1056*/ 47714, // Rule ID 848 //
19081 GIM_CheckFeatures, GIFBS_HasNEON,
19082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
19083 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19085 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19089 // (intrinsic_wo_chain:{ *:[v2i32] } 2222:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32,
19091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19094 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19095 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19096 GIR_EraseFromParent, /*InsnID*/0,
19097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19098 // GIR_Coverage, 848,
19099 GIR_Done,
19100 // Label 1056: @47714
19101 GIM_Try, /*On fail goto*//*Label 1057*/ 47773, // Rule ID 855 //
19102 GIM_CheckFeatures, GIFBS_HasNEON,
19103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
19104 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19105 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19106 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19110 // (intrinsic_wo_chain:{ *:[v8i8] } 2193:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd,
19112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19115 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19116 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19117 GIR_EraseFromParent, /*InsnID*/0,
19118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19119 // GIR_Coverage, 855,
19120 GIR_Done,
19121 // Label 1057: @47773
19122 GIM_Try, /*On fail goto*//*Label 1058*/ 47832, // Rule ID 856 //
19123 GIM_CheckFeatures, GIFBS_HasNEON,
19124 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
19125 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19126 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19127 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19131 // (intrinsic_wo_chain:{ *:[v16i8] } 2193:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq,
19133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19136 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19137 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19138 GIR_EraseFromParent, /*InsnID*/0,
19139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19140 // GIR_Coverage, 856,
19141 GIR_Done,
19142 // Label 1058: @47832
19143 GIM_Try, /*On fail goto*//*Label 1059*/ 47891, // Rule ID 869 //
19144 GIM_CheckFeatures, GIFBS_HasNEON,
19145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19146 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19147 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19148 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19152 // (intrinsic_wo_chain:{ *:[v4i16] } 2204:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16,
19154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19157 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19158 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19159 GIR_EraseFromParent, /*InsnID*/0,
19160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19161 // GIR_Coverage, 869,
19162 GIR_Done,
19163 // Label 1059: @47891
19164 GIM_Try, /*On fail goto*//*Label 1060*/ 47950, // Rule ID 870 //
19165 GIM_CheckFeatures, GIFBS_HasNEON,
19166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19167 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19168 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19169 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19173 // (intrinsic_wo_chain:{ *:[v2i32] } 2204:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19174 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32,
19175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19178 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19179 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19180 GIR_EraseFromParent, /*InsnID*/0,
19181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19182 // GIR_Coverage, 870,
19183 GIR_Done,
19184 // Label 1060: @47950
19185 GIM_Try, /*On fail goto*//*Label 1061*/ 48009, // Rule ID 871 //
19186 GIM_CheckFeatures, GIFBS_HasNEON,
19187 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19188 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19189 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19190 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19194 // (intrinsic_wo_chain:{ *:[v8i16] } 2204:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16,
19196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19199 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19200 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19201 GIR_EraseFromParent, /*InsnID*/0,
19202 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19203 // GIR_Coverage, 871,
19204 GIR_Done,
19205 // Label 1061: @48009
19206 GIM_Try, /*On fail goto*//*Label 1062*/ 48068, // Rule ID 872 //
19207 GIM_CheckFeatures, GIFBS_HasNEON,
19208 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
19209 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19210 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19211 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19215 // (intrinsic_wo_chain:{ *:[v4i32] } 2204:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32,
19217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19220 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19221 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19222 GIR_EraseFromParent, /*InsnID*/0,
19223 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19224 // GIR_Coverage, 872,
19225 GIR_Done,
19226 // Label 1062: @48068
19227 GIM_Try, /*On fail goto*//*Label 1063*/ 48127, // Rule ID 877 //
19228 GIM_CheckFeatures, GIFBS_HasNEON,
19229 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19230 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19231 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19232 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19236 // (intrinsic_wo_chain:{ *:[v4i16] } 2210:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16,
19238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19241 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19242 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19243 GIR_EraseFromParent, /*InsnID*/0,
19244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19245 // GIR_Coverage, 877,
19246 GIR_Done,
19247 // Label 1063: @48127
19248 GIM_Try, /*On fail goto*//*Label 1064*/ 48186, // Rule ID 878 //
19249 GIM_CheckFeatures, GIFBS_HasNEON,
19250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19251 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19252 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19253 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19257 // (intrinsic_wo_chain:{ *:[v2i32] } 2210:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32,
19259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19262 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19263 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19264 GIR_EraseFromParent, /*InsnID*/0,
19265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19266 // GIR_Coverage, 878,
19267 GIR_Done,
19268 // Label 1064: @48186
19269 GIM_Try, /*On fail goto*//*Label 1065*/ 48245, // Rule ID 879 //
19270 GIM_CheckFeatures, GIFBS_HasNEON,
19271 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19272 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19273 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19274 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19278 // (intrinsic_wo_chain:{ *:[v8i16] } 2210:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16,
19280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19283 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19284 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19285 GIR_EraseFromParent, /*InsnID*/0,
19286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19287 // GIR_Coverage, 879,
19288 GIR_Done,
19289 // Label 1065: @48245
19290 GIM_Try, /*On fail goto*//*Label 1066*/ 48304, // Rule ID 880 //
19291 GIM_CheckFeatures, GIFBS_HasNEON,
19292 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
19293 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19295 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19299 // (intrinsic_wo_chain:{ *:[v4i32] } 2210:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32,
19301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19304 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19305 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19306 GIR_EraseFromParent, /*InsnID*/0,
19307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19308 // GIR_Coverage, 880,
19309 GIR_Done,
19310 // Label 1066: @48304
19311 GIM_Try, /*On fail goto*//*Label 1067*/ 48363, // Rule ID 891 //
19312 GIM_CheckFeatures, GIFBS_HasNEON,
19313 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
19314 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19315 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19316 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19320 // (intrinsic_wo_chain:{ *:[v8i16] } 2190:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8,
19322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19325 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19326 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19327 GIR_EraseFromParent, /*InsnID*/0,
19328 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19329 // GIR_Coverage, 891,
19330 GIR_Done,
19331 // Label 1067: @48363
19332 GIM_Try, /*On fail goto*//*Label 1068*/ 48415, // Rule ID 892 //
19333 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
19334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
19335 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19336 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19337 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19341 // (intrinsic_wo_chain:{ *:[v2i64] } 2190:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
19342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64,
19343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19346 GIR_EraseFromParent, /*InsnID*/0,
19347 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19348 // GIR_Coverage, 892,
19349 GIR_Done,
19350 // Label 1068: @48415
19351 GIM_Try, /*On fail goto*//*Label 1069*/ 48474, // Rule ID 897 //
19352 GIM_CheckFeatures, GIFBS_HasNEON,
19353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
19354 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19355 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19356 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19360 // (intrinsic_wo_chain:{ *:[v4i32] } 2205:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32,
19362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19365 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19366 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19367 GIR_EraseFromParent, /*InsnID*/0,
19368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19369 // GIR_Coverage, 897,
19370 GIR_Done,
19371 // Label 1069: @48474
19372 GIM_Try, /*On fail goto*//*Label 1070*/ 48533, // Rule ID 898 //
19373 GIM_CheckFeatures, GIFBS_HasNEON,
19374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
19375 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19377 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19381 // (intrinsic_wo_chain:{ *:[v2i64] } 2205:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19382 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64,
19383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19386 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19387 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19388 GIR_EraseFromParent, /*InsnID*/0,
19389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19390 // GIR_Coverage, 898,
19391 GIR_Done,
19392 // Label 1070: @48533
19393 GIM_Try, /*On fail goto*//*Label 1071*/ 48592, // Rule ID 1010 //
19394 GIM_CheckFeatures, GIFBS_HasNEON,
19395 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
19396 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19397 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19398 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19402 // (intrinsic_wo_chain:{ *:[v4i16] } 2169:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16,
19404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19407 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19408 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19409 GIR_EraseFromParent, /*InsnID*/0,
19410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19411 // GIR_Coverage, 1010,
19412 GIR_Done,
19413 // Label 1071: @48592
19414 GIM_Try, /*On fail goto*//*Label 1072*/ 48651, // Rule ID 1011 //
19415 GIM_CheckFeatures, GIFBS_HasNEON,
19416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
19417 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19418 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19419 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19423 // (intrinsic_wo_chain:{ *:[v2i32] } 2169:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32,
19425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19428 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19429 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19430 GIR_EraseFromParent, /*InsnID*/0,
19431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19432 // GIR_Coverage, 1011,
19433 GIR_Done,
19434 // Label 1072: @48651
19435 GIM_Try, /*On fail goto*//*Label 1073*/ 48710, // Rule ID 1012 //
19436 GIM_CheckFeatures, GIFBS_HasNEON,
19437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
19438 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19439 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19440 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19444 // (intrinsic_wo_chain:{ *:[v8i16] } 2169:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16,
19446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19449 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19450 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19451 GIR_EraseFromParent, /*InsnID*/0,
19452 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19453 // GIR_Coverage, 1012,
19454 GIR_Done,
19455 // Label 1073: @48710
19456 GIM_Try, /*On fail goto*//*Label 1074*/ 48769, // Rule ID 1013 //
19457 GIM_CheckFeatures, GIFBS_HasNEON,
19458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
19459 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19460 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19461 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19465 // (intrinsic_wo_chain:{ *:[v4i32] } 2169:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32,
19467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19470 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19471 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19472 GIR_EraseFromParent, /*InsnID*/0,
19473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19474 // GIR_Coverage, 1013,
19475 GIR_Done,
19476 // Label 1074: @48769
19477 GIM_Try, /*On fail goto*//*Label 1075*/ 48828, // Rule ID 1014 //
19478 GIM_CheckFeatures, GIFBS_HasNEON,
19479 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
19480 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19482 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19486 // (intrinsic_wo_chain:{ *:[v8i8] } 2169:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8,
19488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19491 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19492 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19493 GIR_EraseFromParent, /*InsnID*/0,
19494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19495 // GIR_Coverage, 1014,
19496 GIR_Done,
19497 // Label 1075: @48828
19498 GIM_Try, /*On fail goto*//*Label 1076*/ 48887, // Rule ID 1015 //
19499 GIM_CheckFeatures, GIFBS_HasNEON,
19500 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
19501 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19502 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19503 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19507 // (intrinsic_wo_chain:{ *:[v16i8] } 2169:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8,
19509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19512 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19513 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19514 GIR_EraseFromParent, /*InsnID*/0,
19515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19516 // GIR_Coverage, 1015,
19517 GIR_Done,
19518 // Label 1076: @48887
19519 GIM_Try, /*On fail goto*//*Label 1077*/ 48946, // Rule ID 1016 //
19520 GIM_CheckFeatures, GIFBS_HasNEON,
19521 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
19522 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19523 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19524 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19528 // (intrinsic_wo_chain:{ *:[v4i16] } 2170:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16,
19530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19533 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19534 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19535 GIR_EraseFromParent, /*InsnID*/0,
19536 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19537 // GIR_Coverage, 1016,
19538 GIR_Done,
19539 // Label 1077: @48946
19540 GIM_Try, /*On fail goto*//*Label 1078*/ 49005, // Rule ID 1017 //
19541 GIM_CheckFeatures, GIFBS_HasNEON,
19542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
19543 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19544 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19545 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19549 // (intrinsic_wo_chain:{ *:[v2i32] } 2170:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32,
19551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19554 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19555 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19556 GIR_EraseFromParent, /*InsnID*/0,
19557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19558 // GIR_Coverage, 1017,
19559 GIR_Done,
19560 // Label 1078: @49005
19561 GIM_Try, /*On fail goto*//*Label 1079*/ 49064, // Rule ID 1018 //
19562 GIM_CheckFeatures, GIFBS_HasNEON,
19563 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
19564 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19565 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19566 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19570 // (intrinsic_wo_chain:{ *:[v8i16] } 2170:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16,
19572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19575 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19576 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19577 GIR_EraseFromParent, /*InsnID*/0,
19578 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19579 // GIR_Coverage, 1018,
19580 GIR_Done,
19581 // Label 1079: @49064
19582 GIM_Try, /*On fail goto*//*Label 1080*/ 49123, // Rule ID 1019 //
19583 GIM_CheckFeatures, GIFBS_HasNEON,
19584 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
19585 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19586 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19587 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19591 // (intrinsic_wo_chain:{ *:[v4i32] } 2170:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32,
19593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19596 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19597 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19598 GIR_EraseFromParent, /*InsnID*/0,
19599 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19600 // GIR_Coverage, 1019,
19601 GIR_Done,
19602 // Label 1080: @49123
19603 GIM_Try, /*On fail goto*//*Label 1081*/ 49182, // Rule ID 1020 //
19604 GIM_CheckFeatures, GIFBS_HasNEON,
19605 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
19606 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19607 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19608 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19612 // (intrinsic_wo_chain:{ *:[v8i8] } 2170:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8,
19614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19617 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19618 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19619 GIR_EraseFromParent, /*InsnID*/0,
19620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19621 // GIR_Coverage, 1020,
19622 GIR_Done,
19623 // Label 1081: @49182
19624 GIM_Try, /*On fail goto*//*Label 1082*/ 49241, // Rule ID 1021 //
19625 GIM_CheckFeatures, GIFBS_HasNEON,
19626 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
19627 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19628 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19629 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19633 // (intrinsic_wo_chain:{ *:[v16i8] } 2170:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8,
19635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19638 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19639 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19640 GIR_EraseFromParent, /*InsnID*/0,
19641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19642 // GIR_Coverage, 1021,
19643 GIR_Done,
19644 // Label 1082: @49241
19645 GIM_Try, /*On fail goto*//*Label 1083*/ 49300, // Rule ID 1038 //
19646 GIM_CheckFeatures, GIFBS_HasNEON,
19647 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
19648 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19649 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19650 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19654 // (intrinsic_wo_chain:{ *:[v8i8] } 2238:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19655 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8,
19656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19659 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19660 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19661 GIR_EraseFromParent, /*InsnID*/0,
19662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19663 // GIR_Coverage, 1038,
19664 GIR_Done,
19665 // Label 1083: @49300
19666 GIM_Try, /*On fail goto*//*Label 1084*/ 49359, // Rule ID 1039 //
19667 GIM_CheckFeatures, GIFBS_HasNEON,
19668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
19669 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19671 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19675 // (intrinsic_wo_chain:{ *:[v4i16] } 2238:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16,
19677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19680 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19681 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19682 GIR_EraseFromParent, /*InsnID*/0,
19683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19684 // GIR_Coverage, 1039,
19685 GIR_Done,
19686 // Label 1084: @49359
19687 GIM_Try, /*On fail goto*//*Label 1085*/ 49418, // Rule ID 1040 //
19688 GIM_CheckFeatures, GIFBS_HasNEON,
19689 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
19690 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19691 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19692 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19696 // (intrinsic_wo_chain:{ *:[v2i32] } 2238:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32,
19698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19701 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19702 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19703 GIR_EraseFromParent, /*InsnID*/0,
19704 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19705 // GIR_Coverage, 1040,
19706 GIR_Done,
19707 // Label 1085: @49418
19708 GIM_Try, /*On fail goto*//*Label 1086*/ 49477, // Rule ID 1133 //
19709 GIM_CheckFeatures, GIFBS_HasNEON,
19710 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
19711 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19712 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19713 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19717 // (intrinsic_wo_chain:{ *:[v2i32] } 2145:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
19718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd,
19719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19722 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19723 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19724 GIR_EraseFromParent, /*InsnID*/0,
19725 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19726 // GIR_Coverage, 1133,
19727 GIR_Done,
19728 // Label 1086: @49477
19729 GIM_Try, /*On fail goto*//*Label 1087*/ 49536, // Rule ID 1134 //
19730 GIM_CheckFeatures, GIFBS_HasNEON,
19731 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
19732 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19733 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19734 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19738 // (intrinsic_wo_chain:{ *:[v4i32] } 2145:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
19739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq,
19740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19743 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19744 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19745 GIR_EraseFromParent, /*InsnID*/0,
19746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19747 // GIR_Coverage, 1134,
19748 GIR_Done,
19749 // Label 1087: @49536
19750 GIM_Try, /*On fail goto*//*Label 1088*/ 49595, // Rule ID 1135 //
19751 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
19752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
19753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19755 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19759 // (intrinsic_wo_chain:{ *:[v4i16] } 2145:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
19760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd,
19761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19764 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19765 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19766 GIR_EraseFromParent, /*InsnID*/0,
19767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19768 // GIR_Coverage, 1135,
19769 GIR_Done,
19770 // Label 1088: @49595
19771 GIM_Try, /*On fail goto*//*Label 1089*/ 49654, // Rule ID 1136 //
19772 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
19773 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
19774 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19775 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19776 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19780 // (intrinsic_wo_chain:{ *:[v8i16] } 2145:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
19781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq,
19782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19785 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19786 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19787 GIR_EraseFromParent, /*InsnID*/0,
19788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19789 // GIR_Coverage, 1136,
19790 GIR_Done,
19791 // Label 1089: @49654
19792 GIM_Try, /*On fail goto*//*Label 1090*/ 49713, // Rule ID 1137 //
19793 GIM_CheckFeatures, GIFBS_HasNEON,
19794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
19795 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19797 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19801 // (intrinsic_wo_chain:{ *:[v2i32] } 2146:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
19802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd,
19803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19806 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19807 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19808 GIR_EraseFromParent, /*InsnID*/0,
19809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19810 // GIR_Coverage, 1137,
19811 GIR_Done,
19812 // Label 1090: @49713
19813 GIM_Try, /*On fail goto*//*Label 1091*/ 49772, // Rule ID 1138 //
19814 GIM_CheckFeatures, GIFBS_HasNEON,
19815 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
19816 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19817 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19818 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19822 // (intrinsic_wo_chain:{ *:[v4i32] } 2146:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
19823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq,
19824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19827 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19828 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19829 GIR_EraseFromParent, /*InsnID*/0,
19830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19831 // GIR_Coverage, 1138,
19832 GIR_Done,
19833 // Label 1091: @49772
19834 GIM_Try, /*On fail goto*//*Label 1092*/ 49831, // Rule ID 1139 //
19835 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
19836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
19837 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19838 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19839 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19843 // (intrinsic_wo_chain:{ *:[v4i16] } 2146:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
19844 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd,
19845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19848 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19849 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19850 GIR_EraseFromParent, /*InsnID*/0,
19851 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19852 // GIR_Coverage, 1139,
19853 GIR_Done,
19854 // Label 1092: @49831
19855 GIM_Try, /*On fail goto*//*Label 1093*/ 49890, // Rule ID 1140 //
19856 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
19857 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
19858 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19859 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19860 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19864 // (intrinsic_wo_chain:{ *:[v8i16] } 2146:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
19865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq,
19866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19869 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19870 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19871 GIR_EraseFromParent, /*InsnID*/0,
19872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19873 // GIR_Coverage, 1140,
19874 GIR_Done,
19875 // Label 1093: @49890
19876 GIM_Try, /*On fail goto*//*Label 1094*/ 49949, // Rule ID 1173 //
19877 GIM_CheckFeatures, GIFBS_HasNEON,
19878 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
19879 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19880 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19881 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19885 // (intrinsic_wo_chain:{ *:[v4i16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16,
19887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19890 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19891 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19892 GIR_EraseFromParent, /*InsnID*/0,
19893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19894 // GIR_Coverage, 1173,
19895 GIR_Done,
19896 // Label 1094: @49949
19897 GIM_Try, /*On fail goto*//*Label 1095*/ 50008, // Rule ID 1174 //
19898 GIM_CheckFeatures, GIFBS_HasNEON,
19899 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
19900 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19902 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19906 // (intrinsic_wo_chain:{ *:[v2i32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32,
19908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19911 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19912 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19913 GIR_EraseFromParent, /*InsnID*/0,
19914 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19915 // GIR_Coverage, 1174,
19916 GIR_Done,
19917 // Label 1095: @50008
19918 GIM_Try, /*On fail goto*//*Label 1096*/ 50067, // Rule ID 1175 //
19919 GIM_CheckFeatures, GIFBS_HasNEON,
19920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
19921 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19922 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19923 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19927 // (intrinsic_wo_chain:{ *:[v8i16] } 2142:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16,
19929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19932 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19933 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19934 GIR_EraseFromParent, /*InsnID*/0,
19935 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19936 // GIR_Coverage, 1175,
19937 GIR_Done,
19938 // Label 1096: @50067
19939 GIM_Try, /*On fail goto*//*Label 1097*/ 50126, // Rule ID 1176 //
19940 GIM_CheckFeatures, GIFBS_HasNEON,
19941 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
19942 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19943 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19944 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19948 // (intrinsic_wo_chain:{ *:[v4i32] } 2142:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32,
19950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19953 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19954 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19955 GIR_EraseFromParent, /*InsnID*/0,
19956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19957 // GIR_Coverage, 1176,
19958 GIR_Done,
19959 // Label 1097: @50126
19960 GIM_Try, /*On fail goto*//*Label 1098*/ 50185, // Rule ID 1177 //
19961 GIM_CheckFeatures, GIFBS_HasNEON,
19962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
19963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19965 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19969 // (intrinsic_wo_chain:{ *:[v8i8] } 2142:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8,
19971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19974 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19975 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19976 GIR_EraseFromParent, /*InsnID*/0,
19977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19978 // GIR_Coverage, 1177,
19979 GIR_Done,
19980 // Label 1098: @50185
19981 GIM_Try, /*On fail goto*//*Label 1099*/ 50244, // Rule ID 1178 //
19982 GIM_CheckFeatures, GIFBS_HasNEON,
19983 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
19984 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19985 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19986 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19990 // (intrinsic_wo_chain:{ *:[v16i8] } 2142:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8,
19992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
19994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
19995 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19996 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
19997 GIR_EraseFromParent, /*InsnID*/0,
19998 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19999 // GIR_Coverage, 1178,
20000 GIR_Done,
20001 // Label 1099: @50244
20002 GIM_Try, /*On fail goto*//*Label 1100*/ 50303, // Rule ID 1179 //
20003 GIM_CheckFeatures, GIFBS_HasNEON,
20004 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20005 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20006 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20007 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20011 // (intrinsic_wo_chain:{ *:[v4i16] } 2143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16,
20013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20016 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20017 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20018 GIR_EraseFromParent, /*InsnID*/0,
20019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20020 // GIR_Coverage, 1179,
20021 GIR_Done,
20022 // Label 1100: @50303
20023 GIM_Try, /*On fail goto*//*Label 1101*/ 50362, // Rule ID 1180 //
20024 GIM_CheckFeatures, GIFBS_HasNEON,
20025 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20026 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20027 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20028 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20032 // (intrinsic_wo_chain:{ *:[v2i32] } 2143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32,
20034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20037 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20038 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20039 GIR_EraseFromParent, /*InsnID*/0,
20040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20041 // GIR_Coverage, 1180,
20042 GIR_Done,
20043 // Label 1101: @50362
20044 GIM_Try, /*On fail goto*//*Label 1102*/ 50421, // Rule ID 1181 //
20045 GIM_CheckFeatures, GIFBS_HasNEON,
20046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20047 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20048 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20049 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20053 // (intrinsic_wo_chain:{ *:[v8i16] } 2143:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16,
20055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20058 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20059 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20060 GIR_EraseFromParent, /*InsnID*/0,
20061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20062 // GIR_Coverage, 1181,
20063 GIR_Done,
20064 // Label 1102: @50421
20065 GIM_Try, /*On fail goto*//*Label 1103*/ 50480, // Rule ID 1182 //
20066 GIM_CheckFeatures, GIFBS_HasNEON,
20067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20068 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20069 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20070 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20074 // (intrinsic_wo_chain:{ *:[v4i32] } 2143:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32,
20076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20079 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20080 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20081 GIR_EraseFromParent, /*InsnID*/0,
20082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20083 // GIR_Coverage, 1182,
20084 GIR_Done,
20085 // Label 1103: @50480
20086 GIM_Try, /*On fail goto*//*Label 1104*/ 50539, // Rule ID 1183 //
20087 GIM_CheckFeatures, GIFBS_HasNEON,
20088 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20089 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20090 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20091 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20095 // (intrinsic_wo_chain:{ *:[v8i8] } 2143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8,
20097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20100 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20101 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20102 GIR_EraseFromParent, /*InsnID*/0,
20103 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20104 // GIR_Coverage, 1183,
20105 GIR_Done,
20106 // Label 1104: @50539
20107 GIM_Try, /*On fail goto*//*Label 1105*/ 50598, // Rule ID 1184 //
20108 GIM_CheckFeatures, GIFBS_HasNEON,
20109 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
20110 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
20111 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
20112 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20116 // (intrinsic_wo_chain:{ *:[v16i8] } 2143:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8,
20118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20121 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20122 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20123 GIR_EraseFromParent, /*InsnID*/0,
20124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20125 // GIR_Coverage, 1184,
20126 GIR_Done,
20127 // Label 1105: @50598
20128 GIM_Try, /*On fail goto*//*Label 1106*/ 50657, // Rule ID 1185 //
20129 GIM_CheckFeatures, GIFBS_HasNEON,
20130 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20131 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20132 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20133 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20137 // (intrinsic_wo_chain:{ *:[v2f32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd,
20139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20142 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20143 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20144 GIR_EraseFromParent, /*InsnID*/0,
20145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20146 // GIR_Coverage, 1185,
20147 GIR_Done,
20148 // Label 1106: @50657
20149 GIM_Try, /*On fail goto*//*Label 1107*/ 50716, // Rule ID 1186 //
20150 GIM_CheckFeatures, GIFBS_HasNEON,
20151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20152 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20154 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20158 // (intrinsic_wo_chain:{ *:[v4f32] } 2142:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq,
20160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20163 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20164 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20165 GIR_EraseFromParent, /*InsnID*/0,
20166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20167 // GIR_Coverage, 1186,
20168 GIR_Done,
20169 // Label 1107: @50716
20170 GIM_Try, /*On fail goto*//*Label 1108*/ 50775, // Rule ID 1187 //
20171 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20173 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20175 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20179 // (intrinsic_wo_chain:{ *:[v4f16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd,
20181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20184 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20185 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20186 GIR_EraseFromParent, /*InsnID*/0,
20187 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20188 // GIR_Coverage, 1187,
20189 GIR_Done,
20190 // Label 1108: @50775
20191 GIM_Try, /*On fail goto*//*Label 1109*/ 50834, // Rule ID 1188 //
20192 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20193 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
20194 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20195 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20196 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20200 // (intrinsic_wo_chain:{ *:[v8f16] } 2142:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq,
20202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20205 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20206 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20207 GIR_EraseFromParent, /*InsnID*/0,
20208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20209 // GIR_Coverage, 1188,
20210 GIR_Done,
20211 // Label 1109: @50834
20212 GIM_Try, /*On fail goto*//*Label 1110*/ 50893, // Rule ID 1253 //
20213 GIM_CheckFeatures, GIFBS_HasNEON,
20214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20215 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20217 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20221 // (intrinsic_wo_chain:{ *:[v8i8] } 2196:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8,
20223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20226 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20227 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20228 GIR_EraseFromParent, /*InsnID*/0,
20229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20230 // GIR_Coverage, 1253,
20231 GIR_Done,
20232 // Label 1110: @50893
20233 GIM_Try, /*On fail goto*//*Label 1111*/ 50952, // Rule ID 1254 //
20234 GIM_CheckFeatures, GIFBS_HasNEON,
20235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20236 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20237 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20238 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20242 // (intrinsic_wo_chain:{ *:[v4i16] } 2196:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16,
20244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20247 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20248 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20249 GIR_EraseFromParent, /*InsnID*/0,
20250 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20251 // GIR_Coverage, 1254,
20252 GIR_Done,
20253 // Label 1111: @50952
20254 GIM_Try, /*On fail goto*//*Label 1112*/ 51011, // Rule ID 1255 //
20255 GIM_CheckFeatures, GIFBS_HasNEON,
20256 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20257 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20258 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20259 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20263 // (intrinsic_wo_chain:{ *:[v2i32] } 2196:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32,
20265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20268 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20269 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20270 GIR_EraseFromParent, /*InsnID*/0,
20271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20272 // GIR_Coverage, 1255,
20273 GIR_Done,
20274 // Label 1112: @51011
20275 GIM_Try, /*On fail goto*//*Label 1113*/ 51070, // Rule ID 1256 //
20276 GIM_CheckFeatures, GIFBS_HasNEON,
20277 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20278 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20279 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20280 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20284 // (intrinsic_wo_chain:{ *:[v2f32] } 2196:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf,
20286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20289 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20290 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20291 GIR_EraseFromParent, /*InsnID*/0,
20292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20293 // GIR_Coverage, 1256,
20294 GIR_Done,
20295 // Label 1113: @51070
20296 GIM_Try, /*On fail goto*//*Label 1114*/ 51129, // Rule ID 1257 //
20297 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
20299 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20301 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20305 // (intrinsic_wo_chain:{ *:[v4f16] } 2196:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh,
20307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20310 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20311 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20312 GIR_EraseFromParent, /*InsnID*/0,
20313 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20314 // GIR_Coverage, 1257,
20315 GIR_Done,
20316 // Label 1114: @51129
20317 GIM_Try, /*On fail goto*//*Label 1115*/ 51188, // Rule ID 1270 //
20318 GIM_CheckFeatures, GIFBS_HasNEON,
20319 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20320 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20321 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20322 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20326 // (intrinsic_wo_chain:{ *:[v4i16] } 2194:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8,
20328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20331 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20332 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20333 GIR_EraseFromParent, /*InsnID*/0,
20334 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20335 // GIR_Coverage, 1270,
20336 GIR_Done,
20337 // Label 1115: @51188
20338 GIM_Try, /*On fail goto*//*Label 1116*/ 51247, // Rule ID 1271 //
20339 GIM_CheckFeatures, GIFBS_HasNEON,
20340 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20341 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20342 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20343 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20347 // (intrinsic_wo_chain:{ *:[v2i32] } 2194:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16,
20349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20352 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20353 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20354 GIR_EraseFromParent, /*InsnID*/0,
20355 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20356 // GIR_Coverage, 1271,
20357 GIR_Done,
20358 // Label 1116: @51247
20359 GIM_Try, /*On fail goto*//*Label 1117*/ 51306, // Rule ID 1272 //
20360 GIM_CheckFeatures, GIFBS_HasNEON,
20361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20362 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
20363 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20364 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20368 // (intrinsic_wo_chain:{ *:[v1i64] } 2194:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
20369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32,
20370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20373 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20374 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20375 GIR_EraseFromParent, /*InsnID*/0,
20376 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20377 // GIR_Coverage, 1272,
20378 GIR_Done,
20379 // Label 1117: @51306
20380 GIM_Try, /*On fail goto*//*Label 1118*/ 51365, // Rule ID 1273 //
20381 GIM_CheckFeatures, GIFBS_HasNEON,
20382 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20383 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20384 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20385 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20389 // (intrinsic_wo_chain:{ *:[v8i16] } 2194:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
20390 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8,
20391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20394 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20395 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20396 GIR_EraseFromParent, /*InsnID*/0,
20397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20398 // GIR_Coverage, 1273,
20399 GIR_Done,
20400 // Label 1118: @51365
20401 GIM_Try, /*On fail goto*//*Label 1119*/ 51424, // Rule ID 1274 //
20402 GIM_CheckFeatures, GIFBS_HasNEON,
20403 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20404 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20405 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20406 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20410 // (intrinsic_wo_chain:{ *:[v4i32] } 2194:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
20411 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16,
20412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20415 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20416 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20417 GIR_EraseFromParent, /*InsnID*/0,
20418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20419 // GIR_Coverage, 1274,
20420 GIR_Done,
20421 // Label 1119: @51424
20422 GIM_Try, /*On fail goto*//*Label 1120*/ 51483, // Rule ID 1275 //
20423 GIM_CheckFeatures, GIFBS_HasNEON,
20424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
20425 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20426 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
20427 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20431 // (intrinsic_wo_chain:{ *:[v2i64] } 2194:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
20432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32,
20433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20436 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20437 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20438 GIR_EraseFromParent, /*InsnID*/0,
20439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20440 // GIR_Coverage, 1275,
20441 GIR_Done,
20442 // Label 1120: @51483
20443 GIM_Try, /*On fail goto*//*Label 1121*/ 51542, // Rule ID 1276 //
20444 GIM_CheckFeatures, GIFBS_HasNEON,
20445 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
20446 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20447 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20448 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20452 // (intrinsic_wo_chain:{ *:[v4i16] } 2195:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20453 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8,
20454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20457 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20458 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20459 GIR_EraseFromParent, /*InsnID*/0,
20460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20461 // GIR_Coverage, 1276,
20462 GIR_Done,
20463 // Label 1121: @51542
20464 GIM_Try, /*On fail goto*//*Label 1122*/ 51601, // Rule ID 1277 //
20465 GIM_CheckFeatures, GIFBS_HasNEON,
20466 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
20467 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20468 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20469 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20473 // (intrinsic_wo_chain:{ *:[v2i32] } 2195:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16,
20475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20478 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20479 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20480 GIR_EraseFromParent, /*InsnID*/0,
20481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20482 // GIR_Coverage, 1277,
20483 GIR_Done,
20484 // Label 1122: @51601
20485 GIM_Try, /*On fail goto*//*Label 1123*/ 51660, // Rule ID 1278 //
20486 GIM_CheckFeatures, GIFBS_HasNEON,
20487 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
20488 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
20489 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
20490 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20494 // (intrinsic_wo_chain:{ *:[v1i64] } 2195:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
20495 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32,
20496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20499 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20500 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20501 GIR_EraseFromParent, /*InsnID*/0,
20502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20503 // GIR_Coverage, 1278,
20504 GIR_Done,
20505 // Label 1123: @51660
20506 GIM_Try, /*On fail goto*//*Label 1124*/ 51719, // Rule ID 1279 //
20507 GIM_CheckFeatures, GIFBS_HasNEON,
20508 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
20509 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20510 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20511 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
20512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20515 // (intrinsic_wo_chain:{ *:[v8i16] } 2195:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
20516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8,
20517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20520 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20521 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20522 GIR_EraseFromParent, /*InsnID*/0,
20523 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20524 // GIR_Coverage, 1279,
20525 GIR_Done,
20526 // Label 1124: @51719
20527 GIM_Try, /*On fail goto*//*Label 1125*/ 51778, // Rule ID 1280 //
20528 GIM_CheckFeatures, GIFBS_HasNEON,
20529 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
20530 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20531 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20532 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20536 // (intrinsic_wo_chain:{ *:[v4i32] } 2195:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
20537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16,
20538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20541 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20542 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20543 GIR_EraseFromParent, /*InsnID*/0,
20544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20545 // GIR_Coverage, 1280,
20546 GIR_Done,
20547 // Label 1125: @51778
20548 GIM_Try, /*On fail goto*//*Label 1126*/ 51837, // Rule ID 1281 //
20549 GIM_CheckFeatures, GIFBS_HasNEON,
20550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
20551 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
20552 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
20553 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20557 // (intrinsic_wo_chain:{ *:[v2i64] } 2195:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
20558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32,
20559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
20561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20562 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20563 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20564 GIR_EraseFromParent, /*InsnID*/0,
20565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20566 // GIR_Coverage, 1281,
20567 GIR_Done,
20568 // Label 1126: @51837
20569 GIM_Try, /*On fail goto*//*Label 1127*/ 51896, // Rule ID 1282 //
20570 GIM_CheckFeatures, GIFBS_HasNEON,
20571 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
20572 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20573 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20574 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20578 // (intrinsic_wo_chain:{ *:[v8i8] } 2199:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20579 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8,
20580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20583 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20584 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20585 GIR_EraseFromParent, /*InsnID*/0,
20586 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20587 // GIR_Coverage, 1282,
20588 GIR_Done,
20589 // Label 1127: @51896
20590 GIM_Try, /*On fail goto*//*Label 1128*/ 51955, // Rule ID 1283 //
20591 GIM_CheckFeatures, GIFBS_HasNEON,
20592 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
20593 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20594 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20595 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20599 // (intrinsic_wo_chain:{ *:[v4i16] } 2199:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16,
20601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20604 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20605 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20606 GIR_EraseFromParent, /*InsnID*/0,
20607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20608 // GIR_Coverage, 1283,
20609 GIR_Done,
20610 // Label 1128: @51955
20611 GIM_Try, /*On fail goto*//*Label 1129*/ 52014, // Rule ID 1284 //
20612 GIM_CheckFeatures, GIFBS_HasNEON,
20613 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
20614 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20615 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20616 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20620 // (intrinsic_wo_chain:{ *:[v2i32] } 2199:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32,
20622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20625 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20626 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20627 GIR_EraseFromParent, /*InsnID*/0,
20628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20629 // GIR_Coverage, 1284,
20630 GIR_Done,
20631 // Label 1129: @52014
20632 GIM_Try, /*On fail goto*//*Label 1130*/ 52073, // Rule ID 1285 //
20633 GIM_CheckFeatures, GIFBS_HasNEON,
20634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
20635 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20637 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20641 // (intrinsic_wo_chain:{ *:[v8i8] } 2200:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8,
20643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20646 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20647 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20648 GIR_EraseFromParent, /*InsnID*/0,
20649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20650 // GIR_Coverage, 1285,
20651 GIR_Done,
20652 // Label 1130: @52073
20653 GIM_Try, /*On fail goto*//*Label 1131*/ 52132, // Rule ID 1286 //
20654 GIM_CheckFeatures, GIFBS_HasNEON,
20655 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
20656 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20657 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20658 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20662 // (intrinsic_wo_chain:{ *:[v4i16] } 2200:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16,
20664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20667 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20668 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20669 GIR_EraseFromParent, /*InsnID*/0,
20670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20671 // GIR_Coverage, 1286,
20672 GIR_Done,
20673 // Label 1131: @52132
20674 GIM_Try, /*On fail goto*//*Label 1132*/ 52191, // Rule ID 1287 //
20675 GIM_CheckFeatures, GIFBS_HasNEON,
20676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
20677 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20678 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20679 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20683 // (intrinsic_wo_chain:{ *:[v2i32] } 2200:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32,
20685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20688 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20689 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20690 GIR_EraseFromParent, /*InsnID*/0,
20691 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20692 // GIR_Coverage, 1287,
20693 GIR_Done,
20694 // Label 1132: @52191
20695 GIM_Try, /*On fail goto*//*Label 1133*/ 52250, // Rule ID 1288 //
20696 GIM_CheckFeatures, GIFBS_HasNEON,
20697 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
20698 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20699 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20700 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20704 // (intrinsic_wo_chain:{ *:[v2f32] } 2199:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf,
20706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20709 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20710 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20711 GIR_EraseFromParent, /*InsnID*/0,
20712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20713 // GIR_Coverage, 1288,
20714 GIR_Done,
20715 // Label 1133: @52250
20716 GIM_Try, /*On fail goto*//*Label 1134*/ 52309, // Rule ID 1289 //
20717 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
20719 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20720 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20721 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20725 // (intrinsic_wo_chain:{ *:[v4f16] } 2199:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh,
20727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20730 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20731 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20732 GIR_EraseFromParent, /*InsnID*/0,
20733 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20734 // GIR_Coverage, 1289,
20735 GIR_Done,
20736 // Label 1134: @52309
20737 GIM_Try, /*On fail goto*//*Label 1135*/ 52368, // Rule ID 1290 //
20738 GIM_CheckFeatures, GIFBS_HasNEON,
20739 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
20740 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20741 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20742 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20746 // (intrinsic_wo_chain:{ *:[v8i8] } 2201:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8,
20748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20751 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20752 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20753 GIR_EraseFromParent, /*InsnID*/0,
20754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20755 // GIR_Coverage, 1290,
20756 GIR_Done,
20757 // Label 1135: @52368
20758 GIM_Try, /*On fail goto*//*Label 1136*/ 52427, // Rule ID 1291 //
20759 GIM_CheckFeatures, GIFBS_HasNEON,
20760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
20761 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20763 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20767 // (intrinsic_wo_chain:{ *:[v4i16] } 2201:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16,
20769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20772 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20773 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20774 GIR_EraseFromParent, /*InsnID*/0,
20775 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20776 // GIR_Coverage, 1291,
20777 GIR_Done,
20778 // Label 1136: @52427
20779 GIM_Try, /*On fail goto*//*Label 1137*/ 52486, // Rule ID 1292 //
20780 GIM_CheckFeatures, GIFBS_HasNEON,
20781 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
20782 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20783 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20784 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20788 // (intrinsic_wo_chain:{ *:[v2i32] } 2201:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32,
20790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20793 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20794 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20795 GIR_EraseFromParent, /*InsnID*/0,
20796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20797 // GIR_Coverage, 1292,
20798 GIR_Done,
20799 // Label 1137: @52486
20800 GIM_Try, /*On fail goto*//*Label 1138*/ 52545, // Rule ID 1293 //
20801 GIM_CheckFeatures, GIFBS_HasNEON,
20802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
20803 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
20804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
20805 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
20806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20809 // (intrinsic_wo_chain:{ *:[v8i8] } 2202:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8,
20811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20814 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20815 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20816 GIR_EraseFromParent, /*InsnID*/0,
20817 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20818 // GIR_Coverage, 1293,
20819 GIR_Done,
20820 // Label 1138: @52545
20821 GIM_Try, /*On fail goto*//*Label 1139*/ 52604, // Rule ID 1294 //
20822 GIM_CheckFeatures, GIFBS_HasNEON,
20823 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
20824 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20825 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20826 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20830 // (intrinsic_wo_chain:{ *:[v4i16] } 2202:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16,
20832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20835 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20836 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20837 GIR_EraseFromParent, /*InsnID*/0,
20838 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20839 // GIR_Coverage, 1294,
20840 GIR_Done,
20841 // Label 1139: @52604
20842 GIM_Try, /*On fail goto*//*Label 1140*/ 52663, // Rule ID 1295 //
20843 GIM_CheckFeatures, GIFBS_HasNEON,
20844 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
20845 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20846 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20847 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20851 // (intrinsic_wo_chain:{ *:[v2i32] } 2202:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20852 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32,
20853 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20856 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20857 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20858 GIR_EraseFromParent, /*InsnID*/0,
20859 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20860 // GIR_Coverage, 1295,
20861 GIR_Done,
20862 // Label 1140: @52663
20863 GIM_Try, /*On fail goto*//*Label 1141*/ 52722, // Rule ID 1296 //
20864 GIM_CheckFeatures, GIFBS_HasNEON,
20865 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
20866 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20867 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20868 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20872 // (intrinsic_wo_chain:{ *:[v2f32] } 2201:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf,
20874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20877 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20878 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20879 GIR_EraseFromParent, /*InsnID*/0,
20880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20881 // GIR_Coverage, 1296,
20882 GIR_Done,
20883 // Label 1141: @52722
20884 GIM_Try, /*On fail goto*//*Label 1142*/ 52781, // Rule ID 1297 //
20885 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
20887 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20889 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20893 // (intrinsic_wo_chain:{ *:[v4f16] } 2201:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh,
20895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20898 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20899 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20900 GIR_EraseFromParent, /*InsnID*/0,
20901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20902 // GIR_Coverage, 1297,
20903 GIR_Done,
20904 // Label 1142: @52781
20905 GIM_Try, /*On fail goto*//*Label 1143*/ 52840, // Rule ID 1304 //
20906 GIM_CheckFeatures, GIFBS_HasNEON,
20907 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
20908 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20909 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20910 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20914 // (intrinsic_wo_chain:{ *:[v2f32] } 2224:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20915 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd,
20916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20919 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20920 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20921 GIR_EraseFromParent, /*InsnID*/0,
20922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20923 // GIR_Coverage, 1304,
20924 GIR_Done,
20925 // Label 1143: @52840
20926 GIM_Try, /*On fail goto*//*Label 1144*/ 52899, // Rule ID 1305 //
20927 GIM_CheckFeatures, GIFBS_HasNEON,
20928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
20929 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
20930 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
20931 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
20932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20935 // (intrinsic_wo_chain:{ *:[v4f32] } 2224:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq,
20937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20940 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20942 GIR_EraseFromParent, /*InsnID*/0,
20943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20944 // GIR_Coverage, 1305,
20945 GIR_Done,
20946 // Label 1144: @52899
20947 GIM_Try, /*On fail goto*//*Label 1145*/ 52958, // Rule ID 1306 //
20948 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
20950 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
20951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
20952 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
20953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20956 // (intrinsic_wo_chain:{ *:[v4f16] } 2224:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd,
20958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20961 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20962 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20963 GIR_EraseFromParent, /*InsnID*/0,
20964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20965 // GIR_Coverage, 1306,
20966 GIR_Done,
20967 // Label 1145: @52958
20968 GIM_Try, /*On fail goto*//*Label 1146*/ 53017, // Rule ID 1307 //
20969 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
20970 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
20971 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
20972 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
20973 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
20974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
20975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
20976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
20977 // (intrinsic_wo_chain:{ *:[v8f16] } 2224:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq,
20979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
20980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
20981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
20982 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20983 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
20984 GIR_EraseFromParent, /*InsnID*/0,
20985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20986 // GIR_Coverage, 1307,
20987 GIR_Done,
20988 // Label 1146: @53017
20989 GIM_Try, /*On fail goto*//*Label 1147*/ 53076, // Rule ID 1314 //
20990 GIM_CheckFeatures, GIFBS_HasNEON,
20991 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
20992 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
20993 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
20994 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
20995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
20996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
20997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
20998 // (intrinsic_wo_chain:{ *:[v2f32] } 2237:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20999 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd,
21000 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21003 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21004 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21005 GIR_EraseFromParent, /*InsnID*/0,
21006 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21007 // GIR_Coverage, 1314,
21008 GIR_Done,
21009 // Label 1147: @53076
21010 GIM_Try, /*On fail goto*//*Label 1148*/ 53135, // Rule ID 1315 //
21011 GIM_CheckFeatures, GIFBS_HasNEON,
21012 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21013 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21014 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21015 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21018 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21019 // (intrinsic_wo_chain:{ *:[v4f32] } 2237:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq,
21021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21024 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21025 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21026 GIR_EraseFromParent, /*InsnID*/0,
21027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21028 // GIR_Coverage, 1315,
21029 GIR_Done,
21030 // Label 1148: @53135
21031 GIM_Try, /*On fail goto*//*Label 1149*/ 53194, // Rule ID 1316 //
21032 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21034 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21035 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21036 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21040 // (intrinsic_wo_chain:{ *:[v4f16] } 2237:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd,
21042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21045 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21046 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21047 GIR_EraseFromParent, /*InsnID*/0,
21048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21049 // GIR_Coverage, 1316,
21050 GIR_Done,
21051 // Label 1149: @53194
21052 GIM_Try, /*On fail goto*//*Label 1150*/ 53253, // Rule ID 1317 //
21053 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
21055 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21056 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21057 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21061 // (intrinsic_wo_chain:{ *:[v8f16] } 2237:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq,
21063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
21065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
21066 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21067 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21068 GIR_EraseFromParent, /*InsnID*/0,
21069 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21070 // GIR_Coverage, 1317,
21071 GIR_Done,
21072 // Label 1150: @53253
21073 GIM_Try, /*On fail goto*//*Label 1151*/ 53312, // Rule ID 1318 //
21074 GIM_CheckFeatures, GIFBS_HasNEON,
21075 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21076 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21077 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21078 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21082 // (intrinsic_wo_chain:{ *:[v4i16] } 2240:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16,
21084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21087 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21088 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21089 GIR_EraseFromParent, /*InsnID*/0,
21090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21091 // GIR_Coverage, 1318,
21092 GIR_Done,
21093 // Label 1151: @53312
21094 GIM_Try, /*On fail goto*//*Label 1152*/ 53371, // Rule ID 1319 //
21095 GIM_CheckFeatures, GIFBS_HasNEON,
21096 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21097 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21099 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21103 // (intrinsic_wo_chain:{ *:[v2i32] } 2240:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32,
21105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21108 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21109 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21110 GIR_EraseFromParent, /*InsnID*/0,
21111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21112 // GIR_Coverage, 1319,
21113 GIR_Done,
21114 // Label 1152: @53371
21115 GIM_Try, /*On fail goto*//*Label 1153*/ 53430, // Rule ID 1320 //
21116 GIM_CheckFeatures, GIFBS_HasNEON,
21117 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21118 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21119 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21120 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21124 // (intrinsic_wo_chain:{ *:[v8i16] } 2240:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16,
21126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21129 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21130 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21131 GIR_EraseFromParent, /*InsnID*/0,
21132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21133 // GIR_Coverage, 1320,
21134 GIR_Done,
21135 // Label 1153: @53430
21136 GIM_Try, /*On fail goto*//*Label 1154*/ 53489, // Rule ID 1321 //
21137 GIM_CheckFeatures, GIFBS_HasNEON,
21138 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21139 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21140 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21141 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21145 // (intrinsic_wo_chain:{ *:[v4i32] } 2240:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32,
21147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21150 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21151 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21152 GIR_EraseFromParent, /*InsnID*/0,
21153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21154 // GIR_Coverage, 1321,
21155 GIR_Done,
21156 // Label 1154: @53489
21157 GIM_Try, /*On fail goto*//*Label 1155*/ 53548, // Rule ID 1322 //
21158 GIM_CheckFeatures, GIFBS_HasNEON,
21159 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21160 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21161 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21162 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21166 // (intrinsic_wo_chain:{ *:[v8i8] } 2240:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8,
21168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21171 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21172 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21173 GIR_EraseFromParent, /*InsnID*/0,
21174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21175 // GIR_Coverage, 1322,
21176 GIR_Done,
21177 // Label 1155: @53548
21178 GIM_Try, /*On fail goto*//*Label 1156*/ 53607, // Rule ID 1323 //
21179 GIM_CheckFeatures, GIFBS_HasNEON,
21180 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21181 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21182 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21183 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21187 // (intrinsic_wo_chain:{ *:[v16i8] } 2240:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8,
21189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21192 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21193 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21194 GIR_EraseFromParent, /*InsnID*/0,
21195 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21196 // GIR_Coverage, 1323,
21197 GIR_Done,
21198 // Label 1156: @53607
21199 GIM_Try, /*On fail goto*//*Label 1157*/ 53666, // Rule ID 1324 //
21200 GIM_CheckFeatures, GIFBS_HasNEON,
21201 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21202 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21203 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21204 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21208 // (intrinsic_wo_chain:{ *:[v1i64] } 2240:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64,
21210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21213 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21214 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21215 GIR_EraseFromParent, /*InsnID*/0,
21216 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21217 // GIR_Coverage, 1324,
21218 GIR_Done,
21219 // Label 1157: @53666
21220 GIM_Try, /*On fail goto*//*Label 1158*/ 53725, // Rule ID 1325 //
21221 GIM_CheckFeatures, GIFBS_HasNEON,
21222 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
21223 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21224 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21225 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21229 // (intrinsic_wo_chain:{ *:[v2i64] } 2240:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64,
21231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21234 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21235 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21236 GIR_EraseFromParent, /*InsnID*/0,
21237 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21238 // GIR_Coverage, 1325,
21239 GIR_Done,
21240 // Label 1158: @53725
21241 GIM_Try, /*On fail goto*//*Label 1159*/ 53784, // Rule ID 1326 //
21242 GIM_CheckFeatures, GIFBS_HasNEON,
21243 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21244 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21245 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21246 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21250 // (intrinsic_wo_chain:{ *:[v4i16] } 2241:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21251 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16,
21252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21255 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21256 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21257 GIR_EraseFromParent, /*InsnID*/0,
21258 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21259 // GIR_Coverage, 1326,
21260 GIR_Done,
21261 // Label 1159: @53784
21262 GIM_Try, /*On fail goto*//*Label 1160*/ 53843, // Rule ID 1327 //
21263 GIM_CheckFeatures, GIFBS_HasNEON,
21264 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21265 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21266 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21267 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21271 // (intrinsic_wo_chain:{ *:[v2i32] } 2241:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32,
21273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21276 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21277 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21278 GIR_EraseFromParent, /*InsnID*/0,
21279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21280 // GIR_Coverage, 1327,
21281 GIR_Done,
21282 // Label 1160: @53843
21283 GIM_Try, /*On fail goto*//*Label 1161*/ 53902, // Rule ID 1328 //
21284 GIM_CheckFeatures, GIFBS_HasNEON,
21285 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21286 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21287 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21288 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21292 // (intrinsic_wo_chain:{ *:[v8i16] } 2241:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16,
21294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21297 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21298 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21299 GIR_EraseFromParent, /*InsnID*/0,
21300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21301 // GIR_Coverage, 1328,
21302 GIR_Done,
21303 // Label 1161: @53902
21304 GIM_Try, /*On fail goto*//*Label 1162*/ 53961, // Rule ID 1329 //
21305 GIM_CheckFeatures, GIFBS_HasNEON,
21306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21307 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21308 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21309 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21313 // (intrinsic_wo_chain:{ *:[v4i32] } 2241:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32,
21315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21318 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21319 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21320 GIR_EraseFromParent, /*InsnID*/0,
21321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21322 // GIR_Coverage, 1329,
21323 GIR_Done,
21324 // Label 1162: @53961
21325 GIM_Try, /*On fail goto*//*Label 1163*/ 54020, // Rule ID 1330 //
21326 GIM_CheckFeatures, GIFBS_HasNEON,
21327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21328 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21329 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21330 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21334 // (intrinsic_wo_chain:{ *:[v8i8] } 2241:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8,
21336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21339 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21340 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21341 GIR_EraseFromParent, /*InsnID*/0,
21342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21343 // GIR_Coverage, 1330,
21344 GIR_Done,
21345 // Label 1163: @54020
21346 GIM_Try, /*On fail goto*//*Label 1164*/ 54079, // Rule ID 1331 //
21347 GIM_CheckFeatures, GIFBS_HasNEON,
21348 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21349 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21350 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21351 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21355 // (intrinsic_wo_chain:{ *:[v16i8] } 2241:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8,
21357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21360 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21361 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21362 GIR_EraseFromParent, /*InsnID*/0,
21363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21364 // GIR_Coverage, 1331,
21365 GIR_Done,
21366 // Label 1164: @54079
21367 GIM_Try, /*On fail goto*//*Label 1165*/ 54138, // Rule ID 1332 //
21368 GIM_CheckFeatures, GIFBS_HasNEON,
21369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21370 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21371 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21372 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21376 // (intrinsic_wo_chain:{ *:[v1i64] } 2241:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64,
21378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21381 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21382 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21383 GIR_EraseFromParent, /*InsnID*/0,
21384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21385 // GIR_Coverage, 1332,
21386 GIR_Done,
21387 // Label 1165: @54138
21388 GIM_Try, /*On fail goto*//*Label 1166*/ 54197, // Rule ID 1333 //
21389 GIM_CheckFeatures, GIFBS_HasNEON,
21390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
21391 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21392 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21393 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21397 // (intrinsic_wo_chain:{ *:[v2i64] } 2241:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64,
21399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21402 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21403 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21404 GIR_EraseFromParent, /*InsnID*/0,
21405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21406 // GIR_Coverage, 1333,
21407 GIR_Done,
21408 // Label 1166: @54197
21409 GIM_Try, /*On fail goto*//*Label 1167*/ 54256, // Rule ID 1367 //
21410 GIM_CheckFeatures, GIFBS_HasNEON,
21411 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21412 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21413 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21414 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21418 // (intrinsic_wo_chain:{ *:[v4i16] } 2234:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16,
21420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21423 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21424 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21425 GIR_EraseFromParent, /*InsnID*/0,
21426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21427 // GIR_Coverage, 1367,
21428 GIR_Done,
21429 // Label 1167: @54256
21430 GIM_Try, /*On fail goto*//*Label 1168*/ 54315, // Rule ID 1368 //
21431 GIM_CheckFeatures, GIFBS_HasNEON,
21432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21433 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21434 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21435 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21439 // (intrinsic_wo_chain:{ *:[v2i32] } 2234:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32,
21441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21444 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21445 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21446 GIR_EraseFromParent, /*InsnID*/0,
21447 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21448 // GIR_Coverage, 1368,
21449 GIR_Done,
21450 // Label 1168: @54315
21451 GIM_Try, /*On fail goto*//*Label 1169*/ 54374, // Rule ID 1369 //
21452 GIM_CheckFeatures, GIFBS_HasNEON,
21453 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21454 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21455 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21456 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21460 // (intrinsic_wo_chain:{ *:[v8i16] } 2234:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16,
21462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21465 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21466 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21467 GIR_EraseFromParent, /*InsnID*/0,
21468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21469 // GIR_Coverage, 1369,
21470 GIR_Done,
21471 // Label 1169: @54374
21472 GIM_Try, /*On fail goto*//*Label 1170*/ 54433, // Rule ID 1370 //
21473 GIM_CheckFeatures, GIFBS_HasNEON,
21474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21475 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21476 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21477 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21481 // (intrinsic_wo_chain:{ *:[v4i32] } 2234:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32,
21483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21486 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21487 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21488 GIR_EraseFromParent, /*InsnID*/0,
21489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21490 // GIR_Coverage, 1370,
21491 GIR_Done,
21492 // Label 1170: @54433
21493 GIM_Try, /*On fail goto*//*Label 1171*/ 54492, // Rule ID 1371 //
21494 GIM_CheckFeatures, GIFBS_HasNEON,
21495 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21496 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21497 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21498 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21502 // (intrinsic_wo_chain:{ *:[v8i8] } 2234:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8,
21504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21507 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21508 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21509 GIR_EraseFromParent, /*InsnID*/0,
21510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21511 // GIR_Coverage, 1371,
21512 GIR_Done,
21513 // Label 1171: @54492
21514 GIM_Try, /*On fail goto*//*Label 1172*/ 54551, // Rule ID 1372 //
21515 GIM_CheckFeatures, GIFBS_HasNEON,
21516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21519 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21523 // (intrinsic_wo_chain:{ *:[v16i8] } 2234:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8,
21525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21528 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21529 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21530 GIR_EraseFromParent, /*InsnID*/0,
21531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21532 // GIR_Coverage, 1372,
21533 GIR_Done,
21534 // Label 1172: @54551
21535 GIM_Try, /*On fail goto*//*Label 1173*/ 54610, // Rule ID 1373 //
21536 GIM_CheckFeatures, GIFBS_HasNEON,
21537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21538 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21539 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21540 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21544 // (intrinsic_wo_chain:{ *:[v1i64] } 2234:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64,
21546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21549 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21550 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21551 GIR_EraseFromParent, /*InsnID*/0,
21552 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21553 // GIR_Coverage, 1373,
21554 GIR_Done,
21555 // Label 1173: @54610
21556 GIM_Try, /*On fail goto*//*Label 1174*/ 54669, // Rule ID 1374 //
21557 GIM_CheckFeatures, GIFBS_HasNEON,
21558 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
21559 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21560 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21561 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21565 // (intrinsic_wo_chain:{ *:[v2i64] } 2234:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64,
21567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21570 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21571 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21572 GIR_EraseFromParent, /*InsnID*/0,
21573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21574 // GIR_Coverage, 1374,
21575 GIR_Done,
21576 // Label 1174: @54669
21577 GIM_Try, /*On fail goto*//*Label 1175*/ 54728, // Rule ID 1375 //
21578 GIM_CheckFeatures, GIFBS_HasNEON,
21579 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21580 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21581 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21582 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21586 // (intrinsic_wo_chain:{ *:[v4i16] } 2235:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i16,
21588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21591 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21592 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21593 GIR_EraseFromParent, /*InsnID*/0,
21594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21595 // GIR_Coverage, 1375,
21596 GIR_Done,
21597 // Label 1175: @54728
21598 GIM_Try, /*On fail goto*//*Label 1176*/ 54787, // Rule ID 1376 //
21599 GIM_CheckFeatures, GIFBS_HasNEON,
21600 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21601 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21603 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21607 // (intrinsic_wo_chain:{ *:[v2i32] } 2235:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i32,
21609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21612 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21613 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21614 GIR_EraseFromParent, /*InsnID*/0,
21615 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21616 // GIR_Coverage, 1376,
21617 GIR_Done,
21618 // Label 1176: @54787
21619 GIM_Try, /*On fail goto*//*Label 1177*/ 54846, // Rule ID 1377 //
21620 GIM_CheckFeatures, GIFBS_HasNEON,
21621 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21622 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21623 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21624 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21628 // (intrinsic_wo_chain:{ *:[v8i16] } 2235:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i16,
21630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21633 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21634 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21635 GIR_EraseFromParent, /*InsnID*/0,
21636 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21637 // GIR_Coverage, 1377,
21638 GIR_Done,
21639 // Label 1177: @54846
21640 GIM_Try, /*On fail goto*//*Label 1178*/ 54905, // Rule ID 1378 //
21641 GIM_CheckFeatures, GIFBS_HasNEON,
21642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21643 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21644 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21645 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21649 // (intrinsic_wo_chain:{ *:[v4i32] } 2235:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i32,
21651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21654 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21655 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21656 GIR_EraseFromParent, /*InsnID*/0,
21657 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21658 // GIR_Coverage, 1378,
21659 GIR_Done,
21660 // Label 1178: @54905
21661 GIM_Try, /*On fail goto*//*Label 1179*/ 54964, // Rule ID 1379 //
21662 GIM_CheckFeatures, GIFBS_HasNEON,
21663 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21664 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21665 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21666 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21670 // (intrinsic_wo_chain:{ *:[v8i8] } 2235:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21671 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i8,
21672 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21675 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21676 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21677 GIR_EraseFromParent, /*InsnID*/0,
21678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21679 // GIR_Coverage, 1379,
21680 GIR_Done,
21681 // Label 1179: @54964
21682 GIM_Try, /*On fail goto*//*Label 1180*/ 55023, // Rule ID 1380 //
21683 GIM_CheckFeatures, GIFBS_HasNEON,
21684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21685 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21686 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21687 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21691 // (intrinsic_wo_chain:{ *:[v16i8] } 2235:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv16i8,
21693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21696 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21697 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21698 GIR_EraseFromParent, /*InsnID*/0,
21699 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21700 // GIR_Coverage, 1380,
21701 GIR_Done,
21702 // Label 1180: @55023
21703 GIM_Try, /*On fail goto*//*Label 1181*/ 55082, // Rule ID 1381 //
21704 GIM_CheckFeatures, GIFBS_HasNEON,
21705 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21706 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21707 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21708 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21712 // (intrinsic_wo_chain:{ *:[v1i64] } 2235:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv1i64,
21714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21717 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21718 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21719 GIR_EraseFromParent, /*InsnID*/0,
21720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21721 // GIR_Coverage, 1381,
21722 GIR_Done,
21723 // Label 1181: @55082
21724 GIM_Try, /*On fail goto*//*Label 1182*/ 55141, // Rule ID 1382 //
21725 GIM_CheckFeatures, GIFBS_HasNEON,
21726 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
21727 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21729 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21733 // (intrinsic_wo_chain:{ *:[v2i64] } 2235:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i64,
21735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21738 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21739 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21740 GIR_EraseFromParent, /*InsnID*/0,
21741 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21742 // GIR_Coverage, 1382,
21743 GIR_Done,
21744 // Label 1182: @55141
21745 GIM_Try, /*On fail goto*//*Label 1183*/ 55200, // Rule ID 1402 //
21746 GIM_CheckFeatures, GIFBS_HasNEON,
21747 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21748 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21749 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21750 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21754 // (intrinsic_wo_chain:{ *:[v4i16] } 2219:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21755 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i16,
21756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21759 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21760 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21761 GIR_EraseFromParent, /*InsnID*/0,
21762 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21763 // GIR_Coverage, 1402,
21764 GIR_Done,
21765 // Label 1183: @55200
21766 GIM_Try, /*On fail goto*//*Label 1184*/ 55259, // Rule ID 1403 //
21767 GIM_CheckFeatures, GIFBS_HasNEON,
21768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21769 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21770 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21771 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21775 // (intrinsic_wo_chain:{ *:[v2i32] } 2219:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i32,
21777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21780 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21781 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21782 GIR_EraseFromParent, /*InsnID*/0,
21783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21784 // GIR_Coverage, 1403,
21785 GIR_Done,
21786 // Label 1184: @55259
21787 GIM_Try, /*On fail goto*//*Label 1185*/ 55318, // Rule ID 1404 //
21788 GIM_CheckFeatures, GIFBS_HasNEON,
21789 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21790 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21791 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21792 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21796 // (intrinsic_wo_chain:{ *:[v8i16] } 2219:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i16,
21798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21801 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21802 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21803 GIR_EraseFromParent, /*InsnID*/0,
21804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21805 // GIR_Coverage, 1404,
21806 GIR_Done,
21807 // Label 1185: @55318
21808 GIM_Try, /*On fail goto*//*Label 1186*/ 55377, // Rule ID 1405 //
21809 GIM_CheckFeatures, GIFBS_HasNEON,
21810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21811 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21812 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21813 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21817 // (intrinsic_wo_chain:{ *:[v4i32] } 2219:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i32,
21819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21822 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21823 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21824 GIR_EraseFromParent, /*InsnID*/0,
21825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21826 // GIR_Coverage, 1405,
21827 GIR_Done,
21828 // Label 1186: @55377
21829 GIM_Try, /*On fail goto*//*Label 1187*/ 55436, // Rule ID 1406 //
21830 GIM_CheckFeatures, GIFBS_HasNEON,
21831 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21832 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
21833 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
21834 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
21835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21838 // (intrinsic_wo_chain:{ *:[v8i8] } 2219:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i8,
21840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21843 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21844 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21845 GIR_EraseFromParent, /*InsnID*/0,
21846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21847 // GIR_Coverage, 1406,
21848 GIR_Done,
21849 // Label 1187: @55436
21850 GIM_Try, /*On fail goto*//*Label 1188*/ 55495, // Rule ID 1407 //
21851 GIM_CheckFeatures, GIFBS_HasNEON,
21852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21853 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
21854 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
21855 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
21856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21859 // (intrinsic_wo_chain:{ *:[v16i8] } 2219:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv16i8,
21861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21864 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21865 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21866 GIR_EraseFromParent, /*InsnID*/0,
21867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21868 // GIR_Coverage, 1407,
21869 GIR_Done,
21870 // Label 1188: @55495
21871 GIM_Try, /*On fail goto*//*Label 1189*/ 55554, // Rule ID 1408 //
21872 GIM_CheckFeatures, GIFBS_HasNEON,
21873 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21874 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
21875 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21876 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
21877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21880 // (intrinsic_wo_chain:{ *:[v1i64] } 2219:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv1i64,
21882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21885 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21886 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21887 GIR_EraseFromParent, /*InsnID*/0,
21888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21889 // GIR_Coverage, 1408,
21890 GIR_Done,
21891 // Label 1189: @55554
21892 GIM_Try, /*On fail goto*//*Label 1190*/ 55613, // Rule ID 1409 //
21893 GIM_CheckFeatures, GIFBS_HasNEON,
21894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
21895 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
21896 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
21897 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
21898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21901 // (intrinsic_wo_chain:{ *:[v2i64] } 2219:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i64,
21903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21906 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21907 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21908 GIR_EraseFromParent, /*InsnID*/0,
21909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21910 // GIR_Coverage, 1409,
21911 GIR_Done,
21912 // Label 1190: @55613
21913 GIM_Try, /*On fail goto*//*Label 1191*/ 55672, // Rule ID 1410 //
21914 GIM_CheckFeatures, GIFBS_HasNEON,
21915 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
21916 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
21917 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21918 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
21919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21922 // (intrinsic_wo_chain:{ *:[v4i16] } 2221:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i16,
21924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21927 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21928 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21929 GIR_EraseFromParent, /*InsnID*/0,
21930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21931 // GIR_Coverage, 1410,
21932 GIR_Done,
21933 // Label 1191: @55672
21934 GIM_Try, /*On fail goto*//*Label 1192*/ 55731, // Rule ID 1411 //
21935 GIM_CheckFeatures, GIFBS_HasNEON,
21936 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
21937 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
21938 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21939 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
21940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21943 // (intrinsic_wo_chain:{ *:[v2i32] } 2221:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i32,
21945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21948 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21949 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21950 GIR_EraseFromParent, /*InsnID*/0,
21951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21952 // GIR_Coverage, 1411,
21953 GIR_Done,
21954 // Label 1192: @55731
21955 GIM_Try, /*On fail goto*//*Label 1193*/ 55790, // Rule ID 1412 //
21956 GIM_CheckFeatures, GIFBS_HasNEON,
21957 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
21958 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
21959 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21960 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
21961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21964 // (intrinsic_wo_chain:{ *:[v8i16] } 2221:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i16,
21966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21969 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21970 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21971 GIR_EraseFromParent, /*InsnID*/0,
21972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21973 // GIR_Coverage, 1412,
21974 GIR_Done,
21975 // Label 1193: @55790
21976 GIM_Try, /*On fail goto*//*Label 1194*/ 55849, // Rule ID 1413 //
21977 GIM_CheckFeatures, GIFBS_HasNEON,
21978 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
21979 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
21980 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21981 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
21982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
21985 // (intrinsic_wo_chain:{ *:[v4i32] } 2221:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i32,
21987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
21990 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21991 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
21992 GIR_EraseFromParent, /*InsnID*/0,
21993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21994 // GIR_Coverage, 1413,
21995 GIR_Done,
21996 // Label 1194: @55849
21997 GIM_Try, /*On fail goto*//*Label 1195*/ 55908, // Rule ID 1414 //
21998 GIM_CheckFeatures, GIFBS_HasNEON,
21999 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22000 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22001 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22002 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22006 // (intrinsic_wo_chain:{ *:[v8i8] } 2221:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i8,
22008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22011 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22012 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22013 GIR_EraseFromParent, /*InsnID*/0,
22014 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22015 // GIR_Coverage, 1414,
22016 GIR_Done,
22017 // Label 1195: @55908
22018 GIM_Try, /*On fail goto*//*Label 1196*/ 55967, // Rule ID 1415 //
22019 GIM_CheckFeatures, GIFBS_HasNEON,
22020 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22021 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22022 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22023 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22027 // (intrinsic_wo_chain:{ *:[v16i8] } 2221:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv16i8,
22029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22032 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22033 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22034 GIR_EraseFromParent, /*InsnID*/0,
22035 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22036 // GIR_Coverage, 1415,
22037 GIR_Done,
22038 // Label 1196: @55967
22039 GIM_Try, /*On fail goto*//*Label 1197*/ 56026, // Rule ID 1416 //
22040 GIM_CheckFeatures, GIFBS_HasNEON,
22041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22042 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22043 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22044 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22048 // (intrinsic_wo_chain:{ *:[v1i64] } 2221:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv1i64,
22050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22053 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22054 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22055 GIR_EraseFromParent, /*InsnID*/0,
22056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22057 // GIR_Coverage, 1416,
22058 GIR_Done,
22059 // Label 1197: @56026
22060 GIM_Try, /*On fail goto*//*Label 1198*/ 56085, // Rule ID 1417 //
22061 GIM_CheckFeatures, GIFBS_HasNEON,
22062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
22063 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22064 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22065 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22069 // (intrinsic_wo_chain:{ *:[v2i64] } 2221:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i64,
22071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22074 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22075 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22076 GIR_EraseFromParent, /*InsnID*/0,
22077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22078 // GIR_Coverage, 1417,
22079 GIR_Done,
22080 // Label 1198: @56085
22081 GIM_Try, /*On fail goto*//*Label 1199*/ 56144, // Rule ID 1451 //
22082 GIM_CheckFeatures, GIFBS_HasNEON,
22083 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22084 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22085 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22086 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22090 // (intrinsic_wo_chain:{ *:[v4i16] } 2214:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i16,
22092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22095 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22096 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22097 GIR_EraseFromParent, /*InsnID*/0,
22098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22099 // GIR_Coverage, 1451,
22100 GIR_Done,
22101 // Label 1199: @56144
22102 GIM_Try, /*On fail goto*//*Label 1200*/ 56203, // Rule ID 1452 //
22103 GIM_CheckFeatures, GIFBS_HasNEON,
22104 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22105 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22106 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22107 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22111 // (intrinsic_wo_chain:{ *:[v2i32] } 2214:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i32,
22113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22116 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22117 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22118 GIR_EraseFromParent, /*InsnID*/0,
22119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22120 // GIR_Coverage, 1452,
22121 GIR_Done,
22122 // Label 1200: @56203
22123 GIM_Try, /*On fail goto*//*Label 1201*/ 56262, // Rule ID 1453 //
22124 GIM_CheckFeatures, GIFBS_HasNEON,
22125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22126 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22127 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22128 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22132 // (intrinsic_wo_chain:{ *:[v8i16] } 2214:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i16,
22134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22137 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22138 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22139 GIR_EraseFromParent, /*InsnID*/0,
22140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22141 // GIR_Coverage, 1453,
22142 GIR_Done,
22143 // Label 1201: @56262
22144 GIM_Try, /*On fail goto*//*Label 1202*/ 56321, // Rule ID 1454 //
22145 GIM_CheckFeatures, GIFBS_HasNEON,
22146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22147 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22148 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22149 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22153 // (intrinsic_wo_chain:{ *:[v4i32] } 2214:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i32,
22155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22158 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22159 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22160 GIR_EraseFromParent, /*InsnID*/0,
22161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22162 // GIR_Coverage, 1454,
22163 GIR_Done,
22164 // Label 1202: @56321
22165 GIM_Try, /*On fail goto*//*Label 1203*/ 56380, // Rule ID 1455 //
22166 GIM_CheckFeatures, GIFBS_HasNEON,
22167 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22168 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22169 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22170 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22174 // (intrinsic_wo_chain:{ *:[v8i8] } 2214:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i8,
22176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22179 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22180 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22181 GIR_EraseFromParent, /*InsnID*/0,
22182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22183 // GIR_Coverage, 1455,
22184 GIR_Done,
22185 // Label 1203: @56380
22186 GIM_Try, /*On fail goto*//*Label 1204*/ 56439, // Rule ID 1456 //
22187 GIM_CheckFeatures, GIFBS_HasNEON,
22188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22189 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22190 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22191 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22195 // (intrinsic_wo_chain:{ *:[v16i8] } 2214:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv16i8,
22197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22200 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22201 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22202 GIR_EraseFromParent, /*InsnID*/0,
22203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22204 // GIR_Coverage, 1456,
22205 GIR_Done,
22206 // Label 1204: @56439
22207 GIM_Try, /*On fail goto*//*Label 1205*/ 56498, // Rule ID 1457 //
22208 GIM_CheckFeatures, GIFBS_HasNEON,
22209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22210 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22211 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22212 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22216 // (intrinsic_wo_chain:{ *:[v1i64] } 2214:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv1i64,
22218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22221 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22222 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22223 GIR_EraseFromParent, /*InsnID*/0,
22224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22225 // GIR_Coverage, 1457,
22226 GIR_Done,
22227 // Label 1205: @56498
22228 GIM_Try, /*On fail goto*//*Label 1206*/ 56557, // Rule ID 1458 //
22229 GIM_CheckFeatures, GIFBS_HasNEON,
22230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
22231 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22233 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22237 // (intrinsic_wo_chain:{ *:[v2i64] } 2214:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i64,
22239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22242 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22243 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22244 GIR_EraseFromParent, /*InsnID*/0,
22245 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22246 // GIR_Coverage, 1458,
22247 GIR_Done,
22248 // Label 1206: @56557
22249 GIM_Try, /*On fail goto*//*Label 1207*/ 56616, // Rule ID 1459 //
22250 GIM_CheckFeatures, GIFBS_HasNEON,
22251 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22252 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22253 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22254 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22258 // (intrinsic_wo_chain:{ *:[v4i16] } 2215:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i16,
22260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22263 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22264 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22265 GIR_EraseFromParent, /*InsnID*/0,
22266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22267 // GIR_Coverage, 1459,
22268 GIR_Done,
22269 // Label 1207: @56616
22270 GIM_Try, /*On fail goto*//*Label 1208*/ 56675, // Rule ID 1460 //
22271 GIM_CheckFeatures, GIFBS_HasNEON,
22272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22273 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
22274 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22275 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22279 // (intrinsic_wo_chain:{ *:[v2i32] } 2215:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i32,
22281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22282 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22284 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22285 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22286 GIR_EraseFromParent, /*InsnID*/0,
22287 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22288 // GIR_Coverage, 1460,
22289 GIR_Done,
22290 // Label 1208: @56675
22291 GIM_Try, /*On fail goto*//*Label 1209*/ 56734, // Rule ID 1461 //
22292 GIM_CheckFeatures, GIFBS_HasNEON,
22293 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22294 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
22295 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22296 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
22297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22300 // (intrinsic_wo_chain:{ *:[v8i16] } 2215:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i16,
22302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22305 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22306 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22307 GIR_EraseFromParent, /*InsnID*/0,
22308 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22309 // GIR_Coverage, 1461,
22310 GIR_Done,
22311 // Label 1209: @56734
22312 GIM_Try, /*On fail goto*//*Label 1210*/ 56793, // Rule ID 1462 //
22313 GIM_CheckFeatures, GIFBS_HasNEON,
22314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22315 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22317 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22321 // (intrinsic_wo_chain:{ *:[v4i32] } 2215:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22322 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i32,
22323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22326 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22327 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22328 GIR_EraseFromParent, /*InsnID*/0,
22329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22330 // GIR_Coverage, 1462,
22331 GIR_Done,
22332 // Label 1210: @56793
22333 GIM_Try, /*On fail goto*//*Label 1211*/ 56852, // Rule ID 1463 //
22334 GIM_CheckFeatures, GIFBS_HasNEON,
22335 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22336 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
22337 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
22338 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
22339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22342 // (intrinsic_wo_chain:{ *:[v8i8] } 2215:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i8,
22344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22347 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22348 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22349 GIR_EraseFromParent, /*InsnID*/0,
22350 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22351 // GIR_Coverage, 1463,
22352 GIR_Done,
22353 // Label 1211: @56852
22354 GIM_Try, /*On fail goto*//*Label 1212*/ 56911, // Rule ID 1464 //
22355 GIM_CheckFeatures, GIFBS_HasNEON,
22356 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22357 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22358 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22359 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22363 // (intrinsic_wo_chain:{ *:[v16i8] } 2215:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv16i8,
22365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22368 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22369 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22370 GIR_EraseFromParent, /*InsnID*/0,
22371 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22372 // GIR_Coverage, 1464,
22373 GIR_Done,
22374 // Label 1212: @56911
22375 GIM_Try, /*On fail goto*//*Label 1213*/ 56970, // Rule ID 1465 //
22376 GIM_CheckFeatures, GIFBS_HasNEON,
22377 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22378 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
22379 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22380 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22384 // (intrinsic_wo_chain:{ *:[v1i64] } 2215:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv1i64,
22386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22389 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22390 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22391 GIR_EraseFromParent, /*InsnID*/0,
22392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22393 // GIR_Coverage, 1465,
22394 GIR_Done,
22395 // Label 1213: @56970
22396 GIM_Try, /*On fail goto*//*Label 1214*/ 57029, // Rule ID 1466 //
22397 GIM_CheckFeatures, GIFBS_HasNEON,
22398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
22399 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
22400 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
22401 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
22402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22405 // (intrinsic_wo_chain:{ *:[v2i64] } 2215:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i64,
22407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
22410 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22411 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22412 GIR_EraseFromParent, /*InsnID*/0,
22413 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22414 // GIR_Coverage, 1466,
22415 GIR_Done,
22416 // Label 1214: @57029
22417 GIM_Try, /*On fail goto*//*Label 1215*/ 57081, // Rule ID 1731 //
22418 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
22419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesd,
22420 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22421 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22422 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22426 // (intrinsic_wo_chain:{ *:[v16i8] } 2118:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
22427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESD,
22428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
22430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
22431 GIR_EraseFromParent, /*InsnID*/0,
22432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22433 // GIR_Coverage, 1731,
22434 GIR_Done,
22435 // Label 1215: @57081
22436 GIM_Try, /*On fail goto*//*Label 1216*/ 57133, // Rule ID 1732 //
22437 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
22438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aese,
22439 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
22440 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
22441 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
22442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22445 // (intrinsic_wo_chain:{ *:[v16i8] } 2119:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
22446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESE,
22447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
22449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
22450 GIR_EraseFromParent, /*InsnID*/0,
22451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22452 // GIR_Coverage, 1732,
22453 GIR_Done,
22454 // Label 1216: @57133
22455 GIM_Try, /*On fail goto*//*Label 1217*/ 57185, // Rule ID 1735 //
22456 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
22457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su1,
22458 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22459 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22460 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22464 // (intrinsic_wo_chain:{ *:[v4i32] } 2132:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
22465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU1,
22466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
22468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
22469 GIR_EraseFromParent, /*InsnID*/0,
22470 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22471 // GIR_Coverage, 1735,
22472 GIR_Done,
22473 // Label 1217: @57185
22474 GIM_Try, /*On fail goto*//*Label 1218*/ 57237, // Rule ID 1736 //
22475 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
22476 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su0,
22477 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
22478 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22479 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22483 // (intrinsic_wo_chain:{ *:[v4i32] } 2135:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
22484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU0,
22485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
22487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
22488 GIR_EraseFromParent, /*InsnID*/0,
22489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22490 // GIR_Coverage, 1736,
22491 GIR_Done,
22492 // Label 1218: @57237
22493 GIM_Try, /*On fail goto*//*Label 1219*/ 57296, // Rule ID 1750 //
22494 GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
22495 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_sqrshr,
22496 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22497 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22498 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22502 // (intrinsic_wo_chain:{ *:[i32] } 1980:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
22503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_SQRSHR,
22504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
22505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
22506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22507 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22508 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22509 GIR_EraseFromParent, /*InsnID*/0,
22510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22511 // GIR_Coverage, 1750,
22512 GIR_Done,
22513 // Label 1219: @57296
22514 GIM_Try, /*On fail goto*//*Label 1220*/ 57355, // Rule ID 1751 //
22515 GIM_CheckFeatures, GIFBS_HasMVEInt_HasV8_1MMainline,
22516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_uqrshl,
22517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22519 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22523 // (intrinsic_wo_chain:{ *:[i32] } 1987:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
22524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_UQRSHL,
22525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
22526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // RdaSrc
22527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22528 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22529 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22530 GIR_EraseFromParent, /*InsnID*/0,
22531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22532 // GIR_Coverage, 1751,
22533 GIR_Done,
22534 // Label 1220: @57355
22535 GIM_Try, /*On fail goto*//*Label 1221*/ 57417, // Rule ID 1867 //
22536 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
22537 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
22538 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22539 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22540 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22544 // (intrinsic_wo_chain:{ *:[i32] } 2317:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
22545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTAB16,
22546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22547 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
22548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
22549 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22550 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22551 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22552 GIR_EraseFromParent, /*InsnID*/0,
22553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22554 // GIR_Coverage, 1867,
22555 GIR_Done,
22556 // Label 1221: @57417
22557 GIM_Try, /*On fail goto*//*Label 1222*/ 57479, // Rule ID 1874 //
22558 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
22559 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
22560 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22561 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22562 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22566 // (intrinsic_wo_chain:{ *:[i32] } 2342:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
22567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB16,
22568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
22570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
22571 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22572 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22573 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22574 GIR_EraseFromParent, /*InsnID*/0,
22575 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22576 // GIR_Coverage, 1874,
22577 GIR_Done,
22578 // Label 1222: @57479
22579 GIM_Try, /*On fail goto*//*Label 1223*/ 57538, // Rule ID 1921 //
22580 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
22581 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
22582 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22583 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22584 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22588 // (intrinsic_wo_chain:{ *:[i32] } 2293:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUAD,
22590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22593 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22594 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22595 GIR_EraseFromParent, /*InsnID*/0,
22596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22597 // GIR_Coverage, 1921,
22598 GIR_Done,
22599 // Label 1223: @57538
22600 GIM_Try, /*On fail goto*//*Label 1224*/ 57597, // Rule ID 1922 //
22601 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
22602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
22603 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22605 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22609 // (intrinsic_wo_chain:{ *:[i32] } 2294:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUADX,
22611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22614 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22615 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22616 GIR_EraseFromParent, /*InsnID*/0,
22617 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22618 // GIR_Coverage, 1922,
22619 GIR_Done,
22620 // Label 1224: @57597
22621 GIM_Try, /*On fail goto*//*Label 1225*/ 57656, // Rule ID 1923 //
22622 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
22623 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
22624 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22625 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22626 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22630 // (intrinsic_wo_chain:{ *:[i32] } 2301:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSD,
22632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22635 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22636 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22637 GIR_EraseFromParent, /*InsnID*/0,
22638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22639 // GIR_Coverage, 1923,
22640 GIR_Done,
22641 // Label 1225: @57656
22642 GIM_Try, /*On fail goto*//*Label 1226*/ 57715, // Rule ID 1924 //
22643 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
22644 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
22645 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22646 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22647 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22651 // (intrinsic_wo_chain:{ *:[i32] } 2302:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSDX,
22653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22656 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22657 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22658 GIR_EraseFromParent, /*InsnID*/0,
22659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22660 // GIR_Coverage, 1924,
22661 GIR_Done,
22662 // Label 1226: @57715
22663 GIM_Try, /*On fail goto*//*Label 1227*/ 57774, // Rule ID 1983 //
22664 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
22665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
22666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22668 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
22670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22672 // (intrinsic_wo_chain:{ *:[i32] } 2295:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBB,
22674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
22676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
22677 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22678 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22679 GIR_EraseFromParent, /*InsnID*/0,
22680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22681 // GIR_Coverage, 1983,
22682 GIR_Done,
22683 // Label 1227: @57774
22684 GIM_Try, /*On fail goto*//*Label 1228*/ 57833, // Rule ID 1984 //
22685 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
22686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
22687 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22688 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22689 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
22691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22693 // (intrinsic_wo_chain:{ *:[i32] } 2296:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBT,
22695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
22697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
22698 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22699 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22700 GIR_EraseFromParent, /*InsnID*/0,
22701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22702 // GIR_Coverage, 1984,
22703 GIR_Done,
22704 // Label 1228: @57833
22705 GIM_Try, /*On fail goto*//*Label 1229*/ 57892, // Rule ID 1985 //
22706 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
22707 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
22708 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22709 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22710 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
22712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22714 // (intrinsic_wo_chain:{ *:[i32] } 2297:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTB,
22716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
22718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
22719 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22720 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22721 GIR_EraseFromParent, /*InsnID*/0,
22722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22723 // GIR_Coverage, 1985,
22724 GIR_Done,
22725 // Label 1229: @57892
22726 GIM_Try, /*On fail goto*//*Label 1230*/ 57951, // Rule ID 1986 //
22727 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
22728 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
22729 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22730 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22731 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
22733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22735 // (intrinsic_wo_chain:{ *:[i32] } 2298:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
22737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
22739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
22740 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22741 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22742 GIR_EraseFromParent, /*InsnID*/0,
22743 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22744 // GIR_Coverage, 1986,
22745 GIR_Done,
22746 // Label 1230: @57951
22747 GIM_Try, /*On fail goto*//*Label 1231*/ 58010, // Rule ID 1987 //
22748 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
22749 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
22750 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22751 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22752 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
22754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22756 // (intrinsic_wo_chain:{ *:[i32] } 2299:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWB,
22758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
22760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
22761 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22762 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22763 GIR_EraseFromParent, /*InsnID*/0,
22764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22765 // GIR_Coverage, 1987,
22766 GIR_Done,
22767 // Label 1231: @58010
22768 GIM_Try, /*On fail goto*//*Label 1232*/ 58069, // Rule ID 1988 //
22769 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
22770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
22771 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22773 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
22775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
22776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
22777 // (intrinsic_wo_chain:{ *:[i32] } 2300:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWT,
22779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
22781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
22782 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22783 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22784 GIR_EraseFromParent, /*InsnID*/0,
22785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22786 // GIR_Coverage, 1988,
22787 GIR_Done,
22788 // Label 1232: @58069
22789 GIM_Try, /*On fail goto*//*Label 1233*/ 58131, // Rule ID 2093 //
22790 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22791 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
22792 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22793 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22794 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22798 // (intrinsic_wo_chain:{ *:[i32] } 2317:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
22799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTAB16,
22800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22803 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22804 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22805 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22806 GIR_EraseFromParent, /*InsnID*/0,
22807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22808 // GIR_Coverage, 2093,
22809 GIR_Done,
22810 // Label 1233: @58131
22811 GIM_Try, /*On fail goto*//*Label 1234*/ 58190, // Rule ID 2126 //
22812 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22813 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
22814 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22815 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22816 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22820 // (intrinsic_wo_chain:{ *:[i32] } 2260:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
22821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
22822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
22824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
22825 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22826 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22827 GIR_EraseFromParent, /*InsnID*/0,
22828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22829 // GIR_Coverage, 2126,
22830 GIR_Done,
22831 // Label 1234: @58190
22832 GIM_Try, /*On fail goto*//*Label 1235*/ 58249, // Rule ID 2127 //
22833 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
22835 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22836 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22837 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22841 // (intrinsic_wo_chain:{ *:[i32] } 2265:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
22842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
22843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
22845 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
22846 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22847 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22848 GIR_EraseFromParent, /*InsnID*/0,
22849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22850 // GIR_Coverage, 2127,
22851 GIR_Done,
22852 // Label 1235: @58249
22853 GIM_Try, /*On fail goto*//*Label 1236*/ 58308, // Rule ID 2163 //
22854 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
22856 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22857 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22858 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22862 // (intrinsic_wo_chain:{ *:[i32] } 2295:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
22863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBB,
22864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22867 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22868 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22869 GIR_EraseFromParent, /*InsnID*/0,
22870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22871 // GIR_Coverage, 2163,
22872 GIR_Done,
22873 // Label 1236: @58308
22874 GIM_Try, /*On fail goto*//*Label 1237*/ 58367, // Rule ID 2164 //
22875 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
22877 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22878 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22879 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22883 // (intrinsic_wo_chain:{ *:[i32] } 2296:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
22884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBT,
22885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22888 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22889 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22890 GIR_EraseFromParent, /*InsnID*/0,
22891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22892 // GIR_Coverage, 2164,
22893 GIR_Done,
22894 // Label 1237: @58367
22895 GIM_Try, /*On fail goto*//*Label 1238*/ 58426, // Rule ID 2165 //
22896 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22897 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
22898 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22899 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22900 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22904 // (intrinsic_wo_chain:{ *:[i32] } 2297:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
22905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTB,
22906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22909 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22910 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22911 GIR_EraseFromParent, /*InsnID*/0,
22912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22913 // GIR_Coverage, 2165,
22914 GIR_Done,
22915 // Label 1238: @58426
22916 GIM_Try, /*On fail goto*//*Label 1239*/ 58485, // Rule ID 2166 //
22917 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
22919 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22921 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22925 // (intrinsic_wo_chain:{ *:[i32] } 2298:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
22926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
22927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22930 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22931 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22932 GIR_EraseFromParent, /*InsnID*/0,
22933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22934 // GIR_Coverage, 2166,
22935 GIR_Done,
22936 // Label 1239: @58485
22937 GIM_Try, /*On fail goto*//*Label 1240*/ 58544, // Rule ID 2167 //
22938 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
22940 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22941 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22942 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22946 // (intrinsic_wo_chain:{ *:[i32] } 2299:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
22947 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWB,
22948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22951 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22952 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22953 GIR_EraseFromParent, /*InsnID*/0,
22954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22955 // GIR_Coverage, 2167,
22956 GIR_Done,
22957 // Label 1240: @58544
22958 GIM_Try, /*On fail goto*//*Label 1241*/ 58603, // Rule ID 2168 //
22959 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
22960 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
22961 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
22962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22963 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
22965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
22966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
22967 // (intrinsic_wo_chain:{ *:[i32] } 2300:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
22968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWT,
22969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
22970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22972 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22973 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
22974 GIR_EraseFromParent, /*InsnID*/0,
22975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22976 // GIR_Coverage, 2168,
22977 GIR_Done,
22978 // Label 1241: @58603
22979 GIM_Try, /*On fail goto*//*Label 1242*/ 58658, // Rule ID 2460 //
22980 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
22981 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
22982 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
22983 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22984 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
22985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22988 // (intrinsic_wo_chain:{ *:[v4f16] } 2149:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
22989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16,
22990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
22992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
22993 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
22994 GIR_EraseFromParent, /*InsnID*/0,
22995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22996 // GIR_Coverage, 2460,
22997 GIR_Done,
22998 // Label 1242: @58658
22999 GIM_Try, /*On fail goto*//*Label 1243*/ 58713, // Rule ID 2461 //
23000 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23001 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23002 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
23003 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
23004 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
23005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23008 // (intrinsic_wo_chain:{ *:[v4f16] } 2148:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
23009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f16,
23010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23013 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23014 GIR_EraseFromParent, /*InsnID*/0,
23015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23016 // GIR_Coverage, 2461,
23017 GIR_Done,
23018 // Label 1243: @58713
23019 GIM_Try, /*On fail goto*//*Label 1244*/ 58768, // Rule ID 2462 //
23020 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23021 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23022 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23023 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23024 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23028 // (intrinsic_wo_chain:{ *:[v8f16] } 2149:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
23029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16,
23030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23033 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23034 GIR_EraseFromParent, /*InsnID*/0,
23035 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23036 // GIR_Coverage, 2462,
23037 GIR_Done,
23038 // Label 1244: @58768
23039 GIM_Try, /*On fail goto*//*Label 1245*/ 58823, // Rule ID 2463 //
23040 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8_3a,
23041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23042 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23043 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23044 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23048 // (intrinsic_wo_chain:{ *:[v8f16] } 2148:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
23049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv8f16,
23050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23053 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23054 GIR_EraseFromParent, /*InsnID*/0,
23055 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23056 // GIR_Coverage, 2463,
23057 GIR_Done,
23058 // Label 1245: @58823
23059 GIM_Try, /*On fail goto*//*Label 1246*/ 58878, // Rule ID 2464 //
23060 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23062 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23063 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23064 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
23065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23068 // (intrinsic_wo_chain:{ *:[v2f32] } 2149:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
23069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32,
23070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23072 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23073 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23074 GIR_EraseFromParent, /*InsnID*/0,
23075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23076 // GIR_Coverage, 2464,
23077 GIR_Done,
23078 // Label 1246: @58878
23079 GIM_Try, /*On fail goto*//*Label 1247*/ 58933, // Rule ID 2465 //
23080 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23081 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23082 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
23083 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
23084 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
23085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23088 // (intrinsic_wo_chain:{ *:[v2f32] } 2148:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
23089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv2f32,
23090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23093 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23094 GIR_EraseFromParent, /*InsnID*/0,
23095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23096 // GIR_Coverage, 2465,
23097 GIR_Done,
23098 // Label 1247: @58933
23099 GIM_Try, /*On fail goto*//*Label 1248*/ 58988, // Rule ID 2466 //
23100 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23101 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot90,
23102 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23103 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23104 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23108 // (intrinsic_wo_chain:{ *:[v4f32] } 2149:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
23109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32,
23110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23113 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23114 GIR_EraseFromParent, /*InsnID*/0,
23115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23116 // GIR_Coverage, 2466,
23117 GIR_Done,
23118 // Label 1248: @58988
23119 GIM_Try, /*On fail goto*//*Label 1249*/ 59043, // Rule ID 2467 //
23120 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_3a,
23121 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcadd_rot270,
23122 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23123 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23124 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
23127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
23128 // (intrinsic_wo_chain:{ *:[v4f32] } 2148:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
23129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCADDv4f32,
23130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
23132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23133 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
23134 GIR_EraseFromParent, /*InsnID*/0,
23135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23136 // GIR_Coverage, 2467,
23137 GIR_Done,
23138 // Label 1249: @59043
23139 GIM_Try, /*On fail goto*//*Label 1250*/ 59136, // Rule ID 3099 //
23140 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23141 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmv,
23142 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23143 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23144 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23146 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23148 // (intrinsic_wo_chain:{ *:[f32] } 1956:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23149 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23150 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23151 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23152 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23153 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23154 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23155 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMVf32,
23156 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23157 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23158 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23159 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23160 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23161 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23164 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23165 GIR_EraseFromParent, /*InsnID*/0,
23166 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23167 // GIR_Coverage, 3099,
23168 GIR_Done,
23169 // Label 1250: @59136
23170 GIM_Try, /*On fail goto*//*Label 1251*/ 59229, // Rule ID 3101 //
23171 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmv,
23173 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23175 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23179 // (intrinsic_wo_chain:{ *:[f16] } 1956:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23180 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23181 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23182 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23183 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23184 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23185 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23186 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMVf16,
23187 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23188 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23189 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23190 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23191 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23192 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23195 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23196 GIR_EraseFromParent, /*InsnID*/0,
23197 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23198 // GIR_Coverage, 3101,
23199 GIR_Done,
23200 // Label 1251: @59229
23201 GIM_Try, /*On fail goto*//*Label 1252*/ 59322, // Rule ID 3103 //
23202 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23203 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmv,
23204 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23205 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23206 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23210 // (intrinsic_wo_chain:{ *:[f32] } 1947:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23211 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23212 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23213 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23214 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23215 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23216 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23217 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMVf32,
23218 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23219 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23220 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23221 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23222 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23223 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23226 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23227 GIR_EraseFromParent, /*InsnID*/0,
23228 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23229 // GIR_Coverage, 3103,
23230 GIR_Done,
23231 // Label 1252: @59322
23232 GIM_Try, /*On fail goto*//*Label 1253*/ 59415, // Rule ID 3105 //
23233 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmv,
23235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23241 // (intrinsic_wo_chain:{ *:[f16] } 1947:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23243 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23244 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23245 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23246 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23247 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23248 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMVf16,
23249 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23250 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23251 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23252 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23253 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23254 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23257 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23258 GIR_EraseFromParent, /*InsnID*/0,
23259 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23260 // GIR_Coverage, 3105,
23261 GIR_Done,
23262 // Label 1253: @59415
23263 GIM_Try, /*On fail goto*//*Label 1254*/ 59508, // Rule ID 3107 //
23264 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23265 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmav,
23266 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23267 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23268 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23272 // (intrinsic_wo_chain:{ *:[f32] } 1954:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23273 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23274 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23275 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23276 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23277 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23278 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23279 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMAVf32,
23280 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23281 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23282 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23283 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23284 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23285 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23286 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23288 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23289 GIR_EraseFromParent, /*InsnID*/0,
23290 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23291 // GIR_Coverage, 3107,
23292 GIR_Done,
23293 // Label 1254: @59508
23294 GIM_Try, /*On fail goto*//*Label 1255*/ 59601, // Rule ID 3109 //
23295 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23296 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minnmav,
23297 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23298 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23299 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23303 // (intrinsic_wo_chain:{ *:[f16] } 1954:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23304 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23305 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23306 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23307 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23308 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23309 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23310 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMINNMAVf16,
23311 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23312 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23313 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23314 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23315 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23316 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23319 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23320 GIR_EraseFromParent, /*InsnID*/0,
23321 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23322 // GIR_Coverage, 3109,
23323 GIR_Done,
23324 // Label 1255: @59601
23325 GIM_Try, /*On fail goto*//*Label 1256*/ 59694, // Rule ID 3111 //
23326 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmav,
23328 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23329 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23330 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23334 // (intrinsic_wo_chain:{ *:[f32] } 1945:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23335 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23336 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23337 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23338 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23339 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23340 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23341 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMAVf32,
23342 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23343 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23344 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23345 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23346 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23347 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23350 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23351 GIR_EraseFromParent, /*InsnID*/0,
23352 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
23353 // GIR_Coverage, 3111,
23354 GIR_Done,
23355 // Label 1256: @59694
23356 GIM_Try, /*On fail goto*//*Label 1257*/ 59787, // Rule ID 3113 //
23357 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23358 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxnmav,
23359 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
23360 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
23361 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
23364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23365 // (intrinsic_wo_chain:{ *:[f16] } 1945:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23366 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23367 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23368 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
23369 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
23370 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23371 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
23372 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::MVE_VMAXNMAVf16,
23373 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23374 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
23375 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23376 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
23377 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23378 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23381 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23382 GIR_EraseFromParent, /*InsnID*/0,
23383 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
23384 // GIR_Coverage, 3113,
23385 GIR_Done,
23386 // Label 1257: @59787
23387 GIM_Try, /*On fail goto*//*Label 1258*/ 59846, // Rule ID 3163 //
23388 GIM_CheckFeatures, GIFBS_HasMVEInt,
23389 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minav,
23390 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23391 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23392 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23396 // (intrinsic_wo_chain:{ *:[i32] } 1952:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
23397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAVs8,
23398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
23400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
23401 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23402 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23403 GIR_EraseFromParent, /*InsnID*/0,
23404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23405 // GIR_Coverage, 3163,
23406 GIR_Done,
23407 // Label 1258: @59846
23408 GIM_Try, /*On fail goto*//*Label 1259*/ 59905, // Rule ID 3165 //
23409 GIM_CheckFeatures, GIFBS_HasMVEInt,
23410 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minav,
23411 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23412 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23413 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23417 // (intrinsic_wo_chain:{ *:[i32] } 1952:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
23418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAVs16,
23419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
23421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
23422 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23423 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23424 GIR_EraseFromParent, /*InsnID*/0,
23425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23426 // GIR_Coverage, 3165,
23427 GIR_Done,
23428 // Label 1259: @59905
23429 GIM_Try, /*On fail goto*//*Label 1260*/ 59964, // Rule ID 3167 //
23430 GIM_CheckFeatures, GIFBS_HasMVEInt,
23431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minav,
23432 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23433 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23434 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23438 // (intrinsic_wo_chain:{ *:[i32] } 1952:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
23439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAVs32,
23440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
23442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
23443 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23444 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23445 GIR_EraseFromParent, /*InsnID*/0,
23446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23447 // GIR_Coverage, 3167,
23448 GIR_Done,
23449 // Label 1260: @59964
23450 GIM_Try, /*On fail goto*//*Label 1261*/ 60023, // Rule ID 3169 //
23451 GIM_CheckFeatures, GIFBS_HasMVEInt,
23452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxav,
23453 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23454 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23455 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23459 // (intrinsic_wo_chain:{ *:[i32] } 1943:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
23460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAVs8,
23461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
23463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
23464 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23465 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23466 GIR_EraseFromParent, /*InsnID*/0,
23467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23468 // GIR_Coverage, 3169,
23469 GIR_Done,
23470 // Label 1261: @60023
23471 GIM_Try, /*On fail goto*//*Label 1262*/ 60082, // Rule ID 3171 //
23472 GIM_CheckFeatures, GIFBS_HasMVEInt,
23473 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxav,
23474 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23475 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23476 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23480 // (intrinsic_wo_chain:{ *:[i32] } 1943:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
23481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAVs16,
23482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
23484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
23485 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23486 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23487 GIR_EraseFromParent, /*InsnID*/0,
23488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23489 // GIR_Coverage, 3171,
23490 GIR_Done,
23491 // Label 1262: @60082
23492 GIM_Try, /*On fail goto*//*Label 1263*/ 60141, // Rule ID 3173 //
23493 GIM_CheckFeatures, GIFBS_HasMVEInt,
23494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxav,
23495 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
23496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
23497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
23499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
23500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23501 // (intrinsic_wo_chain:{ *:[i32] } 1943:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
23502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAVs32,
23503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
23504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
23505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
23506 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23507 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23508 GIR_EraseFromParent, /*InsnID*/0,
23509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23510 // GIR_Coverage, 3173,
23511 GIR_Done,
23512 // Label 1263: @60141
23513 GIM_Try, /*On fail goto*//*Label 1264*/ 60214, // Rule ID 3460 //
23514 GIM_CheckFeatures, GIFBS_HasMVEInt,
23515 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
23516 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23517 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23518 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23522 // (intrinsic_wo_chain:{ *:[v16i8] } 2065:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
23523 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23524 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23525 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi8,
23527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
23529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23530 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23531 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23532 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23533 GIR_EraseFromParent, /*InsnID*/0,
23534 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23535 // GIR_Coverage, 3460,
23536 GIR_Done,
23537 // Label 1264: @60214
23538 GIM_Try, /*On fail goto*//*Label 1265*/ 60287, // Rule ID 3467 //
23539 GIM_CheckFeatures, GIFBS_HasMVEInt,
23540 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
23541 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23542 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23543 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23547 // (intrinsic_wo_chain:{ *:[v8i16] } 2065:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
23548 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23549 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23550 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi16,
23552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
23554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23555 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23556 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23557 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23558 GIR_EraseFromParent, /*InsnID*/0,
23559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23560 // GIR_Coverage, 3467,
23561 GIR_Done,
23562 // Label 1265: @60287
23563 GIM_Try, /*On fail goto*//*Label 1266*/ 60360, // Rule ID 3471 //
23564 GIM_CheckFeatures, GIFBS_HasMVEInt,
23565 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmulh,
23566 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23567 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23568 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23572 // (intrinsic_wo_chain:{ *:[v4i32] } 2065:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
23573 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23574 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23575 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULHi32,
23577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
23579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23580 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23581 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23582 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23583 GIR_EraseFromParent, /*InsnID*/0,
23584 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23585 // GIR_Coverage, 3471,
23586 GIR_Done,
23587 // Label 1266: @60360
23588 GIM_Try, /*On fail goto*//*Label 1267*/ 60433, // Rule ID 3473 //
23589 GIM_CheckFeatures, GIFBS_HasMVEInt,
23590 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
23591 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23592 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23593 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
23594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23597 // (intrinsic_wo_chain:{ *:[v16i8] } 2074:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
23598 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23599 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23600 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi8,
23602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
23604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23605 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23606 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23607 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23608 GIR_EraseFromParent, /*InsnID*/0,
23609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23610 // GIR_Coverage, 3473,
23611 GIR_Done,
23612 // Label 1267: @60433
23613 GIM_Try, /*On fail goto*//*Label 1268*/ 60506, // Rule ID 3475 //
23614 GIM_CheckFeatures, GIFBS_HasMVEInt,
23615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
23616 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23617 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23618 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
23619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23622 // (intrinsic_wo_chain:{ *:[v8i16] } 2074:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
23623 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23624 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23625 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23626 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi16,
23627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
23629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23630 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23631 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23632 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23633 GIR_EraseFromParent, /*InsnID*/0,
23634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23635 // GIR_Coverage, 3475,
23636 GIR_Done,
23637 // Label 1268: @60506
23638 GIM_Try, /*On fail goto*//*Label 1269*/ 60579, // Rule ID 3477 //
23639 GIM_CheckFeatures, GIFBS_HasMVEInt,
23640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmulh,
23641 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23642 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23643 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
23644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
23647 // (intrinsic_wo_chain:{ *:[v4i32] } 2074:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
23648 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23649 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23650 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMULHi32,
23652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
23654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
23655 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23656 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23657 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23658 GIR_EraseFromParent, /*InsnID*/0,
23659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23660 // GIR_Coverage, 3477,
23661 GIR_Done,
23662 // Label 1269: @60579
23663 GIM_Try, /*On fail goto*//*Label 1270*/ 60652, // Rule ID 4635 //
23664 GIM_CheckFeatures, GIFBS_HasMVEInt,
23665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
23666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23668 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23672 // (intrinsic_wo_chain:{ *:[v16i8] } 1998:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
23673 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23674 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23675 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8,
23677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
23679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23680 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23681 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23682 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23683 GIR_EraseFromParent, /*InsnID*/0,
23684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23685 // GIR_Coverage, 4635,
23686 GIR_Done,
23687 // Label 1270: @60652
23688 GIM_Try, /*On fail goto*//*Label 1271*/ 60725, // Rule ID 4640 //
23689 GIM_CheckFeatures, GIFBS_HasMVEInt,
23690 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
23691 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23692 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23693 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23697 // (intrinsic_wo_chain:{ *:[v8i16] } 1998:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
23698 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23699 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23700 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
23702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
23704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23705 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23706 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23707 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23708 GIR_EraseFromParent, /*InsnID*/0,
23709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23710 // GIR_Coverage, 4640,
23711 GIR_Done,
23712 // Label 1271: @60725
23713 GIM_Try, /*On fail goto*//*Label 1272*/ 60798, // Rule ID 4642 //
23714 GIM_CheckFeatures, GIFBS_HasMVEInt,
23715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
23716 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23717 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23718 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23722 // (intrinsic_wo_chain:{ *:[v4i32] } 1998:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
23723 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23724 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23725 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
23727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
23729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23730 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23731 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23732 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23733 GIR_EraseFromParent, /*InsnID*/0,
23734 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23735 // GIR_Coverage, 4642,
23736 GIR_Done,
23737 // Label 1272: @60798
23738 GIM_Try, /*On fail goto*//*Label 1273*/ 60871, // Rule ID 4644 //
23739 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23740 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
23741 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23742 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23743 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23747 // (intrinsic_wo_chain:{ *:[v8f16] } 1998:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
23748 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23750 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
23752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
23754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23755 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23756 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23757 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23758 GIR_EraseFromParent, /*InsnID*/0,
23759 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23760 // GIR_Coverage, 4644,
23761 GIR_Done,
23762 // Label 1273: @60871
23763 GIM_Try, /*On fail goto*//*Label 1274*/ 60944, // Rule ID 4646 //
23764 GIM_CheckFeatures, GIFBS_HasMVEFloat,
23765 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vbrsr,
23766 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23767 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23768 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
23772 // (intrinsic_wo_chain:{ *:[v4f32] } 1998:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
23773 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23774 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23775 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
23777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
23779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
23780 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23781 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23782 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23783 GIR_EraseFromParent, /*InsnID*/0,
23784 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23785 // GIR_Coverage, 4646,
23786 GIR_Done,
23787 // Label 1274: @60944
23788 GIM_Reject,
23789 // Label 907: @60945
23790 GIM_Try, /*On fail goto*//*Label 1275*/ 72596,
23791 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
23792 GIM_Try, /*On fail goto*//*Label 1276*/ 61036, // Rule ID 3870 //
23793 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
23794 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23795 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23796 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23797 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23800 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23801 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23802 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
23803 // MIs[1] Operand 1
23804 // No operand predicates
23805 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
23806 GIM_CheckIsSafeToFold, /*InsnID*/1,
23807 // (intrinsic_wo_chain:{ *:[v16i8] } 2075:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
23808 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23809 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23810 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms8,
23812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23814 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23815 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23816 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23817 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23818 GIR_EraseFromParent, /*InsnID*/0,
23819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23820 // GIR_Coverage, 3870,
23821 GIR_Done,
23822 // Label 1276: @61036
23823 GIM_Try, /*On fail goto*//*Label 1277*/ 61122, // Rule ID 3872 //
23824 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
23825 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23827 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23828 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23831 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23832 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23833 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
23834 // MIs[1] Operand 1
23835 // No operand predicates
23836 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
23837 GIM_CheckIsSafeToFold, /*InsnID*/1,
23838 // (intrinsic_wo_chain:{ *:[v16i8] } 2075:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
23839 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23840 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23841 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23842 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu8,
23843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23845 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23846 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23847 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23848 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23849 GIR_EraseFromParent, /*InsnID*/0,
23850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23851 // GIR_Coverage, 3872,
23852 GIR_Done,
23853 // Label 1277: @61122
23854 GIM_Try, /*On fail goto*//*Label 1278*/ 61208, // Rule ID 3874 //
23855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
23856 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23857 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23858 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23859 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23862 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23863 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23864 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
23865 // MIs[1] Operand 1
23866 // No operand predicates
23867 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
23868 GIM_CheckIsSafeToFold, /*InsnID*/1,
23869 // (intrinsic_wo_chain:{ *:[v8i16] } 2075:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
23870 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23871 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23872 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23873 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms16,
23874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23876 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23877 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23878 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23879 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23880 GIR_EraseFromParent, /*InsnID*/0,
23881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23882 // GIR_Coverage, 3874,
23883 GIR_Done,
23884 // Label 1278: @61208
23885 GIM_Try, /*On fail goto*//*Label 1279*/ 61294, // Rule ID 3876 //
23886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
23887 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
23888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
23889 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23890 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23894 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23895 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
23896 // MIs[1] Operand 1
23897 // No operand predicates
23898 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
23899 GIM_CheckIsSafeToFold, /*InsnID*/1,
23900 // (intrinsic_wo_chain:{ *:[v8i16] } 2075:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
23901 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23902 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23903 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu16,
23905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23907 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23908 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23909 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23910 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23911 GIR_EraseFromParent, /*InsnID*/0,
23912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23913 // GIR_Coverage, 3876,
23914 GIR_Done,
23915 // Label 1279: @61294
23916 GIM_Try, /*On fail goto*//*Label 1280*/ 61380, // Rule ID 3878 //
23917 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
23918 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23919 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23920 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23921 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23924 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23925 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23926 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
23927 // MIs[1] Operand 1
23928 // No operand predicates
23929 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
23930 GIM_CheckIsSafeToFold, /*InsnID*/1,
23931 // (intrinsic_wo_chain:{ *:[v4i32] } 2075:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
23932 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23933 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23934 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimms32,
23936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23938 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23939 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23940 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23941 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23942 GIR_EraseFromParent, /*InsnID*/0,
23943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23944 // GIR_Coverage, 3878,
23945 GIR_Done,
23946 // Label 1280: @61380
23947 GIM_Try, /*On fail goto*//*Label 1281*/ 61466, // Rule ID 3880 //
23948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqshl_imm,
23949 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
23950 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
23951 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23952 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23955 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23956 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23957 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
23958 // MIs[1] Operand 1
23959 // No operand predicates
23960 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
23961 GIM_CheckIsSafeToFold, /*InsnID*/1,
23962 // (intrinsic_wo_chain:{ *:[v4i32] } 2075:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
23963 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23964 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23965 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHLimmu32,
23967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
23969 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
23970 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
23971 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
23972 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23973 GIR_EraseFromParent, /*InsnID*/0,
23974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23975 // GIR_Coverage, 3880,
23976 GIR_Done,
23977 // Label 1281: @61466
23978 GIM_Try, /*On fail goto*//*Label 1282*/ 61552, // Rule ID 3888 //
23979 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
23980 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
23981 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
23982 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
23983 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
23984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
23985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
23986 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
23987 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
23988 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
23989 // MIs[1] Operand 1
23990 // No operand predicates
23991 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
23992 GIM_CheckIsSafeToFold, /*InsnID*/1,
23993 // (intrinsic_wo_chain:{ *:[v16i8] } 2092:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
23994 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
23996 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
23997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms8,
23998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
23999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24000 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24001 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24002 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24003 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24004 GIR_EraseFromParent, /*InsnID*/0,
24005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24006 // GIR_Coverage, 3888,
24007 GIR_Done,
24008 // Label 1282: @61552
24009 GIM_Try, /*On fail goto*//*Label 1283*/ 61638, // Rule ID 3890 //
24010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24011 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24013 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24014 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24017 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24018 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24019 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
24020 // MIs[1] Operand 1
24021 // No operand predicates
24022 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24023 GIM_CheckIsSafeToFold, /*InsnID*/1,
24024 // (intrinsic_wo_chain:{ *:[v16i8] } 2092:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24025 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24026 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24027 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu8,
24029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24031 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24032 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24033 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24034 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24035 GIR_EraseFromParent, /*InsnID*/0,
24036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24037 // GIR_Coverage, 3890,
24038 GIR_Done,
24039 // Label 1283: @61638
24040 GIM_Try, /*On fail goto*//*Label 1284*/ 61724, // Rule ID 3892 //
24041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24042 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24043 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24044 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24045 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24049 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24050 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
24051 // MIs[1] Operand 1
24052 // No operand predicates
24053 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24054 GIM_CheckIsSafeToFold, /*InsnID*/1,
24055 // (intrinsic_wo_chain:{ *:[v8i16] } 2092:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24056 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24057 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24058 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms16,
24060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24062 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24063 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24064 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24065 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24066 GIR_EraseFromParent, /*InsnID*/0,
24067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24068 // GIR_Coverage, 3892,
24069 GIR_Done,
24070 // Label 1284: @61724
24071 GIM_Try, /*On fail goto*//*Label 1285*/ 61810, // Rule ID 3894 //
24072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24073 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24074 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24075 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24076 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24079 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24080 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24081 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
24082 // MIs[1] Operand 1
24083 // No operand predicates
24084 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24085 GIM_CheckIsSafeToFold, /*InsnID*/1,
24086 // (intrinsic_wo_chain:{ *:[v8i16] } 2092:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24087 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24088 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24089 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu16,
24091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24093 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24094 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24095 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24096 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24097 GIR_EraseFromParent, /*InsnID*/0,
24098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24099 // GIR_Coverage, 3894,
24100 GIR_Done,
24101 // Label 1285: @61810
24102 GIM_Try, /*On fail goto*//*Label 1286*/ 61896, // Rule ID 3896 //
24103 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24104 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24105 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24106 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24107 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24110 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24111 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24112 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
24113 // MIs[1] Operand 1
24114 // No operand predicates
24115 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24116 GIM_CheckIsSafeToFold, /*InsnID*/1,
24117 // (intrinsic_wo_chain:{ *:[v4i32] } 2092:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24118 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24119 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24120 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_imms32,
24122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24124 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24125 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24126 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24127 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24128 GIR_EraseFromParent, /*InsnID*/0,
24129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24130 // GIR_Coverage, 3896,
24131 GIR_Done,
24132 // Label 1286: @61896
24133 GIM_Try, /*On fail goto*//*Label 1287*/ 61982, // Rule ID 3898 //
24134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrshr_imm,
24135 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24137 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
24138 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24142 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24143 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
24144 // MIs[1] Operand 1
24145 // No operand predicates
24146 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24147 GIM_CheckIsSafeToFold, /*InsnID*/1,
24148 // (intrinsic_wo_chain:{ *:[v4i32] } 2092:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24149 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24150 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24151 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHR_immu32,
24153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
24155 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24156 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24157 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24158 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24159 GIR_EraseFromParent, /*InsnID*/0,
24160 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24161 // GIR_Coverage, 3898,
24162 GIR_Done,
24163 // Label 1287: @61982
24164 GIM_Try, /*On fail goto*//*Label 1288*/ 62067, // Rule ID 3988 //
24165 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24166 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24167 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24168 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24169 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24170 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24171 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24172 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
24173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24174 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24175 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24176 // MIs[1] Operand 1
24177 // No operand predicates
24178 GIM_CheckIsSafeToFold, /*InsnID*/1,
24179 // (intrinsic_wo_chain:{ *:[v8f16] } 2011:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
24180 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24181 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24182 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16_fix,
24184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24186 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24187 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24188 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24189 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24190 GIR_EraseFromParent, /*InsnID*/0,
24191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24192 // GIR_Coverage, 3988,
24193 GIR_Done,
24194 // Label 1288: @62067
24195 GIM_Try, /*On fail goto*//*Label 1289*/ 62152, // Rule ID 3990 //
24196 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24197 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24198 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24199 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24200 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24201 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24203 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
24204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24205 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24206 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24207 // MIs[1] Operand 1
24208 // No operand predicates
24209 GIM_CheckIsSafeToFold, /*InsnID*/1,
24210 // (intrinsic_wo_chain:{ *:[v8i16] } 2011:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
24211 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24212 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24213 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16_fix,
24215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24217 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24218 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24219 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24220 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24221 GIR_EraseFromParent, /*InsnID*/0,
24222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24223 // GIR_Coverage, 3990,
24224 GIR_Done,
24225 // Label 1289: @62152
24226 GIM_Try, /*On fail goto*//*Label 1290*/ 62237, // Rule ID 3992 //
24227 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24228 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24229 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24230 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24231 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24232 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24234 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24236 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24237 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24238 // MIs[1] Operand 1
24239 // No operand predicates
24240 GIM_CheckIsSafeToFold, /*InsnID*/1,
24241 // (intrinsic_wo_chain:{ *:[v8f16] } 2011:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
24242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24244 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16_fix,
24246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24248 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24249 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24250 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24251 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24252 GIR_EraseFromParent, /*InsnID*/0,
24253 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24254 // GIR_Coverage, 3992,
24255 GIR_Done,
24256 // Label 1290: @62237
24257 GIM_Try, /*On fail goto*//*Label 1291*/ 62322, // Rule ID 3994 //
24258 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24259 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24260 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24261 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24262 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24263 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24265 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24267 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24268 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24269 // MIs[1] Operand 1
24270 // No operand predicates
24271 GIM_CheckIsSafeToFold, /*InsnID*/1,
24272 // (intrinsic_wo_chain:{ *:[v8i16] } 2011:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
24273 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24274 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24275 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16_fix,
24277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24279 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24280 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24281 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24282 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24283 GIR_EraseFromParent, /*InsnID*/0,
24284 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24285 // GIR_Coverage, 3994,
24286 GIR_Done,
24287 // Label 1291: @62322
24288 GIM_Try, /*On fail goto*//*Label 1292*/ 62407, // Rule ID 3996 //
24289 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24290 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24291 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24292 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24293 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24294 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24296 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
24297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24299 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24300 // MIs[1] Operand 1
24301 // No operand predicates
24302 GIM_CheckIsSafeToFold, /*InsnID*/1,
24303 // (intrinsic_wo_chain:{ *:[v4f32] } 2011:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
24304 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24305 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24306 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32_fix,
24308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24310 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24311 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24312 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24313 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24314 GIR_EraseFromParent, /*InsnID*/0,
24315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24316 // GIR_Coverage, 3996,
24317 GIR_Done,
24318 // Label 1292: @62407
24319 GIM_Try, /*On fail goto*//*Label 1293*/ 62492, // Rule ID 3998 //
24320 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24322 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24323 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24324 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24325 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24327 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
24328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24330 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24331 // MIs[1] Operand 1
24332 // No operand predicates
24333 GIM_CheckIsSafeToFold, /*InsnID*/1,
24334 // (intrinsic_wo_chain:{ *:[v4i32] } 2011:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
24335 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24336 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24337 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32_fix,
24339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24341 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24342 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24343 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24344 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24345 GIR_EraseFromParent, /*InsnID*/0,
24346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24347 // GIR_Coverage, 3998,
24348 GIR_Done,
24349 // Label 1293: @62492
24350 GIM_Try, /*On fail goto*//*Label 1294*/ 62577, // Rule ID 4000 //
24351 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24353 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24355 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24356 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24358 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24360 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24361 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24362 // MIs[1] Operand 1
24363 // No operand predicates
24364 GIM_CheckIsSafeToFold, /*InsnID*/1,
24365 // (intrinsic_wo_chain:{ *:[v4f32] } 2011:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
24366 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24367 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24368 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32_fix,
24370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24372 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24373 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24374 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24375 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24376 GIR_EraseFromParent, /*InsnID*/0,
24377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24378 // GIR_Coverage, 4000,
24379 GIR_Done,
24380 // Label 1294: @62577
24381 GIM_Try, /*On fail goto*//*Label 1295*/ 62662, // Rule ID 4002 //
24382 GIM_CheckFeatures, GIFBS_HasMVEFloat,
24383 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_fix,
24384 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24385 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24386 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24387 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24389 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
24390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24391 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24392 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
24393 // MIs[1] Operand 1
24394 // No operand predicates
24395 GIM_CheckIsSafeToFold, /*InsnID*/1,
24396 // (intrinsic_wo_chain:{ *:[v4i32] } 2011:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
24397 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24398 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24399 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24400 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32_fix,
24401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
24403 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
24404 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24405 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24406 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24407 GIR_EraseFromParent, /*InsnID*/0,
24408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24409 // GIR_Coverage, 4002,
24410 GIR_Done,
24411 // Label 1295: @62662
24412 GIM_Try, /*On fail goto*//*Label 1296*/ 62729, // Rule ID 3115 //
24413 GIM_CheckFeatures, GIFBS_HasMVEInt,
24414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
24415 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24416 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24417 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24418 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24422 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24423 // (intrinsic_wo_chain:{ *:[i32] } 1958:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs8,
24425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24428 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24429 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24430 GIR_EraseFromParent, /*InsnID*/0,
24431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24432 // GIR_Coverage, 3115,
24433 GIR_Done,
24434 // Label 1296: @62729
24435 GIM_Try, /*On fail goto*//*Label 1297*/ 62796, // Rule ID 3117 //
24436 GIM_CheckFeatures, GIFBS_HasMVEInt,
24437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
24438 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24439 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24440 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24441 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24445 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24446 // (intrinsic_wo_chain:{ *:[i32] } 1958:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs16,
24448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24451 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24452 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24453 GIR_EraseFromParent, /*InsnID*/0,
24454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24455 // GIR_Coverage, 3117,
24456 GIR_Done,
24457 // Label 1297: @62796
24458 GIM_Try, /*On fail goto*//*Label 1298*/ 62863, // Rule ID 3119 //
24459 GIM_CheckFeatures, GIFBS_HasMVEInt,
24460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
24461 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24462 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24463 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24464 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24468 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24469 // (intrinsic_wo_chain:{ *:[i32] } 1958:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVs32,
24471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24474 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24475 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24476 GIR_EraseFromParent, /*InsnID*/0,
24477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24478 // GIR_Coverage, 3119,
24479 GIR_Done,
24480 // Label 1298: @62863
24481 GIM_Try, /*On fail goto*//*Label 1299*/ 62930, // Rule ID 3121 //
24482 GIM_CheckFeatures, GIFBS_HasMVEInt,
24483 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
24484 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24485 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24486 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24487 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24491 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24492 // (intrinsic_wo_chain:{ *:[i32] } 1958:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24493 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu8,
24494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24497 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24498 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24499 GIR_EraseFromParent, /*InsnID*/0,
24500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24501 // GIR_Coverage, 3121,
24502 GIR_Done,
24503 // Label 1299: @62930
24504 GIM_Try, /*On fail goto*//*Label 1300*/ 62997, // Rule ID 3123 //
24505 GIM_CheckFeatures, GIFBS_HasMVEInt,
24506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
24507 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24508 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24509 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24510 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24514 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24515 // (intrinsic_wo_chain:{ *:[i32] } 1958:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24516 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu16,
24517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24520 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24521 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24522 GIR_EraseFromParent, /*InsnID*/0,
24523 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24524 // GIR_Coverage, 3123,
24525 GIR_Done,
24526 // Label 1300: @62997
24527 GIM_Try, /*On fail goto*//*Label 1301*/ 63064, // Rule ID 3125 //
24528 GIM_CheckFeatures, GIFBS_HasMVEInt,
24529 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_minv,
24530 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24531 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24532 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24533 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24537 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24538 // (intrinsic_wo_chain:{ *:[i32] } 1958:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINVu32,
24540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24543 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24544 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24545 GIR_EraseFromParent, /*InsnID*/0,
24546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24547 // GIR_Coverage, 3125,
24548 GIR_Done,
24549 // Label 1301: @63064
24550 GIM_Try, /*On fail goto*//*Label 1302*/ 63131, // Rule ID 3127 //
24551 GIM_CheckFeatures, GIFBS_HasMVEInt,
24552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
24553 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24555 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24556 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24560 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24561 // (intrinsic_wo_chain:{ *:[i32] } 1949:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs8,
24563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24566 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24567 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24568 GIR_EraseFromParent, /*InsnID*/0,
24569 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24570 // GIR_Coverage, 3127,
24571 GIR_Done,
24572 // Label 1302: @63131
24573 GIM_Try, /*On fail goto*//*Label 1303*/ 63198, // Rule ID 3129 //
24574 GIM_CheckFeatures, GIFBS_HasMVEInt,
24575 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
24576 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24577 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24578 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24579 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24583 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24584 // (intrinsic_wo_chain:{ *:[i32] } 1949:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs16,
24586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24589 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24590 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24591 GIR_EraseFromParent, /*InsnID*/0,
24592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24593 // GIR_Coverage, 3129,
24594 GIR_Done,
24595 // Label 1303: @63198
24596 GIM_Try, /*On fail goto*//*Label 1304*/ 63265, // Rule ID 3131 //
24597 GIM_CheckFeatures, GIFBS_HasMVEInt,
24598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
24599 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24601 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24602 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24606 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24607 // (intrinsic_wo_chain:{ *:[i32] } 1949:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVs32,
24609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24612 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24613 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24614 GIR_EraseFromParent, /*InsnID*/0,
24615 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24616 // GIR_Coverage, 3131,
24617 GIR_Done,
24618 // Label 1304: @63265
24619 GIM_Try, /*On fail goto*//*Label 1305*/ 63332, // Rule ID 3133 //
24620 GIM_CheckFeatures, GIFBS_HasMVEInt,
24621 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
24622 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24623 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24624 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24625 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24629 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24630 // (intrinsic_wo_chain:{ *:[i32] } 1949:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24631 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu8,
24632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24635 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24636 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24637 GIR_EraseFromParent, /*InsnID*/0,
24638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24639 // GIR_Coverage, 3133,
24640 GIR_Done,
24641 // Label 1305: @63332
24642 GIM_Try, /*On fail goto*//*Label 1306*/ 63399, // Rule ID 3135 //
24643 GIM_CheckFeatures, GIFBS_HasMVEInt,
24644 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
24645 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24646 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24647 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24648 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24652 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24653 // (intrinsic_wo_chain:{ *:[i32] } 1949:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu16,
24655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24658 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24659 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24660 GIR_EraseFromParent, /*InsnID*/0,
24661 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24662 // GIR_Coverage, 3135,
24663 GIR_Done,
24664 // Label 1306: @63399
24665 GIM_Try, /*On fail goto*//*Label 1307*/ 63466, // Rule ID 3137 //
24666 GIM_CheckFeatures, GIFBS_HasMVEInt,
24667 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_maxv,
24668 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24669 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
24670 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24671 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
24674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24675 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24676 // (intrinsic_wo_chain:{ *:[i32] } 1949:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXVu32,
24678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
24679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // prev
24680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vec
24681 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24682 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24683 GIR_EraseFromParent, /*InsnID*/0,
24684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24685 // GIR_Coverage, 3137,
24686 GIR_Done,
24687 // Label 1307: @63466
24688 GIM_Try, /*On fail goto*//*Label 1308*/ 63547, // Rule ID 3538 //
24689 GIM_CheckFeatures, GIFBS_HasMVEInt,
24690 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
24691 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24692 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24693 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24694 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24698 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24699 // (intrinsic_wo_chain:{ *:[v16i8] } 1995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24700 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24701 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24702 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs8,
24704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24707 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24708 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24709 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24710 GIR_EraseFromParent, /*InsnID*/0,
24711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24712 // GIR_Coverage, 3538,
24713 GIR_Done,
24714 // Label 1308: @63547
24715 GIM_Try, /*On fail goto*//*Label 1309*/ 63628, // Rule ID 3540 //
24716 GIM_CheckFeatures, GIFBS_HasMVEInt,
24717 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
24718 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24719 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24720 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24721 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24725 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24726 // (intrinsic_wo_chain:{ *:[v8i16] } 1995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24727 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24728 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24729 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs16,
24731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24734 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24735 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24736 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24737 GIR_EraseFromParent, /*InsnID*/0,
24738 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24739 // GIR_Coverage, 3540,
24740 GIR_Done,
24741 // Label 1309: @63628
24742 GIM_Try, /*On fail goto*//*Label 1310*/ 63709, // Rule ID 3542 //
24743 GIM_CheckFeatures, GIFBS_HasMVEInt,
24744 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
24745 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24746 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24747 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24748 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24752 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24753 // (intrinsic_wo_chain:{ *:[v4i32] } 1995:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24754 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24755 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24756 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDs32,
24758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24761 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24762 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24763 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24764 GIR_EraseFromParent, /*InsnID*/0,
24765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24766 // GIR_Coverage, 3542,
24767 GIR_Done,
24768 // Label 1310: @63709
24769 GIM_Try, /*On fail goto*//*Label 1311*/ 63790, // Rule ID 3544 //
24770 GIM_CheckFeatures, GIFBS_HasMVEInt,
24771 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
24772 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24773 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24774 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24775 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24779 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24780 // (intrinsic_wo_chain:{ *:[v16i8] } 1995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24781 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24782 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24783 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu8,
24785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24788 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24789 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24790 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24791 GIR_EraseFromParent, /*InsnID*/0,
24792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24793 // GIR_Coverage, 3544,
24794 GIR_Done,
24795 // Label 1311: @63790
24796 GIM_Try, /*On fail goto*//*Label 1312*/ 63871, // Rule ID 3546 //
24797 GIM_CheckFeatures, GIFBS_HasMVEInt,
24798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
24799 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24801 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24802 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24806 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24807 // (intrinsic_wo_chain:{ *:[v8i16] } 1995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24808 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24809 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24810 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu16,
24812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24815 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24816 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24817 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24818 GIR_EraseFromParent, /*InsnID*/0,
24819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24820 // GIR_Coverage, 3546,
24821 GIR_Done,
24822 // Label 1312: @63871
24823 GIM_Try, /*On fail goto*//*Label 1313*/ 63952, // Rule ID 3548 //
24824 GIM_CheckFeatures, GIFBS_HasMVEInt,
24825 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
24826 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24827 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24828 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24829 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24833 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24834 // (intrinsic_wo_chain:{ *:[v4i32] } 1995:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24835 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24836 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24837 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDu32,
24839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24842 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24843 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24844 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24845 GIR_EraseFromParent, /*InsnID*/0,
24846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24847 // GIR_Coverage, 3548,
24848 GIR_Done,
24849 // Label 1313: @63952
24850 GIM_Try, /*On fail goto*//*Label 1314*/ 64033, // Rule ID 3550 //
24851 GIM_CheckFeatures, GIFBS_HasMVEInt,
24852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
24853 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24854 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24855 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24856 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24860 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24861 // (intrinsic_wo_chain:{ *:[v16i8] } 2081:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24862 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24863 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24864 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs8,
24866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24869 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24870 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24871 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24872 GIR_EraseFromParent, /*InsnID*/0,
24873 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24874 // GIR_Coverage, 3550,
24875 GIR_Done,
24876 // Label 1314: @64033
24877 GIM_Try, /*On fail goto*//*Label 1315*/ 64114, // Rule ID 3552 //
24878 GIM_CheckFeatures, GIFBS_HasMVEInt,
24879 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
24880 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24881 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24882 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24883 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24887 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24888 // (intrinsic_wo_chain:{ *:[v8i16] } 2081:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24889 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24890 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24891 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs16,
24893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24896 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24897 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24898 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24899 GIR_EraseFromParent, /*InsnID*/0,
24900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24901 // GIR_Coverage, 3552,
24902 GIR_Done,
24903 // Label 1315: @64114
24904 GIM_Try, /*On fail goto*//*Label 1316*/ 64195, // Rule ID 3554 //
24905 GIM_CheckFeatures, GIFBS_HasMVEInt,
24906 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
24907 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24909 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24910 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24914 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
24915 // (intrinsic_wo_chain:{ *:[v4i32] } 2081:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24916 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24917 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24918 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDs32,
24920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24923 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24924 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24925 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24926 GIR_EraseFromParent, /*InsnID*/0,
24927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24928 // GIR_Coverage, 3554,
24929 GIR_Done,
24930 // Label 1316: @64195
24931 GIM_Try, /*On fail goto*//*Label 1317*/ 64276, // Rule ID 3556 //
24932 GIM_CheckFeatures, GIFBS_HasMVEInt,
24933 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
24934 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
24935 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
24936 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
24937 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24941 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24942 // (intrinsic_wo_chain:{ *:[v16i8] } 2081:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24943 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24944 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24945 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu8,
24947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24950 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24951 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24952 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24953 GIR_EraseFromParent, /*InsnID*/0,
24954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24955 // GIR_Coverage, 3556,
24956 GIR_Done,
24957 // Label 1317: @64276
24958 GIM_Try, /*On fail goto*//*Label 1318*/ 64357, // Rule ID 3558 //
24959 GIM_CheckFeatures, GIFBS_HasMVEInt,
24960 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
24961 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
24962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
24963 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
24964 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24968 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24969 // (intrinsic_wo_chain:{ *:[v8i16] } 2081:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24970 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24971 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24972 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
24973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu16,
24974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
24975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
24976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
24977 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
24978 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
24979 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
24980 GIR_EraseFromParent, /*InsnID*/0,
24981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24982 // GIR_Coverage, 3558,
24983 GIR_Done,
24984 // Label 1318: @64357
24985 GIM_Try, /*On fail goto*//*Label 1319*/ 64438, // Rule ID 3560 //
24986 GIM_CheckFeatures, GIFBS_HasMVEInt,
24987 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrhadd,
24988 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
24989 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
24990 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
24991 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
24992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
24993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
24994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
24995 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
24996 // (intrinsic_wo_chain:{ *:[v4i32] } 2081:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24997 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24998 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
24999 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRHADDu32,
25001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25004 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25005 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25006 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25007 GIR_EraseFromParent, /*InsnID*/0,
25008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25009 // GIR_Coverage, 3560,
25010 GIR_Done,
25011 // Label 1319: @64438
25012 GIM_Try, /*On fail goto*//*Label 1320*/ 64519, // Rule ID 3568 //
25013 GIM_CheckFeatures, GIFBS_HasMVEInt,
25014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25015 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25016 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25018 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25022 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25023 // (intrinsic_wo_chain:{ *:[v16i8] } 2030:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25024 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25025 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25026 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs8,
25028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25031 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25032 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25033 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25034 GIR_EraseFromParent, /*InsnID*/0,
25035 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25036 // GIR_Coverage, 3568,
25037 GIR_Done,
25038 // Label 1320: @64519
25039 GIM_Try, /*On fail goto*//*Label 1321*/ 64600, // Rule ID 3571 //
25040 GIM_CheckFeatures, GIFBS_HasMVEInt,
25041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25042 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25043 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25044 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25045 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25049 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25050 // (intrinsic_wo_chain:{ *:[v8i16] } 2030:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25051 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25052 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25053 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs16,
25055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25058 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25059 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25060 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25061 GIR_EraseFromParent, /*InsnID*/0,
25062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25063 // GIR_Coverage, 3571,
25064 GIR_Done,
25065 // Label 1321: @64600
25066 GIM_Try, /*On fail goto*//*Label 1322*/ 64681, // Rule ID 3574 //
25067 GIM_CheckFeatures, GIFBS_HasMVEInt,
25068 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25069 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25070 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25071 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25072 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25076 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25077 // (intrinsic_wo_chain:{ *:[v4i32] } 2030:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25078 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25079 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25080 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDs32,
25082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25085 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25086 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25087 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25088 GIR_EraseFromParent, /*InsnID*/0,
25089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25090 // GIR_Coverage, 3574,
25091 GIR_Done,
25092 // Label 1322: @64681
25093 GIM_Try, /*On fail goto*//*Label 1323*/ 64762, // Rule ID 3577 //
25094 GIM_CheckFeatures, GIFBS_HasMVEInt,
25095 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25096 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25097 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25098 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25099 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25103 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25104 // (intrinsic_wo_chain:{ *:[v16i8] } 2030:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25105 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25106 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25107 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu8,
25109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25112 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25113 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25114 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25115 GIR_EraseFromParent, /*InsnID*/0,
25116 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25117 // GIR_Coverage, 3577,
25118 GIR_Done,
25119 // Label 1323: @64762
25120 GIM_Try, /*On fail goto*//*Label 1324*/ 64843, // Rule ID 3580 //
25121 GIM_CheckFeatures, GIFBS_HasMVEInt,
25122 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25123 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25124 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25125 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25126 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25130 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25131 // (intrinsic_wo_chain:{ *:[v8i16] } 2030:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25132 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25134 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu16,
25136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25139 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25140 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25141 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25142 GIR_EraseFromParent, /*InsnID*/0,
25143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25144 // GIR_Coverage, 3580,
25145 GIR_Done,
25146 // Label 1324: @64843
25147 GIM_Try, /*On fail goto*//*Label 1325*/ 64924, // Rule ID 3583 //
25148 GIM_CheckFeatures, GIFBS_HasMVEInt,
25149 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhadd,
25150 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25151 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25152 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25153 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25157 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25158 // (intrinsic_wo_chain:{ *:[v4i32] } 2030:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25159 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25160 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25161 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHADDu32,
25163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25166 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25167 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25168 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25169 GIR_EraseFromParent, /*InsnID*/0,
25170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25171 // GIR_Coverage, 3583,
25172 GIR_Done,
25173 // Label 1325: @64924
25174 GIM_Try, /*On fail goto*//*Label 1326*/ 65005, // Rule ID 3586 //
25175 GIM_CheckFeatures, GIFBS_HasMVEInt,
25176 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25177 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25178 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25179 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25180 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25184 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25185 // (intrinsic_wo_chain:{ *:[v16i8] } 2031:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25186 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25187 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25188 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs8,
25190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25193 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25194 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25195 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25196 GIR_EraseFromParent, /*InsnID*/0,
25197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25198 // GIR_Coverage, 3586,
25199 GIR_Done,
25200 // Label 1326: @65005
25201 GIM_Try, /*On fail goto*//*Label 1327*/ 65086, // Rule ID 3589 //
25202 GIM_CheckFeatures, GIFBS_HasMVEInt,
25203 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25204 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25205 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25206 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25207 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25211 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25212 // (intrinsic_wo_chain:{ *:[v8i16] } 2031:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25213 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25215 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs16,
25217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25220 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25221 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25222 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25223 GIR_EraseFromParent, /*InsnID*/0,
25224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25225 // GIR_Coverage, 3589,
25226 GIR_Done,
25227 // Label 1327: @65086
25228 GIM_Try, /*On fail goto*//*Label 1328*/ 65167, // Rule ID 3592 //
25229 GIM_CheckFeatures, GIFBS_HasMVEInt,
25230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25231 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25233 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25234 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25238 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25239 // (intrinsic_wo_chain:{ *:[v4i32] } 2031:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25240 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25241 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25242 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25243 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBs32,
25244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25247 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25248 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25249 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25250 GIR_EraseFromParent, /*InsnID*/0,
25251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25252 // GIR_Coverage, 3592,
25253 GIR_Done,
25254 // Label 1328: @65167
25255 GIM_Try, /*On fail goto*//*Label 1329*/ 65248, // Rule ID 3595 //
25256 GIM_CheckFeatures, GIFBS_HasMVEInt,
25257 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25258 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25259 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25260 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25261 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25265 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25266 // (intrinsic_wo_chain:{ *:[v16i8] } 2031:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25267 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25268 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25269 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu8,
25271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25274 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25275 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25276 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25277 GIR_EraseFromParent, /*InsnID*/0,
25278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25279 // GIR_Coverage, 3595,
25280 GIR_Done,
25281 // Label 1329: @65248
25282 GIM_Try, /*On fail goto*//*Label 1330*/ 65329, // Rule ID 3598 //
25283 GIM_CheckFeatures, GIFBS_HasMVEInt,
25284 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25285 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25286 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25287 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25288 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25292 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25293 // (intrinsic_wo_chain:{ *:[v8i16] } 2031:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25294 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25295 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25296 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu16,
25298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25301 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25302 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25303 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25304 GIR_EraseFromParent, /*InsnID*/0,
25305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25306 // GIR_Coverage, 3598,
25307 GIR_Done,
25308 // Label 1330: @65329
25309 GIM_Try, /*On fail goto*//*Label 1331*/ 65410, // Rule ID 3601 //
25310 GIM_CheckFeatures, GIFBS_HasMVEInt,
25311 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vhsub,
25312 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25313 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25314 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25315 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25319 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25320 // (intrinsic_wo_chain:{ *:[v4i32] } 2031:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25321 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25322 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25323 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHSUBu32,
25325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25328 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25329 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25330 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25331 GIR_EraseFromParent, /*InsnID*/0,
25332 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25333 // GIR_Coverage, 3601,
25334 GIR_Done,
25335 // Label 1331: @65410
25336 GIM_Try, /*On fail goto*//*Label 1332*/ 65491, // Rule ID 3982 //
25337 GIM_CheckFeatures, GIFBS_HasMVEFloat,
25338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25339 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25340 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25341 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25342 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25346 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25347 // (intrinsic_wo_chain:{ *:[v4f32] } 1995:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
25348 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25349 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25350 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf32,
25352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25355 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25356 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25357 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25358 GIR_EraseFromParent, /*InsnID*/0,
25359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25360 // GIR_Coverage, 3982,
25361 GIR_Done,
25362 // Label 1332: @65491
25363 GIM_Try, /*On fail goto*//*Label 1333*/ 65572, // Rule ID 3984 //
25364 GIM_CheckFeatures, GIFBS_HasMVEFloat,
25365 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabd,
25366 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25367 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25368 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25369 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25373 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25374 // (intrinsic_wo_chain:{ *:[v8f16] } 1995:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
25375 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25376 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25377 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf16,
25379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25382 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25383 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25384 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25385 GIR_EraseFromParent, /*InsnID*/0,
25386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25387 // GIR_Coverage, 3984,
25388 GIR_Done,
25389 // Label 1333: @65572
25390 GIM_Try, /*On fail goto*//*Label 1334*/ 65653, // Rule ID 4343 //
25391 GIM_CheckFeatures, GIFBS_HasMVEInt,
25392 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
25393 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25395 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25396 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25400 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25401 // (intrinsic_wo_chain:{ *:[v8i16] } 2058:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25402 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25403 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25404 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp8,
25406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25409 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25410 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25411 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25412 GIR_EraseFromParent, /*InsnID*/0,
25413 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25414 // GIR_Coverage, 4343,
25415 GIR_Done,
25416 // Label 1334: @65653
25417 GIM_Try, /*On fail goto*//*Label 1335*/ 65734, // Rule ID 4345 //
25418 GIM_CheckFeatures, GIFBS_HasMVEInt,
25419 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
25420 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25421 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25422 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25423 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25427 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25428 // (intrinsic_wo_chain:{ *:[v8i16] } 2058:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25429 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25430 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25431 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp8,
25433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25436 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25437 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25438 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25439 GIR_EraseFromParent, /*InsnID*/0,
25440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25441 // GIR_Coverage, 4345,
25442 GIR_Done,
25443 // Label 1335: @65734
25444 GIM_Try, /*On fail goto*//*Label 1336*/ 65815, // Rule ID 4347 //
25445 GIM_CheckFeatures, GIFBS_HasMVEInt,
25446 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
25447 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25449 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25450 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25454 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25455 // (intrinsic_wo_chain:{ *:[v4i32] } 2058:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25456 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25457 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25458 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBp16,
25460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25463 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25464 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25465 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25466 GIR_EraseFromParent, /*InsnID*/0,
25467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25468 // GIR_Coverage, 4347,
25469 GIR_Done,
25470 // Label 1336: @65815
25471 GIM_Try, /*On fail goto*//*Label 1337*/ 65896, // Rule ID 4349 //
25472 GIM_CheckFeatures, GIFBS_HasMVEInt,
25473 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull_poly,
25474 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25475 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25476 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25477 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25481 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25482 // (intrinsic_wo_chain:{ *:[v4i32] } 2058:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25483 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25484 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25485 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTp16,
25487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25490 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25491 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25492 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25493 GIR_EraseFromParent, /*InsnID*/0,
25494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25495 // GIR_Coverage, 4349,
25496 GIR_Done,
25497 // Label 1337: @65896
25498 GIM_Try, /*On fail goto*//*Label 1338*/ 65977, // Rule ID 4375 //
25499 GIM_CheckFeatures, GIFBS_HasMVEInt,
25500 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
25501 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25502 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25503 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25504 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25508 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25509 // (intrinsic_wo_chain:{ *:[v16i8] } 2056:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25510 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25511 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25512 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs8,
25514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25517 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25518 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25519 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25520 GIR_EraseFromParent, /*InsnID*/0,
25521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25522 // GIR_Coverage, 4375,
25523 GIR_Done,
25524 // Label 1338: @65977
25525 GIM_Try, /*On fail goto*//*Label 1339*/ 66058, // Rule ID 4377 //
25526 GIM_CheckFeatures, GIFBS_HasMVEInt,
25527 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
25528 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25529 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25530 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25531 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25535 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25536 // (intrinsic_wo_chain:{ *:[v8i16] } 2056:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25537 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25538 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25539 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs16,
25541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25544 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25545 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25547 GIR_EraseFromParent, /*InsnID*/0,
25548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25549 // GIR_Coverage, 4377,
25550 GIR_Done,
25551 // Label 1339: @66058
25552 GIM_Try, /*On fail goto*//*Label 1340*/ 66139, // Rule ID 4379 //
25553 GIM_CheckFeatures, GIFBS_HasMVEInt,
25554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
25555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25557 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25558 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25562 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25563 // (intrinsic_wo_chain:{ *:[v4i32] } 2056:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25564 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25565 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25566 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHs32,
25568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25571 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25572 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25573 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25574 GIR_EraseFromParent, /*InsnID*/0,
25575 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25576 // GIR_Coverage, 4379,
25577 GIR_Done,
25578 // Label 1340: @66139
25579 GIM_Try, /*On fail goto*//*Label 1341*/ 66220, // Rule ID 4381 //
25580 GIM_CheckFeatures, GIFBS_HasMVEInt,
25581 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
25582 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25583 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25584 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25585 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25589 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25590 // (intrinsic_wo_chain:{ *:[v16i8] } 2056:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25591 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25592 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25593 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu8,
25595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25598 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25599 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25600 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25601 GIR_EraseFromParent, /*InsnID*/0,
25602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25603 // GIR_Coverage, 4381,
25604 GIR_Done,
25605 // Label 1341: @66220
25606 GIM_Try, /*On fail goto*//*Label 1342*/ 66301, // Rule ID 4383 //
25607 GIM_CheckFeatures, GIFBS_HasMVEInt,
25608 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
25609 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25610 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25611 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25612 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25616 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25617 // (intrinsic_wo_chain:{ *:[v8i16] } 2056:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25618 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25619 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25620 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu16,
25622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25625 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25626 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25627 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25628 GIR_EraseFromParent, /*InsnID*/0,
25629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25630 // GIR_Coverage, 4383,
25631 GIR_Done,
25632 // Label 1342: @66301
25633 GIM_Try, /*On fail goto*//*Label 1343*/ 66382, // Rule ID 4385 //
25634 GIM_CheckFeatures, GIFBS_HasMVEInt,
25635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmulh,
25636 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25637 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25638 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25639 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25643 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25644 // (intrinsic_wo_chain:{ *:[v4i32] } 2056:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25645 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25646 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25647 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULHu32,
25649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25652 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25653 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25654 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25655 GIR_EraseFromParent, /*InsnID*/0,
25656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25657 // GIR_Coverage, 4385,
25658 GIR_Done,
25659 // Label 1343: @66382
25660 GIM_Try, /*On fail goto*//*Label 1344*/ 66463, // Rule ID 4387 //
25661 GIM_CheckFeatures, GIFBS_HasMVEInt,
25662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
25663 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25664 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25665 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25666 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25670 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25671 // (intrinsic_wo_chain:{ *:[v16i8] } 2091:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25672 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25673 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25674 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs8,
25676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25679 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25680 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25681 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25682 GIR_EraseFromParent, /*InsnID*/0,
25683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25684 // GIR_Coverage, 4387,
25685 GIR_Done,
25686 // Label 1344: @66463
25687 GIM_Try, /*On fail goto*//*Label 1345*/ 66544, // Rule ID 4389 //
25688 GIM_CheckFeatures, GIFBS_HasMVEInt,
25689 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
25690 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25691 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25692 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25693 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25697 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25698 // (intrinsic_wo_chain:{ *:[v8i16] } 2091:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25699 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs16,
25703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25706 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25707 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25708 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25709 GIR_EraseFromParent, /*InsnID*/0,
25710 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25711 // GIR_Coverage, 4389,
25712 GIR_Done,
25713 // Label 1345: @66544
25714 GIM_Try, /*On fail goto*//*Label 1346*/ 66625, // Rule ID 4391 //
25715 GIM_CheckFeatures, GIFBS_HasMVEInt,
25716 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
25717 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25718 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25719 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25720 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25724 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25725 // (intrinsic_wo_chain:{ *:[v4i32] } 2091:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25726 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25727 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25728 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHs32,
25730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25733 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25734 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25735 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25736 GIR_EraseFromParent, /*InsnID*/0,
25737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25738 // GIR_Coverage, 4391,
25739 GIR_Done,
25740 // Label 1346: @66625
25741 GIM_Try, /*On fail goto*//*Label 1347*/ 66706, // Rule ID 4393 //
25742 GIM_CheckFeatures, GIFBS_HasMVEInt,
25743 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
25744 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25745 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25746 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25747 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25751 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25752 // (intrinsic_wo_chain:{ *:[v16i8] } 2091:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25753 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25754 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25755 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu8,
25757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25760 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25761 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25762 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25763 GIR_EraseFromParent, /*InsnID*/0,
25764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25765 // GIR_Coverage, 4393,
25766 GIR_Done,
25767 // Label 1347: @66706
25768 GIM_Try, /*On fail goto*//*Label 1348*/ 66787, // Rule ID 4395 //
25769 GIM_CheckFeatures, GIFBS_HasMVEInt,
25770 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
25771 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25773 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25774 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25778 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25779 // (intrinsic_wo_chain:{ *:[v8i16] } 2091:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25780 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25781 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25782 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu16,
25784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25787 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25788 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25789 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25790 GIR_EraseFromParent, /*InsnID*/0,
25791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25792 // GIR_Coverage, 4395,
25793 GIR_Done,
25794 // Label 1348: @66787
25795 GIM_Try, /*On fail goto*//*Label 1349*/ 66868, // Rule ID 4397 //
25796 GIM_CheckFeatures, GIFBS_HasMVEInt,
25797 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vrmulh,
25798 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25799 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25800 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25801 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25805 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25806 // (intrinsic_wo_chain:{ *:[v4i32] } 2091:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25807 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25808 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25809 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25810 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRMULHu32,
25811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25814 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25815 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25816 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25817 GIR_EraseFromParent, /*InsnID*/0,
25818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25819 // GIR_Coverage, 4397,
25820 GIR_Done,
25821 // Label 1349: @66868
25822 GIM_Try, /*On fail goto*//*Label 1350*/ 66935, // Rule ID 4449 //
25823 GIM_CheckFeatures, GIFBS_HasMVEFloat,
25824 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow,
25825 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25827 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25828 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25832 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25833 // (intrinsic_wo_chain:{ *:[v8f16] } 2014:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
25834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32bh,
25835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
25837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25838 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25839 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25840 GIR_EraseFromParent, /*InsnID*/0,
25841 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25842 // GIR_Coverage, 4449,
25843 GIR_Done,
25844 // Label 1350: @66935
25845 GIM_Try, /*On fail goto*//*Label 1351*/ 67002, // Rule ID 4455 //
25846 GIM_CheckFeatures, GIFBS_HasMVEFloat,
25847 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcvt_narrow,
25848 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
25849 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25850 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25851 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25855 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25856 // (intrinsic_wo_chain:{ *:[v8f16] } 2014:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
25857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16f32th,
25858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
25860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25861 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25862 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25863 GIR_EraseFromParent, /*InsnID*/0,
25864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25865 // GIR_Coverage, 4455,
25866 GIR_Done,
25867 // Label 1351: @67002
25868 GIM_Try, /*On fail goto*//*Label 1352*/ 67083, // Rule ID 4473 //
25869 GIM_CheckFeatures, GIFBS_HasMVEInt,
25870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
25871 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25873 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25874 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25878 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25879 // (intrinsic_wo_chain:{ *:[v4i32] } 2066:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25880 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25881 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25882 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs16bh,
25884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25887 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25888 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25889 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25890 GIR_EraseFromParent, /*InsnID*/0,
25891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25892 // GIR_Coverage, 4473,
25893 GIR_Done,
25894 // Label 1352: @67083
25895 GIM_Try, /*On fail goto*//*Label 1353*/ 67164, // Rule ID 4475 //
25896 GIM_CheckFeatures, GIFBS_HasMVEInt,
25897 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
25898 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
25899 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
25900 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
25901 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25905 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25906 // (intrinsic_wo_chain:{ *:[v4i32] } 2066:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25907 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25908 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25909 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs16th,
25911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25914 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25915 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25916 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25917 GIR_EraseFromParent, /*InsnID*/0,
25918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25919 // GIR_Coverage, 4475,
25920 GIR_Done,
25921 // Label 1353: @67164
25922 GIM_Try, /*On fail goto*//*Label 1354*/ 67245, // Rule ID 4477 //
25923 GIM_CheckFeatures, GIFBS_HasMVEInt,
25924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
25925 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
25926 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25927 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25928 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25932 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
25933 // (intrinsic_wo_chain:{ *:[v2i64] } 2066:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25934 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25935 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25936 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs32bh,
25938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25941 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25942 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25943 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25944 GIR_EraseFromParent, /*InsnID*/0,
25945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25946 // GIR_Coverage, 4477,
25947 GIR_Done,
25948 // Label 1354: @67245
25949 GIM_Try, /*On fail goto*//*Label 1355*/ 67326, // Rule ID 4479 //
25950 GIM_CheckFeatures, GIFBS_HasMVEInt,
25951 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmull,
25952 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
25953 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
25954 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
25955 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25959 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
25960 // (intrinsic_wo_chain:{ *:[v2i64] } 2066:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25961 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25962 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
25963 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
25964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMULLs32th,
25965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
25967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
25968 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25969 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25970 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
25971 GIR_EraseFromParent, /*InsnID*/0,
25972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
25973 // GIR_Coverage, 4479,
25974 GIR_Done,
25975 // Label 1355: @67326
25976 GIM_Try, /*On fail goto*//*Label 1356*/ 67402, // Rule ID 3858 //
25977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
25978 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
25979 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
25980 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
25981 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
25982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
25983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
25984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
25985 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25986 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
25987 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_7,
25988 // MIs[1] Operand 1
25989 // No operand predicates
25990 GIM_CheckIsSafeToFold, /*InsnID*/1,
25991 // (intrinsic_wo_chain:{ *:[v16i8] } 2106:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
25992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm8,
25993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
25994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
25995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
25996 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25997 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
25998 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
25999 GIR_EraseFromParent, /*InsnID*/0,
26000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26001 // GIR_Coverage, 3858,
26002 GIR_Done,
26003 // Label 1356: @67402
26004 GIM_Try, /*On fail goto*//*Label 1357*/ 67478, // Rule ID 3860 //
26005 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
26006 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26007 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26008 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26009 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26013 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26014 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26015 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
26016 // MIs[1] Operand 1
26017 // No operand predicates
26018 GIM_CheckIsSafeToFold, /*InsnID*/1,
26019 // (intrinsic_wo_chain:{ *:[v8i16] } 2106:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
26020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm16,
26021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26024 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26025 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26026 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26027 GIR_EraseFromParent, /*InsnID*/0,
26028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26029 // GIR_Coverage, 3860,
26030 GIR_Done,
26031 // Label 1357: @67478
26032 GIM_Try, /*On fail goto*//*Label 1358*/ 67554, // Rule ID 3862 //
26033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsli,
26034 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26035 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26036 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26037 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26041 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26042 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26043 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
26044 // MIs[1] Operand 1
26045 // No operand predicates
26046 GIM_CheckIsSafeToFold, /*InsnID*/1,
26047 // (intrinsic_wo_chain:{ *:[v4i32] } 2106:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
26048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSLIimm32,
26049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26052 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26053 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26054 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26055 GIR_EraseFromParent, /*InsnID*/0,
26056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26057 // GIR_Coverage, 3862,
26058 GIR_Done,
26059 // Label 1358: @67554
26060 GIM_Try, /*On fail goto*//*Label 1359*/ 67630, // Rule ID 3864 //
26061 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
26062 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
26063 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
26064 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26065 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26070 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26071 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
26072 // MIs[1] Operand 1
26073 // No operand predicates
26074 GIM_CheckIsSafeToFold, /*InsnID*/1,
26075 // (intrinsic_wo_chain:{ *:[v16i8] } 2108:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) => (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
26076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm8,
26077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26080 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26081 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26082 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26083 GIR_EraseFromParent, /*InsnID*/0,
26084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26085 // GIR_Coverage, 3864,
26086 GIR_Done,
26087 // Label 1359: @67630
26088 GIM_Try, /*On fail goto*//*Label 1360*/ 67706, // Rule ID 3866 //
26089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
26090 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26091 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
26092 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26093 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26097 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26098 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26099 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
26100 // MIs[1] Operand 1
26101 // No operand predicates
26102 GIM_CheckIsSafeToFold, /*InsnID*/1,
26103 // (intrinsic_wo_chain:{ *:[v8i16] } 2108:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) => (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
26104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm16,
26105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26108 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26109 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26110 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26111 GIR_EraseFromParent, /*InsnID*/0,
26112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26113 // GIR_Coverage, 3866,
26114 GIR_Done,
26115 // Label 1360: @67706
26116 GIM_Try, /*On fail goto*//*Label 1361*/ 67782, // Rule ID 3868 //
26117 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vsri,
26118 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26119 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26120 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26121 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
26124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26126 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26127 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm32,
26128 // MIs[1] Operand 1
26129 // No operand predicates
26130 GIM_CheckIsSafeToFold, /*InsnID*/1,
26131 // (intrinsic_wo_chain:{ *:[v4i32] } 2108:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) => (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
26132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSRIimm32,
26133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
26135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
26136 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
26137 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26138 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26139 GIR_EraseFromParent, /*InsnID*/0,
26140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26141 // GIR_Coverage, 3868,
26142 GIR_Done,
26143 // Label 1361: @67782
26144 GIM_Try, /*On fail goto*//*Label 1362*/ 67871, // Rule ID 4315 //
26145 GIM_CheckFeatures, GIFBS_HasMVEFloat,
26146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq,
26147 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
26148 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26149 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26150 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26153 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26154 // MIs[1] Operand 1
26155 // No operand predicates
26156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
26158 GIM_CheckIsSafeToFold, /*InsnID*/1,
26159 // (intrinsic_wo_chain:{ *:[v8f16] } 2005:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
26160 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26161 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26162 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf16,
26164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
26167 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26168 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26169 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26170 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26171 GIR_EraseFromParent, /*InsnID*/0,
26172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26173 // GIR_Coverage, 4315,
26174 GIR_Done,
26175 // Label 1362: @67871
26176 GIM_Try, /*On fail goto*//*Label 1363*/ 67960, // Rule ID 4317 //
26177 GIM_CheckFeatures, GIFBS_HasMVEFloat,
26178 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmulq,
26179 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26180 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26181 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26182 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
26184 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26185 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
26186 // MIs[1] Operand 1
26187 // No operand predicates
26188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
26189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
26190 GIM_CheckIsSafeToFold, /*InsnID*/1,
26191 // (intrinsic_wo_chain:{ *:[v4f32] } 2005:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
26192 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26193 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
26194 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
26195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMULf32,
26196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
26197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
26198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qm
26199 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26200 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
26201 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26202 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
26203 GIR_EraseFromParent, /*InsnID*/0,
26204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26205 // GIR_Coverage, 4317,
26206 GIR_Done,
26207 // Label 1363: @67960
26208 GIM_Try, /*On fail goto*//*Label 1364*/ 68031, // Rule ID 146 //
26209 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
26210 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
26211 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26212 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26213 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26214 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
26216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26219 // (intrinsic_wo_chain:{ *:[i32] } 2336:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
26220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8,
26221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26225 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26226 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26227 GIR_EraseFromParent, /*InsnID*/0,
26228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26229 // GIR_Coverage, 146,
26230 GIR_Done,
26231 // Label 1364: @68031
26232 GIM_Try, /*On fail goto*//*Label 1365*/ 68102, // Rule ID 476 //
26233 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
26234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
26235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26238 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
26240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
26241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
26243 // (intrinsic_wo_chain:{ *:[i32] } 2336:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8,
26245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26249 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26250 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26251 GIR_EraseFromParent, /*InsnID*/0,
26252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26253 // GIR_Coverage, 476,
26254 GIR_Done,
26255 // Label 1365: @68102
26256 GIM_Try, /*On fail goto*//*Label 1366*/ 68173, // Rule ID 535 //
26257 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
26258 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
26259 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26260 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26261 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26262 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
26264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
26265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
26267 // (intrinsic_wo_chain:{ *:[i32] } 2281:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD,
26269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26273 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26274 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26275 GIR_EraseFromParent, /*InsnID*/0,
26276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26277 // GIR_Coverage, 535,
26278 GIR_Done,
26279 // Label 1366: @68173
26280 GIM_Try, /*On fail goto*//*Label 1367*/ 68244, // Rule ID 536 //
26281 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
26282 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
26283 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26284 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26285 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26286 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
26288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
26289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
26291 // (intrinsic_wo_chain:{ *:[i32] } 2282:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26292 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX,
26293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26297 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26298 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26299 GIR_EraseFromParent, /*InsnID*/0,
26300 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26301 // GIR_Coverage, 536,
26302 GIR_Done,
26303 // Label 1367: @68244
26304 GIM_Try, /*On fail goto*//*Label 1368*/ 68315, // Rule ID 537 //
26305 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
26306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
26307 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26308 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26309 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26310 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
26312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
26313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
26315 // (intrinsic_wo_chain:{ *:[i32] } 2289:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD,
26317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26321 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26322 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26323 GIR_EraseFromParent, /*InsnID*/0,
26324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26325 // GIR_Coverage, 537,
26326 GIR_Done,
26327 // Label 1368: @68315
26328 GIM_Try, /*On fail goto*//*Label 1369*/ 68386, // Rule ID 538 //
26329 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
26330 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
26331 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26332 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26333 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26334 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
26336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
26337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
26338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
26339 // (intrinsic_wo_chain:{ *:[i32] } 2290:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX,
26341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26345 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26346 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26347 GIR_EraseFromParent, /*InsnID*/0,
26348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26349 // GIR_Coverage, 538,
26350 GIR_Done,
26351 // Label 1369: @68386
26352 GIM_Try, /*On fail goto*//*Label 1370*/ 68450, // Rule ID 965 //
26353 GIM_CheckFeatures, GIFBS_HasDotProd,
26354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
26355 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
26356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
26357 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
26358 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
26359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
26361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
26362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
26363 // (intrinsic_wo_chain:{ *:[v2i32] } 2138:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
26364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTD,
26365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26369 GIR_EraseFromParent, /*InsnID*/0,
26370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26371 // GIR_Coverage, 965,
26372 GIR_Done,
26373 // Label 1370: @68450
26374 GIM_Try, /*On fail goto*//*Label 1371*/ 68514, // Rule ID 966 //
26375 GIM_CheckFeatures, GIFBS_HasDotProd,
26376 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
26377 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
26378 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
26379 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
26380 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
26381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
26383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
26384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
26385 // (intrinsic_wo_chain:{ *:[v2i32] } 2126:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
26386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTD,
26387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26391 GIR_EraseFromParent, /*InsnID*/0,
26392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26393 // GIR_Coverage, 966,
26394 GIR_Done,
26395 // Label 1371: @68514
26396 GIM_Try, /*On fail goto*//*Label 1372*/ 68578, // Rule ID 967 //
26397 GIM_CheckFeatures, GIFBS_HasDotProd,
26398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
26399 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26400 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26401 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26402 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
26403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26407 // (intrinsic_wo_chain:{ *:[v4i32] } 2138:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
26408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTQ,
26409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26413 GIR_EraseFromParent, /*InsnID*/0,
26414 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26415 // GIR_Coverage, 967,
26416 GIR_Done,
26417 // Label 1372: @68578
26418 GIM_Try, /*On fail goto*//*Label 1373*/ 68642, // Rule ID 968 //
26419 GIM_CheckFeatures, GIFBS_HasDotProd,
26420 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
26421 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26422 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26423 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26424 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
26425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26429 // (intrinsic_wo_chain:{ *:[v4i32] } 2126:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
26430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTQ,
26431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26435 GIR_EraseFromParent, /*InsnID*/0,
26436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26437 // GIR_Coverage, 968,
26438 GIR_Done,
26439 // Label 1373: @68642
26440 GIM_Try, /*On fail goto*//*Label 1374*/ 68706, // Rule ID 969 //
26441 GIM_CheckFeatures, GIFBS_HasMatMulInt8,
26442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_smmla,
26443 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26445 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26446 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
26447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26451 // (intrinsic_wo_chain:{ *:[v4i32] } 2137:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
26452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSMMLA,
26453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26457 GIR_EraseFromParent, /*InsnID*/0,
26458 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26459 // GIR_Coverage, 969,
26460 GIR_Done,
26461 // Label 1374: @68706
26462 GIM_Try, /*On fail goto*//*Label 1375*/ 68770, // Rule ID 970 //
26463 GIM_CheckFeatures, GIFBS_HasMatMulInt8,
26464 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_ummla,
26465 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26466 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26467 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26468 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
26469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26473 // (intrinsic_wo_chain:{ *:[v4i32] } 2139:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
26474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUMMLA,
26475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26479 GIR_EraseFromParent, /*InsnID*/0,
26480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26481 // GIR_Coverage, 970,
26482 GIR_Done,
26483 // Label 1375: @68770
26484 GIM_Try, /*On fail goto*//*Label 1376*/ 68834, // Rule ID 971 //
26485 GIM_CheckFeatures, GIFBS_HasMatMulInt8,
26486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_usmmla,
26487 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26489 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26490 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
26491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26495 // (intrinsic_wo_chain:{ *:[v4i32] } 2141:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
26496 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUSMMLA,
26497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26501 GIR_EraseFromParent, /*InsnID*/0,
26502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26503 // GIR_Coverage, 971,
26504 GIR_Done,
26505 // Label 1376: @68834
26506 GIM_Try, /*On fail goto*//*Label 1377*/ 68898, // Rule ID 972 //
26507 GIM_CheckFeatures, GIFBS_HasMatMulInt8,
26508 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_usdot,
26509 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
26510 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
26511 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
26512 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
26513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
26515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
26516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
26517 // (intrinsic_wo_chain:{ *:[v2i32] } 2140:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
26518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUSDOTD,
26519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26523 GIR_EraseFromParent, /*InsnID*/0,
26524 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26525 // GIR_Coverage, 972,
26526 GIR_Done,
26527 // Label 1377: @68898
26528 GIM_Try, /*On fail goto*//*Label 1378*/ 68962, // Rule ID 973 //
26529 GIM_CheckFeatures, GIFBS_HasMatMulInt8,
26530 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_usdot,
26531 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26532 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26533 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
26534 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
26535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26539 // (intrinsic_wo_chain:{ *:[v4i32] } 2140:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
26540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUSDOTQ,
26541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26545 GIR_EraseFromParent, /*InsnID*/0,
26546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26547 // GIR_Coverage, 973,
26548 GIR_Done,
26549 // Label 1378: @68962
26550 GIM_Try, /*On fail goto*//*Label 1379*/ 69033, // Rule ID 1706 //
26551 GIM_CheckFeatures, GIFBS_HasNEON,
26552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx1,
26553 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
26554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
26555 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
26556 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
26557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26558 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
26559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
26560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
26561 // (intrinsic_wo_chain:{ *:[v8i8] } 2256:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
26562 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1,
26563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
26564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
26565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26567 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26568 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26569 GIR_EraseFromParent, /*InsnID*/0,
26570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26571 // GIR_Coverage, 1706,
26572 GIR_Done,
26573 // Label 1379: @69033
26574 GIM_Try, /*On fail goto*//*Label 1380*/ 69097, // Rule ID 1737 //
26575 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
26576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su0,
26577 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26578 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26579 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26580 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26585 // (intrinsic_wo_chain:{ *:[v4i32] } 2131:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
26586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0,
26587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
26588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
26589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26591 GIR_EraseFromParent, /*InsnID*/0,
26592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26593 // GIR_Coverage, 1737,
26594 GIR_Done,
26595 // Label 1380: @69097
26596 GIM_Try, /*On fail goto*//*Label 1381*/ 69161, // Rule ID 1738 //
26597 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
26598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h,
26599 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26601 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26602 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26607 // (intrinsic_wo_chain:{ *:[v4i32] } 2133:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
26608 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H,
26609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
26610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
26611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26613 GIR_EraseFromParent, /*InsnID*/0,
26614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26615 // GIR_Coverage, 1738,
26616 GIR_Done,
26617 // Label 1381: @69161
26618 GIM_Try, /*On fail goto*//*Label 1382*/ 69225, // Rule ID 1739 //
26619 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
26620 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h2,
26621 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26622 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26623 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26624 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26629 // (intrinsic_wo_chain:{ *:[v4i32] } 2134:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
26630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2,
26631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
26632 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
26633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26635 GIR_EraseFromParent, /*InsnID*/0,
26636 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26637 // GIR_Coverage, 1739,
26638 GIR_Done,
26639 // Label 1382: @69225
26640 GIM_Try, /*On fail goto*//*Label 1383*/ 69289, // Rule ID 1740 //
26641 GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
26642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su1,
26643 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26644 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26645 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
26646 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
26647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26651 // (intrinsic_wo_chain:{ *:[v4i32] } 2136:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
26652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1,
26653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
26654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
26655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26657 GIR_EraseFromParent, /*InsnID*/0,
26658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26659 // GIR_Coverage, 1740,
26660 GIR_Done,
26661 // Label 1383: @69289
26662 GIM_Try, /*On fail goto*//*Label 1384*/ 69353, // Rule ID 1741 //
26663 GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
26664 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfdot,
26665 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
26666 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
26667 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
26668 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
26669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
26670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
26671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
26672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
26673 // (intrinsic_wo_chain:{ *:[v2f32] } 2122:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm) => (BF16VDOTS_VDOTD:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vd, DPR:{ *:[v4bf16] }:$Vn, DPR:{ *:[v4bf16] }:$Vm)
26674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BF16VDOTS_VDOTD,
26675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26679 GIR_EraseFromParent, /*InsnID*/0,
26680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26681 // GIR_Coverage, 1741,
26682 GIR_Done,
26683 // Label 1384: @69353
26684 GIM_Try, /*On fail goto*//*Label 1385*/ 69417, // Rule ID 1742 //
26685 GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
26686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfdot,
26687 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26688 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26689 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26690 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26695 // (intrinsic_wo_chain:{ *:[v4f32] } 2122:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (BF16VDOTS_VDOTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
26696 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BF16VDOTS_VDOTQ,
26697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26700 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26701 GIR_EraseFromParent, /*InsnID*/0,
26702 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26703 // GIR_Coverage, 1742,
26704 GIR_Done,
26705 // Label 1385: @69417
26706 GIM_Try, /*On fail goto*//*Label 1386*/ 69481, // Rule ID 1743 //
26707 GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
26708 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfmmla,
26709 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26710 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26711 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26712 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26717 // (intrinsic_wo_chain:{ *:[v4f32] } 2125:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (VMMLA:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
26718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMMLA,
26719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26723 GIR_EraseFromParent, /*InsnID*/0,
26724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26725 // GIR_Coverage, 1743,
26726 GIR_Done,
26727 // Label 1386: @69481
26728 GIM_Try, /*On fail goto*//*Label 1387*/ 69545, // Rule ID 1744 //
26729 GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
26730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfmlalt,
26731 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26732 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26733 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26734 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26739 // (intrinsic_wo_chain:{ *:[v4f32] } 2124:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (VBF16MALTQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
26740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBF16MALTQ,
26741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26745 GIR_EraseFromParent, /*InsnID*/0,
26746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26747 // GIR_Coverage, 1744,
26748 GIR_Done,
26749 // Label 1387: @69545
26750 GIM_Try, /*On fail goto*//*Label 1388*/ 69609, // Rule ID 1745 //
26751 GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
26752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_bfmlalb,
26753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
26754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
26755 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
26756 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
26757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
26758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
26759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
26760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
26761 // (intrinsic_wo_chain:{ *:[v4f32] } 2123:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm) => (VBF16MALBQ:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vd, QPR:{ *:[v8bf16] }:$Vn, QPR:{ *:[v8bf16] }:$Vm)
26762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBF16MALBQ,
26763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
26764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
26765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
26766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
26767 GIR_EraseFromParent, /*InsnID*/0,
26768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26769 // GIR_Coverage, 1745,
26770 GIR_Done,
26771 // Label 1388: @69609
26772 GIM_Try, /*On fail goto*//*Label 1389*/ 69680, // Rule ID 1913 //
26773 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
26774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
26775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26778 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
26781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
26782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26783 // (intrinsic_wo_chain:{ *:[i32] } 2281:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
26784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD,
26785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26789 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26790 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26791 GIR_EraseFromParent, /*InsnID*/0,
26792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26793 // GIR_Coverage, 1913,
26794 GIR_Done,
26795 // Label 1389: @69680
26796 GIM_Try, /*On fail goto*//*Label 1390*/ 69751, // Rule ID 1914 //
26797 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
26798 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
26799 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26801 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26802 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
26805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
26806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26807 // (intrinsic_wo_chain:{ *:[i32] } 2282:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
26808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX,
26809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26810 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26811 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26813 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26814 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26815 GIR_EraseFromParent, /*InsnID*/0,
26816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26817 // GIR_Coverage, 1914,
26818 GIR_Done,
26819 // Label 1390: @69751
26820 GIM_Try, /*On fail goto*//*Label 1391*/ 69822, // Rule ID 1915 //
26821 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
26822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
26823 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26824 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26825 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26826 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
26829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
26830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26831 // (intrinsic_wo_chain:{ *:[i32] } 2289:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
26832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD,
26833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26837 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26838 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26839 GIR_EraseFromParent, /*InsnID*/0,
26840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26841 // GIR_Coverage, 1915,
26842 GIR_Done,
26843 // Label 1391: @69822
26844 GIM_Try, /*On fail goto*//*Label 1392*/ 69893, // Rule ID 1916 //
26845 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
26846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
26847 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26848 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26849 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26850 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
26853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
26854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26855 // (intrinsic_wo_chain:{ *:[i32] } 2290:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
26856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX,
26857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
26859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
26860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
26861 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26862 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26863 GIR_EraseFromParent, /*InsnID*/0,
26864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26865 // GIR_Coverage, 1916,
26866 GIR_Done,
26867 // Label 1392: @69893
26868 GIM_Try, /*On fail goto*//*Label 1393*/ 69964, // Rule ID 1989 //
26869 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
26870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
26871 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26873 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26874 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26879 // (intrinsic_wo_chain:{ *:[i32] } 2279:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
26880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB,
26881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
26883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
26884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
26885 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26886 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26887 GIR_EraseFromParent, /*InsnID*/0,
26888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26889 // GIR_Coverage, 1989,
26890 GIR_Done,
26891 // Label 1393: @69964
26892 GIM_Try, /*On fail goto*//*Label 1394*/ 70035, // Rule ID 1990 //
26893 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
26894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
26895 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26896 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26897 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26898 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26903 // (intrinsic_wo_chain:{ *:[i32] } 2280:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
26904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT,
26905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
26907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
26908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
26909 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26910 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26911 GIR_EraseFromParent, /*InsnID*/0,
26912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26913 // GIR_Coverage, 1990,
26914 GIR_Done,
26915 // Label 1394: @70035
26916 GIM_Try, /*On fail goto*//*Label 1395*/ 70106, // Rule ID 1991 //
26917 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
26918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
26919 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26920 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26921 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26922 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26927 // (intrinsic_wo_chain:{ *:[i32] } 2285:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
26928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB,
26929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
26931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
26932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
26933 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26934 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26935 GIR_EraseFromParent, /*InsnID*/0,
26936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26937 // GIR_Coverage, 1991,
26938 GIR_Done,
26939 // Label 1395: @70106
26940 GIM_Try, /*On fail goto*//*Label 1396*/ 70177, // Rule ID 1992 //
26941 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
26942 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
26943 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26944 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26945 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26946 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26951 // (intrinsic_wo_chain:{ *:[i32] } 2286:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
26952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
26953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
26955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
26956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
26957 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26958 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26959 GIR_EraseFromParent, /*InsnID*/0,
26960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26961 // GIR_Coverage, 1992,
26962 GIR_Done,
26963 // Label 1396: @70177
26964 GIM_Try, /*On fail goto*//*Label 1397*/ 70248, // Rule ID 1993 //
26965 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
26966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
26967 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26968 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26969 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26970 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26975 // (intrinsic_wo_chain:{ *:[i32] } 2287:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
26976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB,
26977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
26978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
26979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
26980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
26981 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
26982 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
26983 GIR_EraseFromParent, /*InsnID*/0,
26984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
26985 // GIR_Coverage, 1993,
26986 GIR_Done,
26987 // Label 1397: @70248
26988 GIM_Try, /*On fail goto*//*Label 1398*/ 70319, // Rule ID 1994 //
26989 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
26990 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
26991 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
26992 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
26993 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
26994 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
26995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
26996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
26997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
26998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
26999 // (intrinsic_wo_chain:{ *:[i32] } 2288:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT,
27001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27003 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27004 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27005 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27006 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27007 GIR_EraseFromParent, /*InsnID*/0,
27008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27009 // GIR_Coverage, 1994,
27010 GIR_Done,
27011 // Label 1398: @70319
27012 GIM_Try, /*On fail goto*//*Label 1399*/ 70390, // Rule ID 2173 //
27013 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
27015 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27016 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27018 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27023 // (intrinsic_wo_chain:{ *:[i32] } 2279:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB,
27025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27029 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27030 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27031 GIR_EraseFromParent, /*InsnID*/0,
27032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27033 // GIR_Coverage, 2173,
27034 GIR_Done,
27035 // Label 1399: @70390
27036 GIM_Try, /*On fail goto*//*Label 1400*/ 70461, // Rule ID 2174 //
27037 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
27039 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27040 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27041 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27042 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27047 // (intrinsic_wo_chain:{ *:[i32] } 2280:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT,
27049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27051 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27053 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27054 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27055 GIR_EraseFromParent, /*InsnID*/0,
27056 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27057 // GIR_Coverage, 2174,
27058 GIR_Done,
27059 // Label 1400: @70461
27060 GIM_Try, /*On fail goto*//*Label 1401*/ 70532, // Rule ID 2175 //
27061 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27062 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
27063 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27064 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27065 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27066 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27071 // (intrinsic_wo_chain:{ *:[i32] } 2285:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB,
27073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27077 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27078 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27079 GIR_EraseFromParent, /*InsnID*/0,
27080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27081 // GIR_Coverage, 2175,
27082 GIR_Done,
27083 // Label 1401: @70532
27084 GIM_Try, /*On fail goto*//*Label 1402*/ 70603, // Rule ID 2176 //
27085 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27086 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
27087 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27088 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27089 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27090 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27095 // (intrinsic_wo_chain:{ *:[i32] } 2286:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
27097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27101 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27102 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27103 GIR_EraseFromParent, /*InsnID*/0,
27104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27105 // GIR_Coverage, 2176,
27106 GIR_Done,
27107 // Label 1402: @70603
27108 GIM_Try, /*On fail goto*//*Label 1403*/ 70674, // Rule ID 2177 //
27109 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
27111 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27112 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27113 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27114 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27119 // (intrinsic_wo_chain:{ *:[i32] } 2287:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB,
27121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27125 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27126 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27127 GIR_EraseFromParent, /*InsnID*/0,
27128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27129 // GIR_Coverage, 2177,
27130 GIR_Done,
27131 // Label 1403: @70674
27132 GIM_Try, /*On fail goto*//*Label 1404*/ 70745, // Rule ID 2178 //
27133 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
27134 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
27135 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
27136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
27137 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27138 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
27140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
27141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
27142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
27143 // (intrinsic_wo_chain:{ *:[i32] } 2288:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT,
27145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
27146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
27147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
27148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
27149 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27150 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27151 GIR_EraseFromParent, /*InsnID*/0,
27152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27153 // GIR_Coverage, 2178,
27154 GIR_Done,
27155 // Label 1404: @70745
27156 GIM_Try, /*On fail goto*//*Label 1405*/ 70816, // Rule ID 2473 //
27157 GIM_CheckFeatures, GIFBS_HasNEON,
27158 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27159 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
27160 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
27161 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
27162 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
27163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27167 // (intrinsic_wo_chain:{ *:[v8i8] } 2147:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VBSPd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
27169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27173 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27174 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27175 GIR_EraseFromParent, /*InsnID*/0,
27176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27177 // GIR_Coverage, 2473,
27178 GIR_Done,
27179 // Label 1405: @70816
27180 GIM_Try, /*On fail goto*//*Label 1406*/ 70887, // Rule ID 2474 //
27181 GIM_CheckFeatures, GIFBS_HasNEON,
27182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27183 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
27184 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
27185 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
27186 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
27187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27191 // (intrinsic_wo_chain:{ *:[v4i16] } 2147:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VBSPd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
27193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27197 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27198 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27199 GIR_EraseFromParent, /*InsnID*/0,
27200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27201 // GIR_Coverage, 2474,
27202 GIR_Done,
27203 // Label 1406: @70887
27204 GIM_Try, /*On fail goto*//*Label 1407*/ 70958, // Rule ID 2475 //
27205 GIM_CheckFeatures, GIFBS_HasNEON,
27206 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27207 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27208 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27209 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
27210 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
27211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27215 // (intrinsic_wo_chain:{ *:[v2i32] } 2147:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VBSPd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
27217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27221 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27222 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27223 GIR_EraseFromParent, /*InsnID*/0,
27224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27225 // GIR_Coverage, 2475,
27226 GIR_Done,
27227 // Label 1407: @70958
27228 GIM_Try, /*On fail goto*//*Label 1408*/ 71029, // Rule ID 2476 //
27229 GIM_CheckFeatures, GIFBS_HasNEON,
27230 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27231 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
27232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
27233 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
27234 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
27235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27239 // (intrinsic_wo_chain:{ *:[v2f32] } 2147:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VBSPd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
27240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
27241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27245 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27246 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27247 GIR_EraseFromParent, /*InsnID*/0,
27248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27249 // GIR_Coverage, 2476,
27250 GIR_Done,
27251 // Label 1408: @71029
27252 GIM_Try, /*On fail goto*//*Label 1409*/ 71100, // Rule ID 2477 //
27253 GIM_CheckFeatures, GIFBS_HasNEON,
27254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27255 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
27256 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
27257 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
27258 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
27259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
27260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
27261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
27262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
27263 // (intrinsic_wo_chain:{ *:[v1i64] } 2147:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VBSPd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
27264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPd,
27265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27269 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27270 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27271 GIR_EraseFromParent, /*InsnID*/0,
27272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27273 // GIR_Coverage, 2477,
27274 GIR_Done,
27275 // Label 1409: @71100
27276 GIM_Try, /*On fail goto*//*Label 1410*/ 71171, // Rule ID 2480 //
27277 GIM_CheckFeatures, GIFBS_HasNEON,
27278 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27279 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27280 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27281 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27282 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
27283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27287 // (intrinsic_wo_chain:{ *:[v16i8] } 2147:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VBSPq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
27289 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27293 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27294 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27295 GIR_EraseFromParent, /*InsnID*/0,
27296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27297 // GIR_Coverage, 2480,
27298 GIR_Done,
27299 // Label 1410: @71171
27300 GIM_Try, /*On fail goto*//*Label 1411*/ 71242, // Rule ID 2481 //
27301 GIM_CheckFeatures, GIFBS_HasNEON,
27302 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27303 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27304 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27305 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27306 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
27307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27311 // (intrinsic_wo_chain:{ *:[v8i16] } 2147:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VBSPq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
27313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27317 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27318 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27319 GIR_EraseFromParent, /*InsnID*/0,
27320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27321 // GIR_Coverage, 2481,
27322 GIR_Done,
27323 // Label 1411: @71242
27324 GIM_Try, /*On fail goto*//*Label 1412*/ 71313, // Rule ID 2482 //
27325 GIM_CheckFeatures, GIFBS_HasNEON,
27326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27327 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27328 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27329 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27330 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27335 // (intrinsic_wo_chain:{ *:[v4i32] } 2147:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VBSPq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
27337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27341 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27342 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27343 GIR_EraseFromParent, /*InsnID*/0,
27344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27345 // GIR_Coverage, 2482,
27346 GIR_Done,
27347 // Label 1412: @71313
27348 GIM_Try, /*On fail goto*//*Label 1413*/ 71384, // Rule ID 2483 //
27349 GIM_CheckFeatures, GIFBS_HasNEON,
27350 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27351 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27352 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27353 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27354 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27359 // (intrinsic_wo_chain:{ *:[v4f32] } 2147:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VBSPq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
27360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
27361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27365 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27366 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27367 GIR_EraseFromParent, /*InsnID*/0,
27368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27369 // GIR_Coverage, 2483,
27370 GIR_Done,
27371 // Label 1413: @71384
27372 GIM_Try, /*On fail goto*//*Label 1414*/ 71455, // Rule ID 2484 //
27373 GIM_CheckFeatures, GIFBS_HasNEON,
27374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
27375 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
27376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
27377 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
27378 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
27379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
27381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
27382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
27383 // (intrinsic_wo_chain:{ *:[v2i64] } 2147:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VBSPq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
27384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSPq,
27385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
27387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
27388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
27389 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
27390 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27391 GIR_EraseFromParent, /*InsnID*/0,
27392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27393 // GIR_Coverage, 2484,
27394 GIR_Done,
27395 // Label 1414: @71455
27396 GIM_Try, /*On fail goto*//*Label 1415*/ 71526, // Rule ID 4720 //
27397 GIM_CheckFeatures, GIFBS_HasMVEInt,
27398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlah,
27399 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27400 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27401 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27402 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27407 // (intrinsic_wo_chain:{ *:[v16i8] } 2061:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLAH_qrs8,
27409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27413 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27414 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27415 GIR_EraseFromParent, /*InsnID*/0,
27416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27417 // GIR_Coverage, 4720,
27418 GIR_Done,
27419 // Label 1415: @71526
27420 GIM_Try, /*On fail goto*//*Label 1416*/ 71597, // Rule ID 4722 //
27421 GIM_CheckFeatures, GIFBS_HasMVEInt,
27422 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlah,
27423 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27424 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27425 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27426 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27431 // (intrinsic_wo_chain:{ *:[v8i16] } 2061:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27432 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLAH_qrs16,
27433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27437 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27438 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27439 GIR_EraseFromParent, /*InsnID*/0,
27440 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27441 // GIR_Coverage, 4722,
27442 GIR_Done,
27443 // Label 1416: @71597
27444 GIM_Try, /*On fail goto*//*Label 1417*/ 71668, // Rule ID 4724 //
27445 GIM_CheckFeatures, GIFBS_HasMVEInt,
27446 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlah,
27447 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27448 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27449 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27450 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27455 // (intrinsic_wo_chain:{ *:[v4i32] } 2061:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
27456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLAH_qrs32,
27457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27461 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27462 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27463 GIR_EraseFromParent, /*InsnID*/0,
27464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27465 // GIR_Coverage, 4724,
27466 GIR_Done,
27467 // Label 1417: @71668
27468 GIM_Try, /*On fail goto*//*Label 1418*/ 71739, // Rule ID 4726 //
27469 GIM_CheckFeatures, GIFBS_HasMVEInt,
27470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlah,
27471 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27472 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27473 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27474 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27479 // (intrinsic_wo_chain:{ *:[v16i8] } 2070:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLAH_qrs8,
27481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27485 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27486 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27487 GIR_EraseFromParent, /*InsnID*/0,
27488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27489 // GIR_Coverage, 4726,
27490 GIR_Done,
27491 // Label 1418: @71739
27492 GIM_Try, /*On fail goto*//*Label 1419*/ 71810, // Rule ID 4728 //
27493 GIM_CheckFeatures, GIFBS_HasMVEInt,
27494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlah,
27495 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27498 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27503 // (intrinsic_wo_chain:{ *:[v8i16] } 2070:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27504 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLAH_qrs16,
27505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27509 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27510 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27511 GIR_EraseFromParent, /*InsnID*/0,
27512 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27513 // GIR_Coverage, 4728,
27514 GIR_Done,
27515 // Label 1419: @71810
27516 GIM_Try, /*On fail goto*//*Label 1420*/ 71881, // Rule ID 4730 //
27517 GIM_CheckFeatures, GIFBS_HasMVEInt,
27518 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlah,
27519 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27520 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27521 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27522 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27527 // (intrinsic_wo_chain:{ *:[v4i32] } 2070:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
27528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLAH_qrs32,
27529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27533 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27534 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27535 GIR_EraseFromParent, /*InsnID*/0,
27536 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27537 // GIR_Coverage, 4730,
27538 GIR_Done,
27539 // Label 1420: @71881
27540 GIM_Try, /*On fail goto*//*Label 1421*/ 71952, // Rule ID 4732 //
27541 GIM_CheckFeatures, GIFBS_HasMVEInt,
27542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlash,
27543 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27544 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27545 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27546 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27551 // (intrinsic_wo_chain:{ *:[v16i8] } 2063:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27552 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLASH_qrs8,
27553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27557 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27558 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27559 GIR_EraseFromParent, /*InsnID*/0,
27560 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27561 // GIR_Coverage, 4732,
27562 GIR_Done,
27563 // Label 1421: @71952
27564 GIM_Try, /*On fail goto*//*Label 1422*/ 72023, // Rule ID 4734 //
27565 GIM_CheckFeatures, GIFBS_HasMVEInt,
27566 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlash,
27567 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27568 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27569 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27570 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27575 // (intrinsic_wo_chain:{ *:[v8i16] } 2063:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLASH_qrs16,
27577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27581 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27582 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27583 GIR_EraseFromParent, /*InsnID*/0,
27584 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27585 // GIR_Coverage, 4734,
27586 GIR_Done,
27587 // Label 1422: @72023
27588 GIM_Try, /*On fail goto*//*Label 1423*/ 72094, // Rule ID 4736 //
27589 GIM_CheckFeatures, GIFBS_HasMVEInt,
27590 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlash,
27591 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27592 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27593 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27594 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27599 // (intrinsic_wo_chain:{ *:[v4i32] } 2063:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
27600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLASH_qrs32,
27601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27605 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27606 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27607 GIR_EraseFromParent, /*InsnID*/0,
27608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27609 // GIR_Coverage, 4736,
27610 GIR_Done,
27611 // Label 1423: @72094
27612 GIM_Try, /*On fail goto*//*Label 1424*/ 72165, // Rule ID 4738 //
27613 GIM_CheckFeatures, GIFBS_HasMVEInt,
27614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlash,
27615 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
27616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27617 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
27618 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27623 // (intrinsic_wo_chain:{ *:[v16i8] } 2072:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLASH_qrs8,
27625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27627 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27629 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27630 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27631 GIR_EraseFromParent, /*InsnID*/0,
27632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27633 // GIR_Coverage, 4738,
27634 GIR_Done,
27635 // Label 1424: @72165
27636 GIM_Try, /*On fail goto*//*Label 1425*/ 72236, // Rule ID 4740 //
27637 GIM_CheckFeatures, GIFBS_HasMVEInt,
27638 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlash,
27639 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27640 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27641 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
27642 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27647 // (intrinsic_wo_chain:{ *:[v8i16] } 2072:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27648 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLASH_qrs16,
27649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27653 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27654 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27655 GIR_EraseFromParent, /*InsnID*/0,
27656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27657 // GIR_Coverage, 4740,
27658 GIR_Done,
27659 // Label 1425: @72236
27660 GIM_Try, /*On fail goto*//*Label 1426*/ 72307, // Rule ID 4742 //
27661 GIM_CheckFeatures, GIFBS_HasMVEInt,
27662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqrdmlash,
27663 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27664 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27665 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
27666 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
27670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
27671 // (intrinsic_wo_chain:{ *:[v4i32] } 2072:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
27672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLASH_qrs32,
27673 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // v1
27675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // v2
27676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // s
27677 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27678 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27679 GIR_EraseFromParent, /*InsnID*/0,
27680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27681 // GIR_Coverage, 4742,
27682 GIR_Done,
27683 // Label 1426: @72307
27684 GIM_Try, /*On fail goto*//*Label 1427*/ 72403, // Rule ID 2609 //
27685 GIM_CheckFeatures, GIFBS_HasNEON,
27686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1c,
27687 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27688 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27689 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27690 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27692 // (intrinsic_wo_chain:{ *:[v4i32] } 2127:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
27693 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
27694 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
27695 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
27696 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
27697 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
27698 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
27699 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
27700 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
27701 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
27702 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
27703 GIR_AddImm, /*InsnID*/1, /*Imm*/17,
27704 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
27705 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, ARM::SPRRegClassID,
27706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1C,
27707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
27709 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
27711 GIR_EraseFromParent, /*InsnID*/0,
27712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27713 // GIR_Coverage, 2609,
27714 GIR_Done,
27715 // Label 1427: @72403
27716 GIM_Try, /*On fail goto*//*Label 1428*/ 72499, // Rule ID 2610 //
27717 GIM_CheckFeatures, GIFBS_HasNEON,
27718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1m,
27719 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27720 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27721 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27722 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27724 // (intrinsic_wo_chain:{ *:[v4i32] } 2129:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
27725 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
27726 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
27727 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
27728 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
27729 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
27730 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
27731 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
27732 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
27733 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
27734 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
27735 GIR_AddImm, /*InsnID*/1, /*Imm*/17,
27736 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
27737 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, ARM::SPRRegClassID,
27738 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1M,
27739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
27741 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
27743 GIR_EraseFromParent, /*InsnID*/0,
27744 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27745 // GIR_Coverage, 2610,
27746 GIR_Done,
27747 // Label 1428: @72499
27748 GIM_Try, /*On fail goto*//*Label 1429*/ 72595, // Rule ID 2611 //
27749 GIM_CheckFeatures, GIFBS_HasNEON,
27750 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1p,
27751 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27752 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
27753 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27754 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
27755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
27756 // (intrinsic_wo_chain:{ *:[v4i32] } 2130:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
27757 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
27758 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
27759 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
27760 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
27761 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
27762 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
27763 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::SUBREG_TO_REG,
27764 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
27765 GIR_AddImm, /*InsnID*/1, /*Imm*/0,
27766 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
27767 GIR_AddImm, /*InsnID*/1, /*Imm*/17,
27768 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPair_with_ssub_0RegClassID,
27769 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, ARM::SPRRegClassID,
27770 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1P,
27771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
27772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // hash_abcd
27773 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wk
27775 GIR_EraseFromParent, /*InsnID*/0,
27776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27777 // GIR_Coverage, 2611,
27778 GIR_Done,
27779 // Label 1429: @72595
27780 GIM_Reject,
27781 // Label 1275: @72596
27782 GIM_Try, /*On fail goto*//*Label 1430*/ 75986,
27783 GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
27784 GIM_Try, /*On fail goto*//*Label 1431*/ 72684, // Rule ID 3693 //
27785 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27786 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27787 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27788 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27789 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27790 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27793 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
27794 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27795 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27796 // (intrinsic_wo_chain:{ *:[v8i16] } 2102:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
27797 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27798 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27799 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8bh,
27801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27803 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27804 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27805 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27806 GIR_EraseFromParent, /*InsnID*/0,
27807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27808 // GIR_Coverage, 3693,
27809 GIR_Done,
27810 // Label 1431: @72684
27811 GIM_Try, /*On fail goto*//*Label 1432*/ 72767, // Rule ID 3697 //
27812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27813 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27814 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27815 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27816 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27817 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27820 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
27821 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27822 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
27823 // (intrinsic_wo_chain:{ *:[v8i16] } 2102:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
27824 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27825 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27826 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws8th,
27828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27830 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27831 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27832 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27833 GIR_EraseFromParent, /*InsnID*/0,
27834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27835 // GIR_Coverage, 3697,
27836 GIR_Done,
27837 // Label 1432: @72767
27838 GIM_Try, /*On fail goto*//*Label 1433*/ 72850, // Rule ID 3701 //
27839 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27840 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27841 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27842 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27843 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27844 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27847 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
27848 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27849 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27850 // (intrinsic_wo_chain:{ *:[v4i32] } 2102:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
27851 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27852 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27853 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16bh,
27855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27857 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27858 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27859 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27860 GIR_EraseFromParent, /*InsnID*/0,
27861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27862 // GIR_Coverage, 3701,
27863 GIR_Done,
27864 // Label 1433: @72850
27865 GIM_Try, /*On fail goto*//*Label 1434*/ 72933, // Rule ID 3705 //
27866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27867 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27868 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27869 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27870 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27871 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27874 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
27875 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
27876 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
27877 // (intrinsic_wo_chain:{ *:[v4i32] } 2102:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
27878 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27880 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lws16th,
27882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27884 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27885 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27886 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27887 GIR_EraseFromParent, /*InsnID*/0,
27888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27889 // GIR_Coverage, 3705,
27890 GIR_Done,
27891 // Label 1434: @72933
27892 GIM_Try, /*On fail goto*//*Label 1435*/ 73016, // Rule ID 3709 //
27893 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27894 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27895 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27896 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27897 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27898 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27901 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
27902 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27903 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27904 // (intrinsic_wo_chain:{ *:[v8i16] } 2102:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
27905 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27906 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27907 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8bh,
27909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27911 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27912 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27913 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27914 GIR_EraseFromParent, /*InsnID*/0,
27915 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27916 // GIR_Coverage, 3709,
27917 GIR_Done,
27918 // Label 1435: @73016
27919 GIM_Try, /*On fail goto*//*Label 1436*/ 73099, // Rule ID 3713 //
27920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27921 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
27922 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
27923 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27924 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27925 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27928 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 8,
27929 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27930 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
27931 // (intrinsic_wo_chain:{ *:[v8i16] } 2102:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
27932 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27933 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27934 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu8th,
27936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27938 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27939 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27940 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27941 GIR_EraseFromParent, /*InsnID*/0,
27942 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27943 // GIR_Coverage, 3713,
27944 GIR_Done,
27945 // Label 1436: @73099
27946 GIM_Try, /*On fail goto*//*Label 1437*/ 73182, // Rule ID 3717 //
27947 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27948 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27949 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27950 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27951 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27952 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27955 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
27956 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27957 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
27958 // (intrinsic_wo_chain:{ *:[v4i32] } 2102:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
27959 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27960 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27961 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16bh,
27963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27965 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27966 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27967 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27968 GIR_EraseFromParent, /*InsnID*/0,
27969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27970 // GIR_Coverage, 3717,
27971 GIR_Done,
27972 // Label 1437: @73182
27973 GIM_Try, /*On fail goto*//*Label 1438*/ 73265, // Rule ID 3721 //
27974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshll_imm,
27975 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
27976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
27977 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
27978 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
27979 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
27980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
27981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
27982 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 16,
27983 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
27984 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
27985 // (intrinsic_wo_chain:{ *:[v4i32] } 2102:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
27986 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27987 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
27988 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
27989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHLL_lwu16th,
27990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
27991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
27992 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
27993 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
27994 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
27995 GIR_EraseFromParent, /*InsnID*/0,
27996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
27997 // GIR_Coverage, 3721,
27998 GIR_Done,
27999 // Label 1438: @73265
28000 GIM_Try, /*On fail goto*//*Label 1439*/ 73354, // Rule ID 4319 //
28001 GIM_CheckFeatures, GIFBS_HasMVEInt,
28002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28003 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28005 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28006 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28007 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28011 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28012 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28013 // (intrinsic_wo_chain:{ *:[v8i16] } 2057:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28014 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28015 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28016 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs8,
28018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28021 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28022 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28023 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28024 GIR_EraseFromParent, /*InsnID*/0,
28025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28026 // GIR_Coverage, 4319,
28027 GIR_Done,
28028 // Label 1439: @73354
28029 GIM_Try, /*On fail goto*//*Label 1440*/ 73443, // Rule ID 4321 //
28030 GIM_CheckFeatures, GIFBS_HasMVEInt,
28031 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28032 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28033 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28034 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28035 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28036 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28040 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28041 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28042 // (intrinsic_wo_chain:{ *:[v8i16] } 2057:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28043 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28044 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28045 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs8,
28047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28050 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28051 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28052 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28053 GIR_EraseFromParent, /*InsnID*/0,
28054 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28055 // GIR_Coverage, 4321,
28056 GIR_Done,
28057 // Label 1440: @73443
28058 GIM_Try, /*On fail goto*//*Label 1441*/ 73532, // Rule ID 4323 //
28059 GIM_CheckFeatures, GIFBS_HasMVEInt,
28060 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28061 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28062 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28063 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28064 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28065 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28069 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28070 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28071 // (intrinsic_wo_chain:{ *:[v4i32] } 2057:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28072 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28073 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28074 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs16,
28076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28079 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28080 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28081 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28082 GIR_EraseFromParent, /*InsnID*/0,
28083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28084 // GIR_Coverage, 4323,
28085 GIR_Done,
28086 // Label 1441: @73532
28087 GIM_Try, /*On fail goto*//*Label 1442*/ 73621, // Rule ID 4325 //
28088 GIM_CheckFeatures, GIFBS_HasMVEInt,
28089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28090 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28091 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28092 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28093 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28094 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28098 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28099 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28100 // (intrinsic_wo_chain:{ *:[v4i32] } 2057:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28101 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28102 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28103 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs16,
28105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28108 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28109 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28110 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28111 GIR_EraseFromParent, /*InsnID*/0,
28112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28113 // GIR_Coverage, 4325,
28114 GIR_Done,
28115 // Label 1442: @73621
28116 GIM_Try, /*On fail goto*//*Label 1443*/ 73710, // Rule ID 4327 //
28117 GIM_CheckFeatures, GIFBS_HasMVEInt,
28118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28119 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
28120 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28121 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28122 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28123 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28127 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28128 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28129 // (intrinsic_wo_chain:{ *:[v2i64] } 2057:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28130 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28131 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28132 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBs32,
28134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28137 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28138 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28139 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28140 GIR_EraseFromParent, /*InsnID*/0,
28141 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28142 // GIR_Coverage, 4327,
28143 GIR_Done,
28144 // Label 1443: @73710
28145 GIM_Try, /*On fail goto*//*Label 1444*/ 73799, // Rule ID 4329 //
28146 GIM_CheckFeatures, GIFBS_HasMVEInt,
28147 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28148 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
28149 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28150 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28151 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28152 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28156 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28157 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28158 // (intrinsic_wo_chain:{ *:[v2i64] } 2057:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28159 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28160 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28161 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTs32,
28163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28166 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28167 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28168 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28169 GIR_EraseFromParent, /*InsnID*/0,
28170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28171 // GIR_Coverage, 4329,
28172 GIR_Done,
28173 // Label 1444: @73799
28174 GIM_Try, /*On fail goto*//*Label 1445*/ 73888, // Rule ID 4331 //
28175 GIM_CheckFeatures, GIFBS_HasMVEInt,
28176 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28177 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28178 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28179 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28180 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28181 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28185 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28186 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28187 // (intrinsic_wo_chain:{ *:[v8i16] } 2057:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28188 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28189 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28190 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28191 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu8,
28192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28195 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28196 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28197 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28198 GIR_EraseFromParent, /*InsnID*/0,
28199 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28200 // GIR_Coverage, 4331,
28201 GIR_Done,
28202 // Label 1445: @73888
28203 GIM_Try, /*On fail goto*//*Label 1446*/ 73977, // Rule ID 4333 //
28204 GIM_CheckFeatures, GIFBS_HasMVEInt,
28205 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28206 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28207 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28208 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28209 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28210 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28212 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28214 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28215 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28216 // (intrinsic_wo_chain:{ *:[v8i16] } 2057:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28217 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28218 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28219 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu8,
28221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28224 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28225 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28226 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28227 GIR_EraseFromParent, /*InsnID*/0,
28228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28229 // GIR_Coverage, 4333,
28230 GIR_Done,
28231 // Label 1446: @73977
28232 GIM_Try, /*On fail goto*//*Label 1447*/ 74066, // Rule ID 4335 //
28233 GIM_CheckFeatures, GIFBS_HasMVEInt,
28234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28238 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28239 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28243 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28244 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28245 // (intrinsic_wo_chain:{ *:[v4i32] } 2057:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28246 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28247 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28248 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu16,
28250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28253 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28254 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28255 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28256 GIR_EraseFromParent, /*InsnID*/0,
28257 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28258 // GIR_Coverage, 4335,
28259 GIR_Done,
28260 // Label 1447: @74066
28261 GIM_Try, /*On fail goto*//*Label 1448*/ 74155, // Rule ID 4337 //
28262 GIM_CheckFeatures, GIFBS_HasMVEInt,
28263 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28264 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28265 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28266 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28267 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28268 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28272 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28273 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28274 // (intrinsic_wo_chain:{ *:[v4i32] } 2057:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28275 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28276 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu16,
28279 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28282 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28283 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28284 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28285 GIR_EraseFromParent, /*InsnID*/0,
28286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28287 // GIR_Coverage, 4337,
28288 GIR_Done,
28289 // Label 1448: @74155
28290 GIM_Try, /*On fail goto*//*Label 1449*/ 74244, // Rule ID 4339 //
28291 GIM_CheckFeatures, GIFBS_HasMVEInt,
28292 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28293 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
28294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28295 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28296 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28297 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28301 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28302 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28303 // (intrinsic_wo_chain:{ *:[v2i64] } 2057:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28304 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28305 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28306 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLBu32,
28308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28311 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28312 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28313 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28314 GIR_EraseFromParent, /*InsnID*/0,
28315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28316 // GIR_Coverage, 4339,
28317 GIR_Done,
28318 // Label 1449: @74244
28319 GIM_Try, /*On fail goto*//*Label 1450*/ 74333, // Rule ID 4341 //
28320 GIM_CheckFeatures, GIFBS_HasMVEInt,
28321 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmull,
28322 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
28323 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28324 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28325 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28326 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28330 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
28331 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
28332 // (intrinsic_wo_chain:{ *:[v2i64] } 2057:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28333 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28334 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28335 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28336 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULLTu32,
28337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qm
28339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qn
28340 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28341 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28342 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28343 GIR_EraseFromParent, /*InsnID*/0,
28344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28345 // GIR_Coverage, 4341,
28346 GIR_Done,
28347 // Label 1450: @74333
28348 GIM_Try, /*On fail goto*//*Label 1451*/ 74430, // Rule ID 3978 //
28349 GIM_CheckFeatures, GIFBS_HasMVEFloat,
28350 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28351 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28352 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28353 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28354 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28355 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
28356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28357 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28358 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28359 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28360 // MIs[1] Operand 1
28361 // No operand predicates
28362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28364 GIM_CheckIsSafeToFold, /*InsnID*/1,
28365 // (intrinsic_wo_chain:{ *:[v8f16] } 2000:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
28366 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28367 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28368 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf16,
28370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28373 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28374 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28375 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28376 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28377 GIR_EraseFromParent, /*InsnID*/0,
28378 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28379 // GIR_Coverage, 3978,
28380 GIR_Done,
28381 // Label 1451: @74430
28382 GIM_Try, /*On fail goto*//*Label 1452*/ 74527, // Rule ID 3980 //
28383 GIM_CheckFeatures, GIFBS_HasMVEFloat,
28384 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28385 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28387 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28388 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28389 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
28390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28391 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28392 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28393 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28394 // MIs[1] Operand 1
28395 // No operand predicates
28396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28398 GIM_CheckIsSafeToFold, /*InsnID*/1,
28399 // (intrinsic_wo_chain:{ *:[v4f32] } 2000:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
28400 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28401 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28402 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDf32,
28404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28407 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28408 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28409 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28410 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28411 GIR_EraseFromParent, /*InsnID*/0,
28412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28413 // GIR_Coverage, 3980,
28414 GIR_Done,
28415 // Label 1452: @74527
28416 GIM_Try, /*On fail goto*//*Label 1453*/ 74624, // Rule ID 4461 //
28417 GIM_CheckFeatures, GIFBS_HasMVEInt,
28418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28419 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28421 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28422 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
28423 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
28424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28425 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28426 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28427 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28428 // MIs[1] Operand 1
28429 // No operand predicates
28430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28432 GIM_CheckIsSafeToFold, /*InsnID*/1,
28433 // (intrinsic_wo_chain:{ *:[v16i8] } 2000:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
28434 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28435 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28436 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28437 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi8,
28438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28441 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28442 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28443 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28444 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28445 GIR_EraseFromParent, /*InsnID*/0,
28446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28447 // GIR_Coverage, 4461,
28448 GIR_Done,
28449 // Label 1453: @74624
28450 GIM_Try, /*On fail goto*//*Label 1454*/ 74721, // Rule ID 4463 //
28451 GIM_CheckFeatures, GIFBS_HasMVEInt,
28452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28453 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28454 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28455 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28456 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28457 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
28458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28459 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28460 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28461 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28462 // MIs[1] Operand 1
28463 // No operand predicates
28464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28466 GIM_CheckIsSafeToFold, /*InsnID*/1,
28467 // (intrinsic_wo_chain:{ *:[v8i16] } 2000:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
28468 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28469 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28470 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi16,
28472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28475 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28476 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28477 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28478 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28479 GIR_EraseFromParent, /*InsnID*/0,
28480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28481 // GIR_Coverage, 4463,
28482 GIR_Done,
28483 // Label 1454: @74721
28484 GIM_Try, /*On fail goto*//*Label 1455*/ 74818, // Rule ID 4465 //
28485 GIM_CheckFeatures, GIFBS_HasMVEInt,
28486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28487 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28489 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28490 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28491 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
28492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28493 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28494 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28495 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28496 // MIs[1] Operand 1
28497 // No operand predicates
28498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28500 GIM_CheckIsSafeToFold, /*InsnID*/1,
28501 // (intrinsic_wo_chain:{ *:[v4i32] } 2000:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
28502 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28503 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28504 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCADDi32,
28506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28509 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28510 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28511 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28512 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28513 GIR_EraseFromParent, /*InsnID*/0,
28514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28515 // GIR_Coverage, 4465,
28516 GIR_Done,
28517 // Label 1455: @74818
28518 GIM_Try, /*On fail goto*//*Label 1456*/ 74915, // Rule ID 4467 //
28519 GIM_CheckFeatures, GIFBS_HasMVEInt,
28520 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28521 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28522 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28523 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28524 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
28525 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
28526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28527 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
28528 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28529 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28530 // MIs[1] Operand 1
28531 // No operand predicates
28532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28534 GIM_CheckIsSafeToFold, /*InsnID*/1,
28535 // (intrinsic_wo_chain:{ *:[v16i8] } 2000:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
28536 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs8,
28540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28543 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28544 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28545 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28547 GIR_EraseFromParent, /*InsnID*/0,
28548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28549 // GIR_Coverage, 4467,
28550 GIR_Done,
28551 // Label 1456: @74915
28552 GIM_Try, /*On fail goto*//*Label 1457*/ 75012, // Rule ID 4469 //
28553 GIM_CheckFeatures, GIFBS_HasMVEInt,
28554 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28555 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28556 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28557 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28558 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28559 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
28560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28561 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
28562 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28563 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28564 // MIs[1] Operand 1
28565 // No operand predicates
28566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28568 GIM_CheckIsSafeToFold, /*InsnID*/1,
28569 // (intrinsic_wo_chain:{ *:[v8i16] } 2000:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
28570 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28571 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28572 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs16,
28574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28577 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28578 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28579 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28580 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28581 GIR_EraseFromParent, /*InsnID*/0,
28582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28583 // GIR_Coverage, 4469,
28584 GIR_Done,
28585 // Label 1457: @75012
28586 GIM_Try, /*On fail goto*//*Label 1458*/ 75109, // Rule ID 4471 //
28587 GIM_CheckFeatures, GIFBS_HasMVEInt,
28588 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcaddq,
28589 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28590 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28591 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28592 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28593 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
28594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28595 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
28596 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28597 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28598 // MIs[1] Operand 1
28599 // No operand predicates
28600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28602 GIM_CheckIsSafeToFold, /*InsnID*/1,
28603 // (intrinsic_wo_chain:{ *:[v4i32] } 2000:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
28604 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28605 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28606 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VHCADDs32,
28608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28611 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28612 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28613 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28614 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28615 GIR_EraseFromParent, /*InsnID*/0,
28616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28617 // GIR_Coverage, 4471,
28618 GIR_Done,
28619 // Label 1458: @75109
28620 GIM_Try, /*On fail goto*//*Label 1459*/ 75188, // Rule ID 3031 //
28621 GIM_CheckFeatures, GIFBS_HasMVEInt,
28622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
28623 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
28624 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28625 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28626 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
28627 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
28628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
28629 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
28630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
28631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28633 // (intrinsic_wo_chain:{ *:[i32] } 1993:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
28634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs8,
28635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
28636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
28637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28639 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28640 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28641 GIR_EraseFromParent, /*InsnID*/0,
28642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28643 // GIR_Coverage, 3031,
28644 GIR_Done,
28645 // Label 1459: @75188
28646 GIM_Try, /*On fail goto*//*Label 1460*/ 75267, // Rule ID 3033 //
28647 GIM_CheckFeatures, GIFBS_HasMVEInt,
28648 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
28649 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
28650 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28651 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28652 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28653 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
28654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
28655 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
28656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
28657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28659 // (intrinsic_wo_chain:{ *:[i32] } 1993:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
28660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs16,
28661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
28662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
28663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28665 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28666 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28667 GIR_EraseFromParent, /*InsnID*/0,
28668 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28669 // GIR_Coverage, 3033,
28670 GIR_Done,
28671 // Label 1460: @75267
28672 GIM_Try, /*On fail goto*//*Label 1461*/ 75346, // Rule ID 3035 //
28673 GIM_CheckFeatures, GIFBS_HasMVEInt,
28674 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
28675 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
28676 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28677 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28678 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28679 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
28680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
28681 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
28682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
28683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28685 // (intrinsic_wo_chain:{ *:[i32] } 1993:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
28686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVs32,
28687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
28688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
28689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28691 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28692 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28693 GIR_EraseFromParent, /*InsnID*/0,
28694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28695 // GIR_Coverage, 3035,
28696 GIR_Done,
28697 // Label 1461: @75346
28698 GIM_Try, /*On fail goto*//*Label 1462*/ 75425, // Rule ID 3037 //
28699 GIM_CheckFeatures, GIFBS_HasMVEInt,
28700 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
28701 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
28702 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28703 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28704 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
28705 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v16s8,
28706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
28707 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
28709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28711 // (intrinsic_wo_chain:{ *:[i32] } 1993:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
28712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu8,
28713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
28714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
28715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28717 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28718 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28719 GIR_EraseFromParent, /*InsnID*/0,
28720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28721 // GIR_Coverage, 3037,
28722 GIR_Done,
28723 // Label 1462: @75425
28724 GIM_Try, /*On fail goto*//*Label 1463*/ 75504, // Rule ID 3039 //
28725 GIM_CheckFeatures, GIFBS_HasMVEInt,
28726 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
28727 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
28728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28729 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28730 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28731 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
28732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
28733 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
28735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28737 // (intrinsic_wo_chain:{ *:[i32] } 1993:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
28738 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu16,
28739 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
28740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
28741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28743 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28744 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28745 GIR_EraseFromParent, /*InsnID*/0,
28746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28747 // GIR_Coverage, 3039,
28748 GIR_Done,
28749 // Label 1463: @75504
28750 GIM_Try, /*On fail goto*//*Label 1464*/ 75583, // Rule ID 3041 //
28751 GIM_CheckFeatures, GIFBS_HasMVEInt,
28752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vabav,
28753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
28754 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28755 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
28756 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28757 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
28758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
28759 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
28760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
28761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28763 // (intrinsic_wo_chain:{ *:[i32] } 1993:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
28764 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABAVu32,
28765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rda
28766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rda_src
28767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28769 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28770 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28771 GIR_EraseFromParent, /*InsnID*/0,
28772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28773 // GIR_Coverage, 3041,
28774 GIR_Done,
28775 // Label 1464: @75583
28776 GIM_Try, /*On fail goto*//*Label 1465*/ 75670, // Rule ID 3948 //
28777 GIM_CheckFeatures, GIFBS_HasMVEFloat,
28778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq,
28779 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28780 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28781 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28782 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
28783 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s16,
28784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28785 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
28786 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28787 // MIs[1] Operand 1
28788 // No operand predicates
28789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28792 GIM_CheckIsSafeToFold, /*InsnID*/1,
28793 // (intrinsic_wo_chain:{ *:[v8f16] } 2003:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
28794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf16,
28795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
28797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28799 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28800 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28801 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28802 GIR_EraseFromParent, /*InsnID*/0,
28803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28804 // GIR_Coverage, 3948,
28805 GIR_Done,
28806 // Label 1465: @75670
28807 GIM_Try, /*On fail goto*//*Label 1466*/ 75757, // Rule ID 3950 //
28808 GIM_CheckFeatures, GIFBS_HasMVEFloat,
28809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vcmlaq,
28810 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
28812 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28813 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
28814 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
28815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
28817 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
28818 // MIs[1] Operand 1
28819 // No operand predicates
28820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
28822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::MQPRRegClassID,
28823 GIM_CheckIsSafeToFold, /*InsnID*/1,
28824 // (intrinsic_wo_chain:{ *:[v4f32] } 2003:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
28825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMLAf32,
28826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qd_src
28828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Qn
28829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Qm
28830 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28831 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28832 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28833 GIR_EraseFromParent, /*InsnID*/0,
28834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28835 // GIR_Coverage, 3950,
28836 GIR_Done,
28837 // Label 1466: @75757
28838 GIM_Try, /*On fail goto*//*Label 1467*/ 75856, // Rule ID 2603 //
28839 GIM_CheckFeatures, GIFBS_HasNEON,
28840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx2,
28841 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
28842 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
28843 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
28844 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
28845 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
28846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28847 // (intrinsic_wo_chain:{ *:[v8i8] } 2257:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
28848 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28849 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
28850 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
28851 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
28852 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
28853 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
28854 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
28855 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::DPairRegClassID,
28856 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
28857 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
28858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX2,
28859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
28860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
28861 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
28863 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28864 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28865 GIR_EraseFromParent, /*InsnID*/0,
28866 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28867 // GIR_Coverage, 2603,
28868 GIR_Done,
28869 // Label 1467: @75856
28870 GIM_Try, /*On fail goto*//*Label 1468*/ 75985, // Rule ID 2604 //
28871 GIM_CheckFeatures, GIFBS_HasNEON,
28872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl3,
28873 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
28874 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
28875 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
28876 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
28877 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
28878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
28879 // (intrinsic_wo_chain:{ *:[v8i8] } 2254:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
28880 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
28881 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
28882 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28883 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
28884 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28885 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
28886 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
28887 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
28888 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
28889 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
28890 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
28891 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
28892 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
28893 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
28894 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
28895 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
28896 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
28897 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
28898 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
28899 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
28900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL3Pseudo,
28901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
28902 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // Vm
28904 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
28905 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28906 GIR_EraseFromParent, /*InsnID*/0,
28907 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28908 // GIR_Coverage, 2604,
28909 GIR_Done,
28910 // Label 1468: @75985
28911 GIM_Reject,
28912 // Label 1430: @75986
28913 GIM_Try, /*On fail goto*//*Label 1469*/ 81446,
28914 GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
28915 GIM_Try, /*On fail goto*//*Label 1470*/ 76086, // Rule ID 3804 //
28916 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
28917 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
28918 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
28919 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
28920 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28921 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28922 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28926 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28927 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28928 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28929 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
28930 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28931 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28932 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs8,
28934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
28936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
28937 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28938 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28939 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28940 GIR_EraseFromParent, /*InsnID*/0,
28941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28942 // GIR_Coverage, 3804,
28943 GIR_Done,
28944 // Label 1470: @76086
28945 GIM_Try, /*On fail goto*//*Label 1471*/ 76181, // Rule ID 3806 //
28946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
28947 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
28948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
28949 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
28950 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28951 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28952 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28956 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28957 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28958 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28959 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
28960 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28961 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28962 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs16,
28964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
28966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
28967 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28968 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28969 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
28970 GIR_EraseFromParent, /*InsnID*/0,
28971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
28972 // GIR_Coverage, 3806,
28973 GIR_Done,
28974 // Label 1471: @76181
28975 GIM_Try, /*On fail goto*//*Label 1472*/ 76276, // Rule ID 3808 //
28976 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
28977 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
28978 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
28979 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
28980 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
28981 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
28982 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
28983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
28984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
28985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
28986 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
28987 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
28988 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
28989 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
28990 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28991 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
28992 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
28993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecs32,
28994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
28995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
28996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
28997 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
28998 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
28999 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29000 GIR_EraseFromParent, /*InsnID*/0,
29001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29002 // GIR_Coverage, 3808,
29003 GIR_Done,
29004 // Label 1472: @76276
29005 GIM_Try, /*On fail goto*//*Label 1473*/ 76371, // Rule ID 3810 //
29006 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29007 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29008 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29009 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29010 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29011 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29012 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29016 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29017 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29018 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29019 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29020 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29021 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29022 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu8,
29024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29027 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29028 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29029 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29030 GIR_EraseFromParent, /*InsnID*/0,
29031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29032 // GIR_Coverage, 3810,
29033 GIR_Done,
29034 // Label 1473: @76371
29035 GIM_Try, /*On fail goto*//*Label 1474*/ 76466, // Rule ID 3812 //
29036 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29037 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29038 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29039 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29040 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29041 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29042 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29046 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29047 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29048 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29049 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29050 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29051 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29052 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu16,
29054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29057 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29058 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29059 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29060 GIR_EraseFromParent, /*InsnID*/0,
29061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29062 // GIR_Coverage, 3812,
29063 GIR_Done,
29064 // Label 1474: @76466
29065 GIM_Try, /*On fail goto*//*Label 1475*/ 76561, // Rule ID 3814 //
29066 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29067 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29068 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29069 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29070 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29071 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29072 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29076 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29077 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29078 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29079 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29080 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29081 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29082 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_by_vecu32,
29084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29087 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29088 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29089 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29090 GIR_EraseFromParent, /*InsnID*/0,
29091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29092 // GIR_Coverage, 3814,
29093 GIR_Done,
29094 // Label 1475: @76561
29095 GIM_Try, /*On fail goto*//*Label 1476*/ 76656, // Rule ID 3816 //
29096 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29097 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29099 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29100 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29101 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29102 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29106 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29107 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29108 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29109 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29110 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29111 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29112 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs8,
29114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29117 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29118 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29119 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29120 GIR_EraseFromParent, /*InsnID*/0,
29121 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29122 // GIR_Coverage, 3816,
29123 GIR_Done,
29124 // Label 1476: @76656
29125 GIM_Try, /*On fail goto*//*Label 1477*/ 76751, // Rule ID 3818 //
29126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29127 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29128 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29129 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29130 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29131 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29132 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29136 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29137 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29138 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29139 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29140 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29141 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29142 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29143 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs16,
29144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29147 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29148 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29149 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29150 GIR_EraseFromParent, /*InsnID*/0,
29151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29152 // GIR_Coverage, 3818,
29153 GIR_Done,
29154 // Label 1477: @76751
29155 GIM_Try, /*On fail goto*//*Label 1478*/ 76846, // Rule ID 3820 //
29156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29157 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29158 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29159 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29160 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29161 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29162 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29166 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29167 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29168 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29169 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29170 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29171 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29172 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecs32,
29174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29177 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29178 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29179 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29180 GIR_EraseFromParent, /*InsnID*/0,
29181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29182 // GIR_Coverage, 3820,
29183 GIR_Done,
29184 // Label 1478: @76846
29185 GIM_Try, /*On fail goto*//*Label 1479*/ 76941, // Rule ID 3822 //
29186 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29187 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29188 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29189 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29190 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29191 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29192 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29196 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29197 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29198 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29199 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29200 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29201 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29202 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu8,
29204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29207 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29208 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29209 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29210 GIR_EraseFromParent, /*InsnID*/0,
29211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29212 // GIR_Coverage, 3822,
29213 GIR_Done,
29214 // Label 1479: @76941
29215 GIM_Try, /*On fail goto*//*Label 1480*/ 77036, // Rule ID 3824 //
29216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29217 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29218 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29219 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29220 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29221 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29222 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29226 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29227 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29228 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29229 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29230 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29231 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29232 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu16,
29234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29237 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29238 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29239 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29240 GIR_EraseFromParent, /*InsnID*/0,
29241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29242 // GIR_Coverage, 3824,
29243 GIR_Done,
29244 // Label 1480: @77036
29245 GIM_Try, /*On fail goto*//*Label 1481*/ 77131, // Rule ID 3826 //
29246 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29247 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29248 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29249 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29250 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29251 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29252 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29256 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29257 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29258 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29259 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29260 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29261 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29262 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_by_vecu32,
29264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29267 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29268 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29269 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29270 GIR_EraseFromParent, /*InsnID*/0,
29271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29272 // GIR_Coverage, 3826,
29273 GIR_Done,
29274 // Label 1481: @77131
29275 GIM_Try, /*On fail goto*//*Label 1482*/ 77226, // Rule ID 3828 //
29276 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29277 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29278 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29279 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29280 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29281 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29282 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29286 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29287 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29288 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29289 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29290 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29291 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29292 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs8,
29294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29297 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29298 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29299 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29300 GIR_EraseFromParent, /*InsnID*/0,
29301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29302 // GIR_Coverage, 3828,
29303 GIR_Done,
29304 // Label 1482: @77226
29305 GIM_Try, /*On fail goto*//*Label 1483*/ 77321, // Rule ID 3830 //
29306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29307 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29308 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29309 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29310 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29311 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29312 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29316 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29317 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29318 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29319 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29321 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29322 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs16,
29324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29327 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29328 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29329 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29330 GIR_EraseFromParent, /*InsnID*/0,
29331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29332 // GIR_Coverage, 3830,
29333 GIR_Done,
29334 // Label 1483: @77321
29335 GIM_Try, /*On fail goto*//*Label 1484*/ 77416, // Rule ID 3832 //
29336 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29337 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29338 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29339 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29340 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29341 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29342 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29346 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29347 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29348 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29349 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29350 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29351 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29352 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecs32,
29354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29357 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29358 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29359 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29360 GIR_EraseFromParent, /*InsnID*/0,
29361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29362 // GIR_Coverage, 3832,
29363 GIR_Done,
29364 // Label 1484: @77416
29365 GIM_Try, /*On fail goto*//*Label 1485*/ 77511, // Rule ID 3834 //
29366 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29367 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29368 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29369 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29370 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29371 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29372 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29376 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29377 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29378 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29379 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29380 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29381 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29382 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu8,
29384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29387 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29388 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29389 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29390 GIR_EraseFromParent, /*InsnID*/0,
29391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29392 // GIR_Coverage, 3834,
29393 GIR_Done,
29394 // Label 1485: @77511
29395 GIM_Try, /*On fail goto*//*Label 1486*/ 77606, // Rule ID 3836 //
29396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29397 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29399 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29400 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29401 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29402 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29406 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29407 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29408 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29409 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29410 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29411 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29412 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu16,
29414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29417 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29418 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29419 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29420 GIR_EraseFromParent, /*InsnID*/0,
29421 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29422 // GIR_Coverage, 3836,
29423 GIR_Done,
29424 // Label 1486: @77606
29425 GIM_Try, /*On fail goto*//*Label 1487*/ 77701, // Rule ID 3838 //
29426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29427 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29429 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29430 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29431 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29432 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29436 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29437 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29438 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29439 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29440 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29441 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29442 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_by_vecu32,
29444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29447 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29448 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29449 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29450 GIR_EraseFromParent, /*InsnID*/0,
29451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29452 // GIR_Coverage, 3838,
29453 GIR_Done,
29454 // Label 1487: @77701
29455 GIM_Try, /*On fail goto*//*Label 1488*/ 77796, // Rule ID 3840 //
29456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29457 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29458 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29459 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29460 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29461 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29462 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29466 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29467 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29468 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29469 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29470 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29471 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29472 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs8,
29474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29477 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29478 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29479 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29480 GIR_EraseFromParent, /*InsnID*/0,
29481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29482 // GIR_Coverage, 3840,
29483 GIR_Done,
29484 // Label 1488: @77796
29485 GIM_Try, /*On fail goto*//*Label 1489*/ 77891, // Rule ID 3842 //
29486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29487 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29489 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29490 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29491 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29492 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29496 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29497 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29498 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29499 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29500 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29501 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29502 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs16,
29504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29507 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29508 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29509 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29510 GIR_EraseFromParent, /*InsnID*/0,
29511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29512 // GIR_Coverage, 3842,
29513 GIR_Done,
29514 // Label 1489: @77891
29515 GIM_Try, /*On fail goto*//*Label 1490*/ 77986, // Rule ID 3844 //
29516 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29517 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29518 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29519 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29520 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29521 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29522 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29526 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29527 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29528 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29529 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29530 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29531 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29532 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecs32,
29534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29537 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29538 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29539 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29540 GIR_EraseFromParent, /*InsnID*/0,
29541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29542 // GIR_Coverage, 3844,
29543 GIR_Done,
29544 // Label 1490: @77986
29545 GIM_Try, /*On fail goto*//*Label 1491*/ 78081, // Rule ID 3846 //
29546 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29547 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29548 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29549 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
29550 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29551 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29552 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29556 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29557 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29558 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29559 // (intrinsic_wo_chain:{ *:[v16i8] } 2098:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29560 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29561 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29562 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu8,
29564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29567 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29568 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29569 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29570 GIR_EraseFromParent, /*InsnID*/0,
29571 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29572 // GIR_Coverage, 3846,
29573 GIR_Done,
29574 // Label 1491: @78081
29575 GIM_Try, /*On fail goto*//*Label 1492*/ 78176, // Rule ID 3848 //
29576 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29577 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29578 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29579 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29580 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29581 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29582 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29586 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29587 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29588 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29589 // (intrinsic_wo_chain:{ *:[v8i16] } 2098:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29590 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29591 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29592 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu16,
29594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29597 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29598 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29599 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29600 GIR_EraseFromParent, /*InsnID*/0,
29601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29602 // GIR_Coverage, 3848,
29603 GIR_Done,
29604 // Label 1492: @78176
29605 GIM_Try, /*On fail goto*//*Label 1493*/ 78271, // Rule ID 3850 //
29606 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_vector,
29607 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
29608 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
29609 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29610 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29611 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29612 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29616 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29617 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29618 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29619 // (intrinsic_wo_chain:{ *:[v4i32] } 2098:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29620 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29621 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
29622 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
29623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_by_vecu32,
29624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29627 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29628 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29629 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
29630 GIR_EraseFromParent, /*InsnID*/0,
29631 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29632 // GIR_Coverage, 3850,
29633 GIR_Done,
29634 // Label 1493: @78271
29635 GIM_Try, /*On fail goto*//*Label 1494*/ 78352, // Rule ID 4409 //
29636 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29637 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29638 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29639 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29640 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29641 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29642 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29644 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29646 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29647 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29648 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29649 // (intrinsic_wo_chain:{ *:[v8i16] } 2068:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs32bh,
29651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29654 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29655 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29656 GIR_EraseFromParent, /*InsnID*/0,
29657 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29658 // GIR_Coverage, 4409,
29659 GIR_Done,
29660 // Label 1494: @78352
29661 GIM_Try, /*On fail goto*//*Label 1495*/ 78433, // Rule ID 4411 //
29662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29663 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29664 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29665 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29666 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29667 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29668 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29672 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29673 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29674 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29675 // (intrinsic_wo_chain:{ *:[v8i16] } 2068:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs32th,
29677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29680 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29681 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29682 GIR_EraseFromParent, /*InsnID*/0,
29683 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29684 // GIR_Coverage, 4411,
29685 GIR_Done,
29686 // Label 1495: @78433
29687 GIM_Try, /*On fail goto*//*Label 1496*/ 78514, // Rule ID 4413 //
29688 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29689 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29690 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29691 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29692 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29693 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29694 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29698 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29699 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29700 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29701 // (intrinsic_wo_chain:{ *:[v16i8] } 2068:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs16bh,
29703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29706 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29707 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29708 GIR_EraseFromParent, /*InsnID*/0,
29709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29710 // GIR_Coverage, 4413,
29711 GIR_Done,
29712 // Label 1496: @78514
29713 GIM_Try, /*On fail goto*//*Label 1497*/ 78595, // Rule ID 4415 //
29714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29715 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29716 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29717 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29718 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29719 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29720 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29724 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29725 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29726 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29727 // (intrinsic_wo_chain:{ *:[v16i8] } 2068:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNs16th,
29729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29732 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29733 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29734 GIR_EraseFromParent, /*InsnID*/0,
29735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29736 // GIR_Coverage, 4415,
29737 GIR_Done,
29738 // Label 1497: @78595
29739 GIM_Try, /*On fail goto*//*Label 1498*/ 78676, // Rule ID 4417 //
29740 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29741 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29742 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29743 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29744 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29745 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29746 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29750 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29751 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29752 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29753 // (intrinsic_wo_chain:{ *:[v8i16] } 2068:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu32bh,
29755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29758 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29759 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29760 GIR_EraseFromParent, /*InsnID*/0,
29761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29762 // GIR_Coverage, 4417,
29763 GIR_Done,
29764 // Label 1498: @78676
29765 GIM_Try, /*On fail goto*//*Label 1499*/ 78757, // Rule ID 4419 //
29766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29767 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29768 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29769 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29770 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29771 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29772 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29776 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29777 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29778 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29779 // (intrinsic_wo_chain:{ *:[v8i16] } 2068:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu32th,
29781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29784 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29785 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29786 GIR_EraseFromParent, /*InsnID*/0,
29787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29788 // GIR_Coverage, 4419,
29789 GIR_Done,
29790 // Label 1499: @78757
29791 GIM_Try, /*On fail goto*//*Label 1500*/ 78838, // Rule ID 4421 //
29792 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29793 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29794 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29795 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29796 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29797 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29798 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29802 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29803 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29804 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29805 // (intrinsic_wo_chain:{ *:[v16i8] } 2068:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu16bh,
29807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29809 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29810 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29811 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29812 GIR_EraseFromParent, /*InsnID*/0,
29813 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29814 // GIR_Coverage, 4421,
29815 GIR_Done,
29816 // Label 1500: @78838
29817 GIM_Try, /*On fail goto*//*Label 1501*/ 78919, // Rule ID 4423 //
29818 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29819 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29820 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29821 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29822 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29823 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29824 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29828 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29829 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
29830 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29831 // (intrinsic_wo_chain:{ *:[v16i8] } 2068:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVNu16th,
29833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29836 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29837 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29838 GIR_EraseFromParent, /*InsnID*/0,
29839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29840 // GIR_Coverage, 4423,
29841 GIR_Done,
29842 // Label 1501: @78919
29843 GIM_Try, /*On fail goto*//*Label 1502*/ 79000, // Rule ID 4425 //
29844 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29845 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29846 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29847 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29848 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29849 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29850 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29854 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29855 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29856 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29857 // (intrinsic_wo_chain:{ *:[v8i16] } 2068:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs32bh,
29859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29862 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29863 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29864 GIR_EraseFromParent, /*InsnID*/0,
29865 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29866 // GIR_Coverage, 4425,
29867 GIR_Done,
29868 // Label 1502: @79000
29869 GIM_Try, /*On fail goto*//*Label 1503*/ 79081, // Rule ID 4427 //
29870 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29871 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29872 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29873 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
29874 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29875 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29876 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29880 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29881 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29882 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29883 // (intrinsic_wo_chain:{ *:[v8i16] } 2068:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs32th,
29885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29888 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29889 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29890 GIR_EraseFromParent, /*InsnID*/0,
29891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29892 // GIR_Coverage, 4427,
29893 GIR_Done,
29894 // Label 1503: @79081
29895 GIM_Try, /*On fail goto*//*Label 1504*/ 79162, // Rule ID 4429 //
29896 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29897 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29898 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29899 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29900 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29901 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29902 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29906 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29907 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29908 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29909 // (intrinsic_wo_chain:{ *:[v16i8] } 2068:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs16bh,
29911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29914 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29915 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29916 GIR_EraseFromParent, /*InsnID*/0,
29917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29918 // GIR_Coverage, 4429,
29919 GIR_Done,
29920 // Label 1504: @79162
29921 GIM_Try, /*On fail goto*//*Label 1505*/ 79243, // Rule ID 4431 //
29922 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqmovn,
29923 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29924 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29925 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
29926 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29927 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29928 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
29932 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
29933 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29934 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
29935 // (intrinsic_wo_chain:{ *:[v16i8] } 2068:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQMOVUNs16th,
29937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd_src
29939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
29940 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29942 GIR_EraseFromParent, /*InsnID*/0,
29943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29944 // GIR_Coverage, 4431,
29945 GIR_Done,
29946 // Label 1505: @79243
29947 GIM_Try, /*On fail goto*//*Label 1506*/ 79324, // Rule ID 4581 //
29948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
29949 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
29950 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
29951 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29952 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29953 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29954 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29958 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29959 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29960 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29961 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
29962 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs8,
29963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29966 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29967 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29968 GIR_EraseFromParent, /*InsnID*/0,
29969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29970 // GIR_Coverage, 4581,
29971 GIR_Done,
29972 // Label 1506: @79324
29973 GIM_Try, /*On fail goto*//*Label 1507*/ 79405, // Rule ID 4583 //
29974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
29975 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
29976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
29977 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
29978 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
29979 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
29980 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
29981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
29982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
29983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
29984 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
29985 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
29986 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
29987 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
29988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs16,
29989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
29990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
29991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
29992 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
29993 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
29994 GIR_EraseFromParent, /*InsnID*/0,
29995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
29996 // GIR_Coverage, 4583,
29997 GIR_Done,
29998 // Label 1507: @79405
29999 GIM_Try, /*On fail goto*//*Label 1508*/ 79486, // Rule ID 4585 //
30000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30001 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30003 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30004 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30005 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30006 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30010 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30011 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30012 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30013 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qrs32,
30015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30018 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30019 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30020 GIR_EraseFromParent, /*InsnID*/0,
30021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30022 // GIR_Coverage, 4585,
30023 GIR_Done,
30024 // Label 1508: @79486
30025 GIM_Try, /*On fail goto*//*Label 1509*/ 79567, // Rule ID 4587 //
30026 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30027 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30028 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30029 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30030 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30031 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30032 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30036 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30037 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30038 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30039 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30040 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru8,
30041 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30044 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30045 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30046 GIR_EraseFromParent, /*InsnID*/0,
30047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30048 // GIR_Coverage, 4587,
30049 GIR_Done,
30050 // Label 1509: @79567
30051 GIM_Try, /*On fail goto*//*Label 1510*/ 79648, // Rule ID 4589 //
30052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30053 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30055 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30056 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30057 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30058 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30062 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30063 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30064 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30065 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru16,
30067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30070 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30071 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30072 GIR_EraseFromParent, /*InsnID*/0,
30073 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30074 // GIR_Coverage, 4589,
30075 GIR_Done,
30076 // Label 1510: @79648
30077 GIM_Try, /*On fail goto*//*Label 1511*/ 79729, // Rule ID 4591 //
30078 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30079 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30080 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30081 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30082 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30083 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30084 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30088 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30089 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30090 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30091 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHL_qru32,
30093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30096 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30097 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30098 GIR_EraseFromParent, /*InsnID*/0,
30099 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30100 // GIR_Coverage, 4591,
30101 GIR_Done,
30102 // Label 1511: @79729
30103 GIM_Try, /*On fail goto*//*Label 1512*/ 79810, // Rule ID 4593 //
30104 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30105 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30106 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30107 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30108 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30109 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30110 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30114 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30115 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30116 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30117 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs8,
30119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30122 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30123 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30124 GIR_EraseFromParent, /*InsnID*/0,
30125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30126 // GIR_Coverage, 4593,
30127 GIR_Done,
30128 // Label 1512: @79810
30129 GIM_Try, /*On fail goto*//*Label 1513*/ 79891, // Rule ID 4595 //
30130 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30131 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30132 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30133 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30134 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30135 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30136 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30140 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30141 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30142 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30143 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs16,
30145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30148 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30149 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30150 GIR_EraseFromParent, /*InsnID*/0,
30151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30152 // GIR_Coverage, 4595,
30153 GIR_Done,
30154 // Label 1513: @79891
30155 GIM_Try, /*On fail goto*//*Label 1514*/ 79972, // Rule ID 4597 //
30156 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30157 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30158 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30159 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30160 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30161 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30162 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30166 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30167 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30168 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30169 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30170 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qrs32,
30171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30174 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30175 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30176 GIR_EraseFromParent, /*InsnID*/0,
30177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30178 // GIR_Coverage, 4597,
30179 GIR_Done,
30180 // Label 1514: @79972
30181 GIM_Try, /*On fail goto*//*Label 1515*/ 80053, // Rule ID 4599 //
30182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30183 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30184 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30185 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30186 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30187 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30188 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30192 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30193 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30194 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30195 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru8,
30197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30200 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30201 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30202 GIR_EraseFromParent, /*InsnID*/0,
30203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30204 // GIR_Coverage, 4599,
30205 GIR_Done,
30206 // Label 1515: @80053
30207 GIM_Try, /*On fail goto*//*Label 1516*/ 80134, // Rule ID 4601 //
30208 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30209 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30210 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30211 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30212 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30213 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30214 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30218 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30219 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30220 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30221 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru16,
30223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30226 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30227 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30228 GIR_EraseFromParent, /*InsnID*/0,
30229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30230 // GIR_Coverage, 4601,
30231 GIR_Done,
30232 // Label 1516: @80134
30233 GIM_Try, /*On fail goto*//*Label 1517*/ 80215, // Rule ID 4603 //
30234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30235 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30237 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30238 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30239 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30240 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30244 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30245 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30246 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30247 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHL_qru32,
30249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30252 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30253 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30254 GIR_EraseFromParent, /*InsnID*/0,
30255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30256 // GIR_Coverage, 4603,
30257 GIR_Done,
30258 // Label 1517: @80215
30259 GIM_Try, /*On fail goto*//*Label 1518*/ 80296, // Rule ID 4605 //
30260 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30261 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30262 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30263 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30264 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30265 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30266 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30270 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30271 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30272 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30273 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs8,
30275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30278 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30279 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30280 GIR_EraseFromParent, /*InsnID*/0,
30281 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30282 // GIR_Coverage, 4605,
30283 GIR_Done,
30284 // Label 1518: @80296
30285 GIM_Try, /*On fail goto*//*Label 1519*/ 80377, // Rule ID 4607 //
30286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30287 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30288 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30289 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30290 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30291 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30292 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30296 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30297 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30298 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30299 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs16,
30301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30304 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30305 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30306 GIR_EraseFromParent, /*InsnID*/0,
30307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30308 // GIR_Coverage, 4607,
30309 GIR_Done,
30310 // Label 1519: @80377
30311 GIM_Try, /*On fail goto*//*Label 1520*/ 80458, // Rule ID 4609 //
30312 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30313 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30314 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30315 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30316 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30317 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30318 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30322 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30323 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30324 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30325 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qrs32,
30327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30330 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30331 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30332 GIR_EraseFromParent, /*InsnID*/0,
30333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30334 // GIR_Coverage, 4609,
30335 GIR_Done,
30336 // Label 1520: @80458
30337 GIM_Try, /*On fail goto*//*Label 1521*/ 80539, // Rule ID 4611 //
30338 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30339 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30340 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30341 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30342 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30343 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30344 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30348 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30349 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30350 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30351 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru8,
30353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30356 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30357 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30358 GIR_EraseFromParent, /*InsnID*/0,
30359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30360 // GIR_Coverage, 4611,
30361 GIR_Done,
30362 // Label 1521: @80539
30363 GIM_Try, /*On fail goto*//*Label 1522*/ 80620, // Rule ID 4613 //
30364 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30365 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30367 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30368 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30369 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30370 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30374 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30375 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30376 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30377 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru16,
30379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30382 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30383 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30384 GIR_EraseFromParent, /*InsnID*/0,
30385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30386 // GIR_Coverage, 4613,
30387 GIR_Done,
30388 // Label 1522: @80620
30389 GIM_Try, /*On fail goto*//*Label 1523*/ 80701, // Rule ID 4615 //
30390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30391 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30392 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30393 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30394 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30395 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30396 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30400 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30401 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30402 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30403 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30404 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHL_qru32,
30405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30408 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30409 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30410 GIR_EraseFromParent, /*InsnID*/0,
30411 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30412 // GIR_Coverage, 4615,
30413 GIR_Done,
30414 // Label 1523: @80701
30415 GIM_Try, /*On fail goto*//*Label 1524*/ 80782, // Rule ID 4617 //
30416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30417 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30418 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30419 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30420 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30421 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30422 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30426 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30427 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30428 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30429 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs8,
30431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30434 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30435 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30436 GIR_EraseFromParent, /*InsnID*/0,
30437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30438 // GIR_Coverage, 4617,
30439 GIR_Done,
30440 // Label 1524: @80782
30441 GIM_Try, /*On fail goto*//*Label 1525*/ 80863, // Rule ID 4619 //
30442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30443 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30444 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30445 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30446 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30447 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30448 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30452 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30453 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30454 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30455 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs16,
30457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30460 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30461 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30462 GIR_EraseFromParent, /*InsnID*/0,
30463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30464 // GIR_Coverage, 4619,
30465 GIR_Done,
30466 // Label 1525: @80863
30467 GIM_Try, /*On fail goto*//*Label 1526*/ 80944, // Rule ID 4621 //
30468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30469 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30471 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30472 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30473 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30474 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30478 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30479 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30480 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
30481 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qrs32,
30483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30486 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30487 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30488 GIR_EraseFromParent, /*InsnID*/0,
30489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30490 // GIR_Coverage, 4621,
30491 GIR_Done,
30492 // Label 1526: @80944
30493 GIM_Try, /*On fail goto*//*Label 1527*/ 81025, // Rule ID 4623 //
30494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30495 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
30496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
30497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30498 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30499 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30500 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30504 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30505 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30506 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30507 // (intrinsic_wo_chain:{ *:[v16i8] } 2096:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru8,
30509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30512 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30513 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30514 GIR_EraseFromParent, /*InsnID*/0,
30515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30516 // GIR_Coverage, 4623,
30517 GIR_Done,
30518 // Label 1527: @81025
30519 GIM_Try, /*On fail goto*//*Label 1528*/ 81106, // Rule ID 4625 //
30520 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30521 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
30522 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
30523 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30524 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30525 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30526 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30530 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30531 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30532 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30533 // (intrinsic_wo_chain:{ *:[v8i16] } 2096:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru16,
30535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30538 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30539 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30540 GIR_EraseFromParent, /*InsnID*/0,
30541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30542 // GIR_Coverage, 4625,
30543 GIR_Done,
30544 // Label 1528: @81106
30545 GIM_Try, /*On fail goto*//*Label 1529*/ 81187, // Rule ID 4627 //
30546 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshl_scalar,
30547 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
30548 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
30549 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30550 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30551 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30552 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
30553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
30554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
30555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
30556 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30557 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
30558 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
30559 // (intrinsic_wo_chain:{ *:[v4i32] } 2096:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHL_qru32,
30561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
30562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // in
30563 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // sh
30564 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30565 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30566 GIR_EraseFromParent, /*InsnID*/0,
30567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30568 // GIR_Coverage, 4627,
30569 GIR_Done,
30570 // Label 1529: @81187
30571 GIM_Try, /*On fail goto*//*Label 1530*/ 81324, // Rule ID 2605 //
30572 GIM_CheckFeatures, GIFBS_HasNEON,
30573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx3,
30574 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
30575 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
30576 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
30577 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
30578 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
30579 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
30580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
30581 // (intrinsic_wo_chain:{ *:[v8i8] } 2258:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30582 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30583 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
30584 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
30585 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
30586 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
30587 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
30588 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
30589 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
30590 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
30591 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
30592 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
30593 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
30594 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
30595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
30596 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
30597 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
30598 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
30599 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
30600 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
30601 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
30602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX3Pseudo,
30603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
30604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
30605 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
30607 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30608 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30609 GIR_EraseFromParent, /*InsnID*/0,
30610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30611 // GIR_Coverage, 2605,
30612 GIR_Done,
30613 // Label 1530: @81324
30614 GIM_Try, /*On fail goto*//*Label 1531*/ 81445, // Rule ID 2606 //
30615 GIM_CheckFeatures, GIFBS_HasNEON,
30616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbl4,
30617 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
30618 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
30619 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
30620 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
30621 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
30622 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
30623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
30624 // (intrinsic_wo_chain:{ *:[v8i8] } 2255:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30625 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30626 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
30627 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
30628 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
30629 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
30630 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
30631 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
30632 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
30633 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
30634 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
30635 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
30636 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
30637 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
30638 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
30639 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
30640 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
30641 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBL4Pseudo,
30642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
30643 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
30644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Vm
30645 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
30646 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30647 GIR_EraseFromParent, /*InsnID*/0,
30648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30649 // GIR_Coverage, 2606,
30650 GIR_Done,
30651 // Label 1531: @81445
30652 GIM_Reject,
30653 // Label 1469: @81446
30654 GIM_Try, /*On fail goto*//*Label 1532*/ 86603,
30655 GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
30656 GIM_Try, /*On fail goto*//*Label 1533*/ 81542, // Rule ID 3175 //
30657 GIM_CheckFeatures, GIFBS_HasMVEInt,
30658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30659 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30661 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30662 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30663 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30664 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
30665 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
30666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30667 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30668 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30669 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30670 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30673 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs8,
30675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30678 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30679 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30680 GIR_EraseFromParent, /*InsnID*/0,
30681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30682 // GIR_Coverage, 3175,
30683 GIR_Done,
30684 // Label 1533: @81542
30685 GIM_Try, /*On fail goto*//*Label 1534*/ 81633, // Rule ID 3179 //
30686 GIM_CheckFeatures, GIFBS_HasMVEInt,
30687 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30688 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30689 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30690 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30691 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30692 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30693 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
30694 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
30695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30696 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30697 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30698 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30699 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30702 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs8,
30704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30707 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30708 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30709 GIR_EraseFromParent, /*InsnID*/0,
30710 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30711 // GIR_Coverage, 3179,
30712 GIR_Done,
30713 // Label 1534: @81633
30714 GIM_Try, /*On fail goto*//*Label 1535*/ 81724, // Rule ID 3183 //
30715 GIM_CheckFeatures, GIFBS_HasMVEInt,
30716 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30717 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30718 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30719 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30720 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30721 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30722 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
30723 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
30724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30725 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
30726 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30727 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30728 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30731 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu8,
30733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30736 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30737 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30738 GIR_EraseFromParent, /*InsnID*/0,
30739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30740 // GIR_Coverage, 3183,
30741 GIR_Done,
30742 // Label 1535: @81724
30743 GIM_Try, /*On fail goto*//*Label 1536*/ 81815, // Rule ID 3187 //
30744 GIM_CheckFeatures, GIFBS_HasMVEInt,
30745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30746 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30747 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30748 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30749 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30750 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30751 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
30752 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
30753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30754 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30755 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30756 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30757 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30760 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs16,
30762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30765 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30766 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30767 GIR_EraseFromParent, /*InsnID*/0,
30768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30769 // GIR_Coverage, 3187,
30770 GIR_Done,
30771 // Label 1536: @81815
30772 GIM_Try, /*On fail goto*//*Label 1537*/ 81906, // Rule ID 3191 //
30773 GIM_CheckFeatures, GIFBS_HasMVEInt,
30774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30778 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30779 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30780 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
30781 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
30782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30783 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30784 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30785 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30786 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30789 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs16,
30791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30794 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30795 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30796 GIR_EraseFromParent, /*InsnID*/0,
30797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30798 // GIR_Coverage, 3191,
30799 GIR_Done,
30800 // Label 1537: @81906
30801 GIM_Try, /*On fail goto*//*Label 1538*/ 81997, // Rule ID 3195 //
30802 GIM_CheckFeatures, GIFBS_HasMVEInt,
30803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30804 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30805 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30806 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30807 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30808 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30809 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
30810 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
30811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30812 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
30813 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30814 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30815 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30818 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu16,
30820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30823 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30824 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30825 GIR_EraseFromParent, /*InsnID*/0,
30826 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30827 // GIR_Coverage, 3195,
30828 GIR_Done,
30829 // Label 1538: @81997
30830 GIM_Try, /*On fail goto*//*Label 1539*/ 82088, // Rule ID 3199 //
30831 GIM_CheckFeatures, GIFBS_HasMVEInt,
30832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30833 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30834 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30835 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30836 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30837 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30838 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
30839 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
30840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30841 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30842 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30843 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30844 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30847 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVs32,
30849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30852 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30853 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30854 GIR_EraseFromParent, /*InsnID*/0,
30855 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30856 // GIR_Coverage, 3199,
30857 GIR_Done,
30858 // Label 1539: @82088
30859 GIM_Try, /*On fail goto*//*Label 1540*/ 82179, // Rule ID 3203 //
30860 GIM_CheckFeatures, GIFBS_HasMVEInt,
30861 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30862 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30863 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30864 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30865 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30866 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30867 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
30868 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
30869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30870 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30871 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30872 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30873 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30876 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVxs32,
30878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30881 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30882 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30883 GIR_EraseFromParent, /*InsnID*/0,
30884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30885 // GIR_Coverage, 3203,
30886 GIR_Done,
30887 // Label 1540: @82179
30888 GIM_Try, /*On fail goto*//*Label 1541*/ 82270, // Rule ID 3207 //
30889 GIM_CheckFeatures, GIFBS_HasMVEInt,
30890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30891 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30892 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30893 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30894 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30895 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30896 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
30897 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
30898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30899 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
30900 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
30901 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30902 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30905 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVu32,
30907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30910 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30911 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30912 GIR_EraseFromParent, /*InsnID*/0,
30913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30914 // GIR_Coverage, 3207,
30915 GIR_Done,
30916 // Label 1541: @82270
30917 GIM_Try, /*On fail goto*//*Label 1542*/ 82361, // Rule ID 3211 //
30918 GIM_CheckFeatures, GIFBS_HasMVEInt,
30919 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30920 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30921 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30922 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30923 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30924 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30925 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
30926 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
30927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30928 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30929 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
30930 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30931 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30934 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs8,
30936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30939 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30940 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30941 GIR_EraseFromParent, /*InsnID*/0,
30942 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30943 // GIR_Coverage, 3211,
30944 GIR_Done,
30945 // Label 1542: @82361
30946 GIM_Try, /*On fail goto*//*Label 1543*/ 82452, // Rule ID 3215 //
30947 GIM_CheckFeatures, GIFBS_HasMVEInt,
30948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30949 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30950 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30951 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30952 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30953 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30954 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
30955 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
30956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30957 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30958 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
30959 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
30960 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30963 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs8,
30965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30968 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30969 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30970 GIR_EraseFromParent, /*InsnID*/0,
30971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
30972 // GIR_Coverage, 3215,
30973 GIR_Done,
30974 // Label 1543: @82452
30975 GIM_Try, /*On fail goto*//*Label 1544*/ 82543, // Rule ID 3219 //
30976 GIM_CheckFeatures, GIFBS_HasMVEInt,
30977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
30978 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
30979 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
30980 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
30981 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
30982 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
30983 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
30984 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
30985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
30986 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
30987 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
30988 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
30989 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
30990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
30991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
30992 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs16,
30994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
30995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
30996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
30997 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
30998 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
30999 GIR_EraseFromParent, /*InsnID*/0,
31000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31001 // GIR_Coverage, 3219,
31002 GIR_Done,
31003 // Label 1544: @82543
31004 GIM_Try, /*On fail goto*//*Label 1545*/ 82634, // Rule ID 3223 //
31005 GIM_CheckFeatures, GIFBS_HasMVEInt,
31006 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31007 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31008 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31009 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31010 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31011 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31012 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31013 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31015 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31016 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31017 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31018 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31021 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs16,
31023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31026 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31027 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31028 GIR_EraseFromParent, /*InsnID*/0,
31029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31030 // GIR_Coverage, 3223,
31031 GIR_Done,
31032 // Label 1545: @82634
31033 GIM_Try, /*On fail goto*//*Label 1546*/ 82725, // Rule ID 3227 //
31034 GIM_CheckFeatures, GIFBS_HasMVEInt,
31035 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31036 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31037 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31038 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31039 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31040 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31041 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31042 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31044 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31045 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31046 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31047 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31050 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVs32,
31052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31055 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31056 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31057 GIR_EraseFromParent, /*InsnID*/0,
31058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31059 // GIR_Coverage, 3227,
31060 GIR_Done,
31061 // Label 1546: @82725
31062 GIM_Try, /*On fail goto*//*Label 1547*/ 82816, // Rule ID 3231 //
31063 GIM_CheckFeatures, GIFBS_HasMVEInt,
31064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31065 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31066 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31067 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31068 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31069 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31070 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31071 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31073 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31074 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31075 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31076 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31079 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVxs32,
31081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31084 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31085 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31086 GIR_EraseFromParent, /*InsnID*/0,
31087 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31088 // GIR_Coverage, 3231,
31089 GIR_Done,
31090 // Label 1547: @82816
31091 GIM_Try, /*On fail goto*//*Label 1548*/ 82911, // Rule ID 3177 //
31092 GIM_CheckFeatures, GIFBS_HasMVEInt,
31093 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31094 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31095 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31096 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31097 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31098 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31099 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31100 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31102 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31103 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31104 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31108 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas8,
31110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31114 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31115 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31116 GIR_EraseFromParent, /*InsnID*/0,
31117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31118 // GIR_Coverage, 3177,
31119 GIR_Done,
31120 // Label 1548: @82911
31121 GIM_Try, /*On fail goto*//*Label 1549*/ 83006, // Rule ID 3181 //
31122 GIM_CheckFeatures, GIFBS_HasMVEInt,
31123 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31124 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31125 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31126 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31127 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31128 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31129 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31130 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31132 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31133 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31134 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31138 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs8,
31140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31144 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31145 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31146 GIR_EraseFromParent, /*InsnID*/0,
31147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31148 // GIR_Coverage, 3181,
31149 GIR_Done,
31150 // Label 1549: @83006
31151 GIM_Try, /*On fail goto*//*Label 1550*/ 83101, // Rule ID 3185 //
31152 GIM_CheckFeatures, GIFBS_HasMVEInt,
31153 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31154 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31155 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31156 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31157 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31158 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31159 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31160 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31162 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
31163 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31164 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31168 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau8,
31170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31174 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31175 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31176 GIR_EraseFromParent, /*InsnID*/0,
31177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31178 // GIR_Coverage, 3185,
31179 GIR_Done,
31180 // Label 1550: @83101
31181 GIM_Try, /*On fail goto*//*Label 1551*/ 83196, // Rule ID 3189 //
31182 GIM_CheckFeatures, GIFBS_HasMVEInt,
31183 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31184 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31185 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31186 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31187 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31188 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31189 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31190 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31192 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31193 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31194 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31198 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas16,
31200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31204 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31205 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31206 GIR_EraseFromParent, /*InsnID*/0,
31207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31208 // GIR_Coverage, 3189,
31209 GIR_Done,
31210 // Label 1551: @83196
31211 GIM_Try, /*On fail goto*//*Label 1552*/ 83291, // Rule ID 3193 //
31212 GIM_CheckFeatures, GIFBS_HasMVEInt,
31213 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31214 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31215 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31216 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31217 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31218 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31219 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31220 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31222 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31223 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31224 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31228 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs16,
31230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31234 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31235 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31236 GIR_EraseFromParent, /*InsnID*/0,
31237 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31238 // GIR_Coverage, 3193,
31239 GIR_Done,
31240 // Label 1552: @83291
31241 GIM_Try, /*On fail goto*//*Label 1553*/ 83386, // Rule ID 3197 //
31242 GIM_CheckFeatures, GIFBS_HasMVEInt,
31243 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31244 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31245 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31246 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31247 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31248 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31249 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31250 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31252 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
31253 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31254 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31258 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau16,
31260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31264 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31265 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31266 GIR_EraseFromParent, /*InsnID*/0,
31267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31268 // GIR_Coverage, 3197,
31269 GIR_Done,
31270 // Label 1553: @83386
31271 GIM_Try, /*On fail goto*//*Label 1554*/ 83481, // Rule ID 3201 //
31272 GIM_CheckFeatures, GIFBS_HasMVEInt,
31273 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31274 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31275 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31276 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31277 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31278 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31279 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31280 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31282 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31283 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31284 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31288 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVas32,
31290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31294 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31295 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31296 GIR_EraseFromParent, /*InsnID*/0,
31297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31298 // GIR_Coverage, 3201,
31299 GIR_Done,
31300 // Label 1554: @83481
31301 GIM_Try, /*On fail goto*//*Label 1555*/ 83576, // Rule ID 3205 //
31302 GIM_CheckFeatures, GIFBS_HasMVEInt,
31303 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31304 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31305 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31306 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31307 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31308 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31309 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31310 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31312 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31313 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31314 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31318 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVaxs32,
31320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31324 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31325 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31326 GIR_EraseFromParent, /*InsnID*/0,
31327 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31328 // GIR_Coverage, 3205,
31329 GIR_Done,
31330 // Label 1555: @83576
31331 GIM_Try, /*On fail goto*//*Label 1556*/ 83671, // Rule ID 3209 //
31332 GIM_CheckFeatures, GIFBS_HasMVEInt,
31333 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31334 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31335 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31336 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31337 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31338 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31339 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31340 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31342 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
31343 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
31344 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31348 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLADAVau32,
31350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31354 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31355 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31356 GIR_EraseFromParent, /*InsnID*/0,
31357 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31358 // GIR_Coverage, 3209,
31359 GIR_Done,
31360 // Label 1556: @83671
31361 GIM_Try, /*On fail goto*//*Label 1557*/ 83766, // Rule ID 3213 //
31362 GIM_CheckFeatures, GIFBS_HasMVEInt,
31363 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31364 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31366 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31367 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31368 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31369 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31370 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31372 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31373 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31374 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31378 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas8,
31380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31384 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31385 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31386 GIR_EraseFromParent, /*InsnID*/0,
31387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31388 // GIR_Coverage, 3213,
31389 GIR_Done,
31390 // Label 1557: @83766
31391 GIM_Try, /*On fail goto*//*Label 1558*/ 83861, // Rule ID 3217 //
31392 GIM_CheckFeatures, GIFBS_HasMVEInt,
31393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31394 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31396 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31397 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31398 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31399 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v16s8,
31400 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v16s8,
31401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31402 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31403 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31404 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31408 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31409 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs8,
31410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31414 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31415 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31416 GIR_EraseFromParent, /*InsnID*/0,
31417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31418 // GIR_Coverage, 3217,
31419 GIR_Done,
31420 // Label 1558: @83861
31421 GIM_Try, /*On fail goto*//*Label 1559*/ 83956, // Rule ID 3221 //
31422 GIM_CheckFeatures, GIFBS_HasMVEInt,
31423 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31424 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31425 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31426 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31427 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31428 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31429 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31430 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31432 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31433 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31434 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31438 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas16,
31440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31444 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31445 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31446 GIR_EraseFromParent, /*InsnID*/0,
31447 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31448 // GIR_Coverage, 3221,
31449 GIR_Done,
31450 // Label 1559: @83956
31451 GIM_Try, /*On fail goto*//*Label 1560*/ 84051, // Rule ID 3225 //
31452 GIM_CheckFeatures, GIFBS_HasMVEInt,
31453 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31454 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31455 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31456 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31457 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31458 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31459 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s16,
31460 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s16,
31461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31462 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31463 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31464 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31468 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs16,
31470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31474 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31475 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31476 GIR_EraseFromParent, /*InsnID*/0,
31477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31478 // GIR_Coverage, 3225,
31479 GIR_Done,
31480 // Label 1560: @84051
31481 GIM_Try, /*On fail goto*//*Label 1561*/ 84146, // Rule ID 3229 //
31482 GIM_CheckFeatures, GIFBS_HasMVEInt,
31483 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31484 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31485 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31486 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31487 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31488 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31489 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31490 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31492 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31493 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31494 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 0,
31495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31498 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31499 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVas32,
31500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31504 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31505 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31506 GIR_EraseFromParent, /*InsnID*/0,
31507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31508 // GIR_Coverage, 3229,
31509 GIR_Done,
31510 // Label 1561: @84146
31511 GIM_Try, /*On fail goto*//*Label 1562*/ 84241, // Rule ID 3233 //
31512 GIM_CheckFeatures, GIFBS_HasMVEInt,
31513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vmldava,
31514 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
31515 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
31516 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
31517 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
31518 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31519 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
31520 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v4s32,
31521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPREvenRegClassID,
31522 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
31523 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 1,
31524 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 1,
31525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/ARM::tGPREvenRegClassID,
31526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/ARM::MQPRRegClassID,
31527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/ARM::MQPRRegClassID,
31528 // (intrinsic_wo_chain:{ *:[i32] } 2050:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMLSDAVaxs32,
31530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // RdaDest
31531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // RdaSrc
31532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // Qn
31533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Qm
31534 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31535 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31536 GIR_EraseFromParent, /*InsnID*/0,
31537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31538 // GIR_Coverage, 3233,
31539 GIR_Done,
31540 // Label 1562: @84241
31541 GIM_Try, /*On fail goto*//*Label 1563*/ 84334, // Rule ID 4267 //
31542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31543 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31544 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31545 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31546 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
31547 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31548 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31549 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31554 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31555 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31556 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31557 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHs8,
31559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31563 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31564 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31565 GIR_EraseFromParent, /*InsnID*/0,
31566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31567 // GIR_Coverage, 4267,
31568 GIR_Done,
31569 // Label 1563: @84334
31570 GIM_Try, /*On fail goto*//*Label 1564*/ 84427, // Rule ID 4269 //
31571 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31572 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31573 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31574 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31575 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
31576 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31577 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31578 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31583 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31584 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31585 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31586 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHs16,
31588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31592 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31593 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31594 GIR_EraseFromParent, /*InsnID*/0,
31595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31596 // GIR_Coverage, 4269,
31597 GIR_Done,
31598 // Label 1564: @84427
31599 GIM_Try, /*On fail goto*//*Label 1565*/ 84520, // Rule ID 4271 //
31600 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31601 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31603 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31604 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
31605 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31606 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31607 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31612 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31613 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31614 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31615 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHs32,
31617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31620 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31621 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31622 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31623 GIR_EraseFromParent, /*InsnID*/0,
31624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31625 // GIR_Coverage, 4271,
31626 GIR_Done,
31627 // Label 1565: @84520
31628 GIM_Try, /*On fail goto*//*Label 1566*/ 84613, // Rule ID 4273 //
31629 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31630 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31631 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31632 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31633 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
31634 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31635 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31636 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31641 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31642 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31643 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31644 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31645 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHXs8,
31646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31649 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31650 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31651 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31652 GIR_EraseFromParent, /*InsnID*/0,
31653 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31654 // GIR_Coverage, 4273,
31655 GIR_Done,
31656 // Label 1566: @84613
31657 GIM_Try, /*On fail goto*//*Label 1567*/ 84706, // Rule ID 4275 //
31658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31659 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31660 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31661 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31662 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
31663 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31664 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31665 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31670 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31671 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31672 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31673 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHXs16,
31675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31679 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31680 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31681 GIR_EraseFromParent, /*InsnID*/0,
31682 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31683 // GIR_Coverage, 4275,
31684 GIR_Done,
31685 // Label 1567: @84706
31686 GIM_Try, /*On fail goto*//*Label 1568*/ 84799, // Rule ID 4277 //
31687 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31688 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31689 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31690 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31691 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
31692 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31693 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31694 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31699 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31700 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31701 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31702 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLADHXs32,
31704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31708 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31709 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31710 GIR_EraseFromParent, /*InsnID*/0,
31711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31712 // GIR_Coverage, 4277,
31713 GIR_Done,
31714 // Label 1568: @84799
31715 GIM_Try, /*On fail goto*//*Label 1569*/ 84892, // Rule ID 4279 //
31716 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31717 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31718 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31719 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31720 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
31721 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31722 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31723 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31728 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31729 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31730 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31731 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHs8,
31733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31737 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31738 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31739 GIR_EraseFromParent, /*InsnID*/0,
31740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31741 // GIR_Coverage, 4279,
31742 GIR_Done,
31743 // Label 1569: @84892
31744 GIM_Try, /*On fail goto*//*Label 1570*/ 84985, // Rule ID 4281 //
31745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31746 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31747 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31748 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31749 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
31750 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31751 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31752 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31757 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31758 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31759 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31760 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHs16,
31762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31766 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31767 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31768 GIR_EraseFromParent, /*InsnID*/0,
31769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31770 // GIR_Coverage, 4281,
31771 GIR_Done,
31772 // Label 1570: @84985
31773 GIM_Try, /*On fail goto*//*Label 1571*/ 85078, // Rule ID 4283 //
31774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31775 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31777 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31778 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
31779 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31780 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31781 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31786 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31787 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31788 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31789 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHs32,
31791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31795 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31796 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31797 GIR_EraseFromParent, /*InsnID*/0,
31798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31799 // GIR_Coverage, 4283,
31800 GIR_Done,
31801 // Label 1571: @85078
31802 GIM_Try, /*On fail goto*//*Label 1572*/ 85171, // Rule ID 4285 //
31803 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31804 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31805 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31806 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31807 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
31808 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31809 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31810 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31815 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31816 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31817 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31818 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHXs8,
31820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31824 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31825 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31826 GIR_EraseFromParent, /*InsnID*/0,
31827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31828 // GIR_Coverage, 4285,
31829 GIR_Done,
31830 // Label 1572: @85171
31831 GIM_Try, /*On fail goto*//*Label 1573*/ 85264, // Rule ID 4287 //
31832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31833 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31834 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31835 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31836 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
31837 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31838 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31839 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31844 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31845 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31846 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31847 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHXs16,
31849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31853 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31854 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31855 GIR_EraseFromParent, /*InsnID*/0,
31856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31857 // GIR_Coverage, 4287,
31858 GIR_Done,
31859 // Label 1573: @85264
31860 GIM_Try, /*On fail goto*//*Label 1574*/ 85357, // Rule ID 4289 //
31861 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31862 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31863 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31864 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31865 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
31866 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31867 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31868 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31873 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31874 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
31875 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
31876 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLADHXs32,
31878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31882 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31883 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31884 GIR_EraseFromParent, /*InsnID*/0,
31885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31886 // GIR_Coverage, 4289,
31887 GIR_Done,
31888 // Label 1574: @85357
31889 GIM_Try, /*On fail goto*//*Label 1575*/ 85450, // Rule ID 4291 //
31890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31891 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31892 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31893 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31894 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
31895 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31896 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31897 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31902 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31903 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31904 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
31905 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHs8,
31907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31911 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31912 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31913 GIR_EraseFromParent, /*InsnID*/0,
31914 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31915 // GIR_Coverage, 4291,
31916 GIR_Done,
31917 // Label 1575: @85450
31918 GIM_Try, /*On fail goto*//*Label 1576*/ 85543, // Rule ID 4293 //
31919 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31920 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
31921 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
31922 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
31923 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
31924 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31925 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31926 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31931 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31932 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31933 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
31934 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31935 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHs16,
31936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31940 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31942 GIR_EraseFromParent, /*InsnID*/0,
31943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31944 // GIR_Coverage, 4293,
31945 GIR_Done,
31946 // Label 1576: @85543
31947 GIM_Try, /*On fail goto*//*Label 1577*/ 85636, // Rule ID 4295 //
31948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31949 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
31950 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
31951 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
31952 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
31953 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31954 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31955 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31960 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
31961 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31962 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
31963 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHs32,
31965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31969 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31970 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
31971 GIR_EraseFromParent, /*InsnID*/0,
31972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
31973 // GIR_Coverage, 4295,
31974 GIR_Done,
31975 // Label 1577: @85636
31976 GIM_Try, /*On fail goto*//*Label 1578*/ 85729, // Rule ID 4297 //
31977 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
31978 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
31979 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
31980 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
31981 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
31982 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
31983 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
31984 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
31985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
31986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
31987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
31988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
31989 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
31990 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
31991 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
31992 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHXs8,
31994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
31995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
31996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
31997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
31998 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
31999 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32000 GIR_EraseFromParent, /*InsnID*/0,
32001 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32002 // GIR_Coverage, 4297,
32003 GIR_Done,
32004 // Label 1578: @85729
32005 GIM_Try, /*On fail goto*//*Label 1579*/ 85822, // Rule ID 4299 //
32006 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32007 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32008 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32009 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32010 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32011 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32012 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32013 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32018 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32019 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32020 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32021 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHXs16,
32023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32027 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32028 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32029 GIR_EraseFromParent, /*InsnID*/0,
32030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32031 // GIR_Coverage, 4299,
32032 GIR_Done,
32033 // Label 1579: @85822
32034 GIM_Try, /*On fail goto*//*Label 1580*/ 85915, // Rule ID 4301 //
32035 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32036 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32037 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32038 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32039 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32040 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32041 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32042 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32047 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32048 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32049 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32050 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQDMLSDHXs32,
32052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32056 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32057 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32058 GIR_EraseFromParent, /*InsnID*/0,
32059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32060 // GIR_Coverage, 4301,
32061 GIR_Done,
32062 // Label 1580: @85915
32063 GIM_Try, /*On fail goto*//*Label 1581*/ 86008, // Rule ID 4303 //
32064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32065 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32066 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32067 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32068 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32069 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32070 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32071 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32076 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32077 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32078 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32079 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHs8,
32081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32085 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32086 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32087 GIR_EraseFromParent, /*InsnID*/0,
32088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32089 // GIR_Coverage, 4303,
32090 GIR_Done,
32091 // Label 1581: @86008
32092 GIM_Try, /*On fail goto*//*Label 1582*/ 86101, // Rule ID 4305 //
32093 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32094 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32095 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32096 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32097 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32098 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32099 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32100 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32105 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32106 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32107 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32108 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHs16,
32110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32114 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32115 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32116 GIR_EraseFromParent, /*InsnID*/0,
32117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32118 // GIR_Coverage, 4305,
32119 GIR_Done,
32120 // Label 1582: @86101
32121 GIM_Try, /*On fail goto*//*Label 1583*/ 86194, // Rule ID 4307 //
32122 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32123 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32124 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32125 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32126 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32127 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32128 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32129 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32134 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32135 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32136 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32137 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHs32,
32139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32143 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32144 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32145 GIR_EraseFromParent, /*InsnID*/0,
32146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32147 // GIR_Coverage, 4307,
32148 GIR_Done,
32149 // Label 1583: @86194
32150 GIM_Try, /*On fail goto*//*Label 1584*/ 86287, // Rule ID 4309 //
32151 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32152 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32153 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32154 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
32155 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
32156 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32157 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32158 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32163 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32164 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32165 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32166 // (intrinsic_wo_chain:{ *:[v16i8] } 2059:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHXs8,
32168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32172 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32173 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32174 GIR_EraseFromParent, /*InsnID*/0,
32175 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32176 // GIR_Coverage, 4309,
32177 GIR_Done,
32178 // Label 1584: @86287
32179 GIM_Try, /*On fail goto*//*Label 1585*/ 86380, // Rule ID 4311 //
32180 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32181 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32182 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32183 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32184 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
32185 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32186 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32187 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32192 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32193 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32194 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32195 // (intrinsic_wo_chain:{ *:[v8i16] } 2059:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHXs16,
32197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32201 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32202 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32203 GIR_EraseFromParent, /*InsnID*/0,
32204 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32205 // GIR_Coverage, 4311,
32206 GIR_Done,
32207 // Label 1585: @86380
32208 GIM_Try, /*On fail goto*//*Label 1586*/ 86473, // Rule ID 4313 //
32209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vqdmlad,
32210 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
32211 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
32212 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32213 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
32214 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32215 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32216 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
32221 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32222 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32223 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32224 // (intrinsic_wo_chain:{ *:[v4i32] } 2059:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRDMLSDHXs32,
32226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
32228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
32229 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // c
32230 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32231 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32232 GIR_EraseFromParent, /*InsnID*/0,
32233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32234 // GIR_Coverage, 4313,
32235 GIR_Done,
32236 // Label 1586: @86473
32237 GIM_Try, /*On fail goto*//*Label 1587*/ 86602, // Rule ID 2607 //
32238 GIM_CheckFeatures, GIFBS_HasNEON,
32239 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx4,
32240 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
32241 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
32242 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
32243 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
32244 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v8s8,
32245 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s8,
32246 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_v8s8,
32247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
32248 // (intrinsic_wo_chain:{ *:[v8i8] } 2259:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
32249 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
32250 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE,
32251 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
32252 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
32253 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
32254 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
32255 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
32256 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
32257 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/3,
32258 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
32259 GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/4,
32260 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, ARM::QQPRRegClassID,
32261 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, ARM::DPRRegClassID,
32262 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, ARM::DPRRegClassID,
32263 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, ARM::DPRRegClassID,
32264 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, ARM::DPRRegClassID,
32265 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX4Pseudo,
32266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
32267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
32268 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
32269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // Vm
32270 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
32271 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32272 GIR_EraseFromParent, /*InsnID*/0,
32273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32274 // GIR_Coverage, 2607,
32275 GIR_Done,
32276 // Label 1587: @86602
32277 GIM_Reject,
32278 // Label 1532: @86603
32279 GIM_Try, /*On fail goto*//*Label 1588*/ 91093,
32280 GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
32281 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vshrn,
32282 GIM_Try, /*On fail goto*//*Label 1589*/ 86724, // Rule ID 3724 //
32283 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32284 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32285 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32286 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32287 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32288 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32289 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32290 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32291 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32295 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32296 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32297 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32298 // MIs[1] Operand 1
32299 // No operand predicates
32300 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32301 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32302 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32303 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32304 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32305 GIM_CheckIsSafeToFold, /*InsnID*/1,
32306 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh,
32308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32311 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32312 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32313 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32314 GIR_EraseFromParent, /*InsnID*/0,
32315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32316 // GIR_Coverage, 3724,
32317 GIR_Done,
32318 // Label 1589: @86724
32319 GIM_Try, /*On fail goto*//*Label 1590*/ 86836, // Rule ID 3726 //
32320 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32321 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32322 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32323 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32324 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32325 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32326 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32327 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32328 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32332 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32333 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32334 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32335 // MIs[1] Operand 1
32336 // No operand predicates
32337 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32338 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32339 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32340 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32341 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32342 GIM_CheckIsSafeToFold, /*InsnID*/1,
32343 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th,
32345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32348 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32349 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32350 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32351 GIR_EraseFromParent, /*InsnID*/0,
32352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32353 // GIR_Coverage, 3726,
32354 GIR_Done,
32355 // Label 1590: @86836
32356 GIM_Try, /*On fail goto*//*Label 1591*/ 86948, // Rule ID 3728 //
32357 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32358 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32359 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32360 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32361 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32362 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32363 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32364 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32365 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32369 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32370 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32371 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32372 // MIs[1] Operand 1
32373 // No operand predicates
32374 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32375 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32376 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32377 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32378 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32379 GIM_CheckIsSafeToFold, /*InsnID*/1,
32380 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32381 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh,
32382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32385 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32386 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32387 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32388 GIR_EraseFromParent, /*InsnID*/0,
32389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32390 // GIR_Coverage, 3728,
32391 GIR_Done,
32392 // Label 1591: @86948
32393 GIM_Try, /*On fail goto*//*Label 1592*/ 87060, // Rule ID 3730 //
32394 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32396 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32397 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32398 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32399 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32400 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32401 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32402 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32406 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32407 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32408 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32409 // MIs[1] Operand 1
32410 // No operand predicates
32411 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32412 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32413 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32414 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32415 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32416 GIM_CheckIsSafeToFold, /*InsnID*/1,
32417 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th,
32419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32422 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32423 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32424 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32425 GIR_EraseFromParent, /*InsnID*/0,
32426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32427 // GIR_Coverage, 3730,
32428 GIR_Done,
32429 // Label 1592: @87060
32430 GIM_Try, /*On fail goto*//*Label 1593*/ 87172, // Rule ID 3732 //
32431 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32432 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32433 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32434 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32435 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32436 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32437 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32438 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32439 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32443 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32444 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32445 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32446 // MIs[1] Operand 1
32447 // No operand predicates
32448 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32449 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32450 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32451 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32452 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32453 GIM_CheckIsSafeToFold, /*InsnID*/1,
32454 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16bh,
32456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32459 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32460 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32461 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32462 GIR_EraseFromParent, /*InsnID*/0,
32463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32464 // GIR_Coverage, 3732,
32465 GIR_Done,
32466 // Label 1593: @87172
32467 GIM_Try, /*On fail goto*//*Label 1594*/ 87284, // Rule ID 3734 //
32468 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32469 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32470 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32471 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32472 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32473 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32474 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32475 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32476 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32480 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32481 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32482 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32483 // MIs[1] Operand 1
32484 // No operand predicates
32485 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32486 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32487 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32488 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32489 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32490 GIM_CheckIsSafeToFold, /*InsnID*/1,
32491 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi16th,
32493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32496 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32497 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32498 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32499 GIR_EraseFromParent, /*InsnID*/0,
32500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32501 // GIR_Coverage, 3734,
32502 GIR_Done,
32503 // Label 1594: @87284
32504 GIM_Try, /*On fail goto*//*Label 1595*/ 87396, // Rule ID 3736 //
32505 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32506 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32507 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32508 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32509 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32510 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32511 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32512 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32513 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32517 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32518 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32519 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32520 // MIs[1] Operand 1
32521 // No operand predicates
32522 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32523 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32524 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32525 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32526 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32527 GIM_CheckIsSafeToFold, /*InsnID*/1,
32528 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32bh,
32530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32532 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32533 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32534 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32535 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32536 GIR_EraseFromParent, /*InsnID*/0,
32537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32538 // GIR_Coverage, 3736,
32539 GIR_Done,
32540 // Label 1595: @87396
32541 GIM_Try, /*On fail goto*//*Label 1596*/ 87508, // Rule ID 3738 //
32542 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32544 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32545 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32546 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32547 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32548 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32549 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32550 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32554 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32555 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32556 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32557 // MIs[1] Operand 1
32558 // No operand predicates
32559 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32560 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32561 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32562 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32563 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32564 GIM_CheckIsSafeToFold, /*InsnID*/1,
32565 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSHRNi32th,
32567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32570 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32571 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32572 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32573 GIR_EraseFromParent, /*InsnID*/0,
32574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32575 // GIR_Coverage, 3738,
32576 GIR_Done,
32577 // Label 1596: @87508
32578 GIM_Try, /*On fail goto*//*Label 1597*/ 87620, // Rule ID 3740 //
32579 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32580 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32581 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32582 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32583 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32584 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32585 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32586 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32587 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32591 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32592 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32593 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32594 // MIs[1] Operand 1
32595 // No operand predicates
32596 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32597 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32598 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32599 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32600 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32601 GIM_CheckIsSafeToFold, /*InsnID*/1,
32602 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh,
32604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32607 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32608 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32609 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32610 GIR_EraseFromParent, /*InsnID*/0,
32611 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32612 // GIR_Coverage, 3740,
32613 GIR_Done,
32614 // Label 1597: @87620
32615 GIM_Try, /*On fail goto*//*Label 1598*/ 87732, // Rule ID 3742 //
32616 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32617 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32618 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32619 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32620 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32621 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32622 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32623 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32624 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32628 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32629 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32630 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32631 // MIs[1] Operand 1
32632 // No operand predicates
32633 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32634 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32635 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32636 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32637 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32638 GIM_CheckIsSafeToFold, /*InsnID*/1,
32639 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th,
32641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32644 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32645 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32646 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32647 GIR_EraseFromParent, /*InsnID*/0,
32648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32649 // GIR_Coverage, 3742,
32650 GIR_Done,
32651 // Label 1598: @87732
32652 GIM_Try, /*On fail goto*//*Label 1599*/ 87844, // Rule ID 3744 //
32653 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32654 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32655 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32656 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32657 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32658 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32659 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32660 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32661 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32665 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32666 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32667 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32668 // MIs[1] Operand 1
32669 // No operand predicates
32670 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32671 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32672 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32673 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32674 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32675 GIM_CheckIsSafeToFold, /*InsnID*/1,
32676 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh,
32678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32681 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32682 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32683 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32684 GIR_EraseFromParent, /*InsnID*/0,
32685 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32686 // GIR_Coverage, 3744,
32687 GIR_Done,
32688 // Label 1599: @87844
32689 GIM_Try, /*On fail goto*//*Label 1600*/ 87956, // Rule ID 3746 //
32690 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32691 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32692 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32693 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32694 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32695 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32696 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32697 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32698 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32702 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32703 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32704 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32705 // MIs[1] Operand 1
32706 // No operand predicates
32707 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32708 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32709 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32710 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32711 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32712 GIM_CheckIsSafeToFold, /*InsnID*/1,
32713 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th,
32715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32718 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32719 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32720 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32721 GIR_EraseFromParent, /*InsnID*/0,
32722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32723 // GIR_Coverage, 3746,
32724 GIR_Done,
32725 // Label 1600: @87956
32726 GIM_Try, /*On fail goto*//*Label 1601*/ 88068, // Rule ID 3748 //
32727 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32729 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32730 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32731 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32732 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32733 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32734 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32735 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32739 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32740 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32741 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32742 // MIs[1] Operand 1
32743 // No operand predicates
32744 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32745 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32746 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32747 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32748 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32749 GIM_CheckIsSafeToFold, /*InsnID*/1,
32750 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16bh,
32752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32755 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32756 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32757 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32758 GIR_EraseFromParent, /*InsnID*/0,
32759 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32760 // GIR_Coverage, 3748,
32761 GIR_Done,
32762 // Label 1601: @88068
32763 GIM_Try, /*On fail goto*//*Label 1602*/ 88180, // Rule ID 3750 //
32764 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32765 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32766 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32767 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32768 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32769 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32770 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32771 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32772 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32777 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32778 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32779 // MIs[1] Operand 1
32780 // No operand predicates
32781 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32782 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32783 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32784 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32785 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32786 GIM_CheckIsSafeToFold, /*InsnID*/1,
32787 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32788 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi16th,
32789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32792 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32793 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32794 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32795 GIR_EraseFromParent, /*InsnID*/0,
32796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32797 // GIR_Coverage, 3750,
32798 GIR_Done,
32799 // Label 1602: @88180
32800 GIM_Try, /*On fail goto*//*Label 1603*/ 88292, // Rule ID 3752 //
32801 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32802 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32803 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32804 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32805 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32806 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32807 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32808 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32809 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32813 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32814 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32815 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32816 // MIs[1] Operand 1
32817 // No operand predicates
32818 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32819 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32820 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32821 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32822 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32823 GIM_CheckIsSafeToFold, /*InsnID*/1,
32824 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32bh,
32826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32829 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32830 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32831 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32832 GIR_EraseFromParent, /*InsnID*/0,
32833 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32834 // GIR_Coverage, 3752,
32835 GIR_Done,
32836 // Label 1603: @88292
32837 GIM_Try, /*On fail goto*//*Label 1604*/ 88404, // Rule ID 3754 //
32838 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32839 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32840 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32841 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32842 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32843 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32844 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32845 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32846 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32850 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32851 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32852 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32853 // MIs[1] Operand 1
32854 // No operand predicates
32855 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
32856 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
32857 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
32858 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
32859 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32860 GIM_CheckIsSafeToFold, /*InsnID*/1,
32861 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRSHRNi32th,
32863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32866 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32867 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32868 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32869 GIR_EraseFromParent, /*InsnID*/0,
32870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32871 // GIR_Coverage, 3754,
32872 GIR_Done,
32873 // Label 1604: @88404
32874 GIM_Try, /*On fail goto*//*Label 1605*/ 88516, // Rule ID 3756 //
32875 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32876 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32877 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32878 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32879 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32880 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32881 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32882 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32883 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32887 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32888 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32889 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32890 // MIs[1] Operand 1
32891 // No operand predicates
32892 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32893 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32894 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32895 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32896 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32897 GIM_CheckIsSafeToFold, /*InsnID*/1,
32898 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs16,
32900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32903 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32904 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32905 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32906 GIR_EraseFromParent, /*InsnID*/0,
32907 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32908 // GIR_Coverage, 3756,
32909 GIR_Done,
32910 // Label 1605: @88516
32911 GIM_Try, /*On fail goto*//*Label 1606*/ 88628, // Rule ID 3758 //
32912 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
32913 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
32914 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
32915 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32916 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32917 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32918 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32919 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32920 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32924 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32925 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32926 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
32927 // MIs[1] Operand 1
32928 // No operand predicates
32929 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32930 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32931 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32932 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32933 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
32934 GIM_CheckIsSafeToFold, /*InsnID*/1,
32935 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths16,
32937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32940 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32941 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32942 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32943 GIR_EraseFromParent, /*InsnID*/0,
32944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32945 // GIR_Coverage, 3758,
32946 GIR_Done,
32947 // Label 1606: @88628
32948 GIM_Try, /*On fail goto*//*Label 1607*/ 88740, // Rule ID 3760 //
32949 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32950 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32951 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32952 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32953 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32954 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32955 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32956 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32957 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32961 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32962 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
32963 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
32964 // MIs[1] Operand 1
32965 // No operand predicates
32966 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
32967 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
32968 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
32969 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
32970 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
32971 GIM_CheckIsSafeToFold, /*InsnID*/1,
32972 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhs32,
32974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
32975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
32976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
32977 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32978 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
32979 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
32980 GIR_EraseFromParent, /*InsnID*/0,
32981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
32982 // GIR_Coverage, 3760,
32983 GIR_Done,
32984 // Label 1607: @88740
32985 GIM_Try, /*On fail goto*//*Label 1608*/ 88852, // Rule ID 3762 //
32986 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
32987 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
32988 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
32989 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
32990 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
32991 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
32992 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
32993 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
32994 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
32995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
32996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
32997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
32998 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32999 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33000 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33001 // MIs[1] Operand 1
33002 // No operand predicates
33003 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33004 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33005 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33006 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33007 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33008 GIM_CheckIsSafeToFold, /*InsnID*/1,
33009 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNths32,
33011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33014 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33015 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33016 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33017 GIR_EraseFromParent, /*InsnID*/0,
33018 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33019 // GIR_Coverage, 3762,
33020 GIR_Done,
33021 // Label 1608: @88852
33022 GIM_Try, /*On fail goto*//*Label 1609*/ 88964, // Rule ID 3764 //
33023 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33025 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33026 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33027 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33028 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33029 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33030 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33031 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33035 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33036 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33037 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33038 // MIs[1] Operand 1
33039 // No operand predicates
33040 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33041 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33042 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33043 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33044 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33045 GIM_CheckIsSafeToFold, /*InsnID*/1,
33046 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu16,
33048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33051 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33052 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33053 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33054 GIR_EraseFromParent, /*InsnID*/0,
33055 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33056 // GIR_Coverage, 3764,
33057 GIR_Done,
33058 // Label 1609: @88964
33059 GIM_Try, /*On fail goto*//*Label 1610*/ 89076, // Rule ID 3766 //
33060 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33061 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33062 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33063 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33064 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33065 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33066 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33067 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33068 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33072 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33073 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33074 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33075 // MIs[1] Operand 1
33076 // No operand predicates
33077 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33078 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33079 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33080 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33081 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33082 GIM_CheckIsSafeToFold, /*InsnID*/1,
33083 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu16,
33085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33088 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33089 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33090 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33091 GIR_EraseFromParent, /*InsnID*/0,
33092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33093 // GIR_Coverage, 3766,
33094 GIR_Done,
33095 // Label 1610: @89076
33096 GIM_Try, /*On fail goto*//*Label 1611*/ 89188, // Rule ID 3768 //
33097 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33098 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33099 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33100 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33101 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33102 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33103 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33104 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33105 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33109 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33110 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33111 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33112 // MIs[1] Operand 1
33113 // No operand predicates
33114 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33115 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33116 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33117 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33118 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33119 GIM_CheckIsSafeToFold, /*InsnID*/1,
33120 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33121 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNbhu32,
33122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33125 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33126 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33127 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33128 GIR_EraseFromParent, /*InsnID*/0,
33129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33130 // GIR_Coverage, 3768,
33131 GIR_Done,
33132 // Label 1611: @89188
33133 GIM_Try, /*On fail goto*//*Label 1612*/ 89300, // Rule ID 3770 //
33134 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33135 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33136 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33137 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33138 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33139 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33140 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33141 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33142 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33147 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33148 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33149 // MIs[1] Operand 1
33150 // No operand predicates
33151 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33152 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33153 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33154 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33155 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33156 GIM_CheckIsSafeToFold, /*InsnID*/1,
33157 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRNthu32,
33159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33162 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33163 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33164 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33165 GIR_EraseFromParent, /*InsnID*/0,
33166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33167 // GIR_Coverage, 3770,
33168 GIR_Done,
33169 // Label 1612: @89300
33170 GIM_Try, /*On fail goto*//*Label 1613*/ 89412, // Rule ID 3772 //
33171 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33172 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33173 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33174 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33175 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33176 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33177 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33178 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33179 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33183 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33184 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33185 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33186 // MIs[1] Operand 1
33187 // No operand predicates
33188 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33189 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33190 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33191 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33192 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33193 GIM_CheckIsSafeToFold, /*InsnID*/1,
33194 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs16,
33196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33199 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33200 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33201 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33202 GIR_EraseFromParent, /*InsnID*/0,
33203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33204 // GIR_Coverage, 3772,
33205 GIR_Done,
33206 // Label 1613: @89412
33207 GIM_Try, /*On fail goto*//*Label 1614*/ 89524, // Rule ID 3774 //
33208 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33209 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33210 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33211 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33212 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33213 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33214 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33215 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33216 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33220 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33221 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33222 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33223 // MIs[1] Operand 1
33224 // No operand predicates
33225 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33226 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33227 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33228 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33229 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33230 GIM_CheckIsSafeToFold, /*InsnID*/1,
33231 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths16,
33233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33236 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33237 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33238 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33239 GIR_EraseFromParent, /*InsnID*/0,
33240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33241 // GIR_Coverage, 3774,
33242 GIR_Done,
33243 // Label 1614: @89524
33244 GIM_Try, /*On fail goto*//*Label 1615*/ 89636, // Rule ID 3776 //
33245 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33246 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33247 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33248 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33249 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33250 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33251 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33252 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33253 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33257 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33258 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33259 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33260 // MIs[1] Operand 1
33261 // No operand predicates
33262 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33263 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33264 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33265 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33266 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33267 GIM_CheckIsSafeToFold, /*InsnID*/1,
33268 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33269 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhs32,
33270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33273 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33274 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33275 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33276 GIR_EraseFromParent, /*InsnID*/0,
33277 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33278 // GIR_Coverage, 3776,
33279 GIR_Done,
33280 // Label 1615: @89636
33281 GIM_Try, /*On fail goto*//*Label 1616*/ 89748, // Rule ID 3778 //
33282 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33283 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33284 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33285 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33286 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33287 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33288 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33289 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33290 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33294 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33295 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33296 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33297 // MIs[1] Operand 1
33298 // No operand predicates
33299 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33300 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33301 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 0,
33302 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33303 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33304 GIM_CheckIsSafeToFold, /*InsnID*/1,
33305 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNths32,
33307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33310 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33311 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33312 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33313 GIR_EraseFromParent, /*InsnID*/0,
33314 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33315 // GIR_Coverage, 3778,
33316 GIR_Done,
33317 // Label 1616: @89748
33318 GIM_Try, /*On fail goto*//*Label 1617*/ 89860, // Rule ID 3780 //
33319 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33320 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33321 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33322 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33323 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33324 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33325 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33326 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33327 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33331 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33332 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33333 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33334 // MIs[1] Operand 1
33335 // No operand predicates
33336 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33337 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33338 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33339 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33340 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33341 GIM_CheckIsSafeToFold, /*InsnID*/1,
33342 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu16,
33344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33347 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33348 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33349 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33350 GIR_EraseFromParent, /*InsnID*/0,
33351 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33352 // GIR_Coverage, 3780,
33353 GIR_Done,
33354 // Label 1617: @89860
33355 GIM_Try, /*On fail goto*//*Label 1618*/ 89972, // Rule ID 3782 //
33356 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33357 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33358 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33359 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33360 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33361 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33362 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33363 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33364 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33368 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33369 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33370 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33371 // MIs[1] Operand 1
33372 // No operand predicates
33373 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33374 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33375 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33376 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33377 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33378 GIM_CheckIsSafeToFold, /*InsnID*/1,
33379 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu16,
33381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33384 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33385 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33386 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33387 GIR_EraseFromParent, /*InsnID*/0,
33388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33389 // GIR_Coverage, 3782,
33390 GIR_Done,
33391 // Label 1618: @89972
33392 GIM_Try, /*On fail goto*//*Label 1619*/ 90084, // Rule ID 3784 //
33393 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33394 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33395 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33396 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33397 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33398 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33399 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33400 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33401 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33405 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33406 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33407 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33408 // MIs[1] Operand 1
33409 // No operand predicates
33410 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33411 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33412 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33413 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33414 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33415 GIM_CheckIsSafeToFold, /*InsnID*/1,
33416 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNbhu32,
33418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33421 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33422 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33423 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33424 GIR_EraseFromParent, /*InsnID*/0,
33425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33426 // GIR_Coverage, 3784,
33427 GIR_Done,
33428 // Label 1619: @90084
33429 GIM_Try, /*On fail goto*//*Label 1620*/ 90196, // Rule ID 3786 //
33430 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33431 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33432 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33433 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33434 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33435 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33436 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33437 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33438 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33442 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33443 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33444 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33445 // MIs[1] Operand 1
33446 // No operand predicates
33447 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33448 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33449 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33450 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 1,
33451 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33452 GIM_CheckIsSafeToFold, /*InsnID*/1,
33453 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRNthu32,
33455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33458 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33459 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33460 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33461 GIR_EraseFromParent, /*InsnID*/0,
33462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33463 // GIR_Coverage, 3786,
33464 GIR_Done,
33465 // Label 1620: @90196
33466 GIM_Try, /*On fail goto*//*Label 1621*/ 90308, // Rule ID 3788 //
33467 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33468 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33469 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33470 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33471 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33472 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33473 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33474 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33475 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33479 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33480 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33481 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33482 // MIs[1] Operand 1
33483 // No operand predicates
33484 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33485 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33486 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33487 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33488 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33489 GIM_CheckIsSafeToFold, /*InsnID*/1,
33490 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16bh,
33492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33495 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33496 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33497 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33498 GIR_EraseFromParent, /*InsnID*/0,
33499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33500 // GIR_Coverage, 3788,
33501 GIR_Done,
33502 // Label 1621: @90308
33503 GIM_Try, /*On fail goto*//*Label 1622*/ 90420, // Rule ID 3790 //
33504 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33505 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33506 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33507 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33508 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33509 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33510 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33511 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33512 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33516 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33517 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33518 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33519 // MIs[1] Operand 1
33520 // No operand predicates
33521 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33522 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33523 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33524 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33525 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33526 GIM_CheckIsSafeToFold, /*InsnID*/1,
33527 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33528 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs16th,
33529 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33532 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33533 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33534 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33535 GIR_EraseFromParent, /*InsnID*/0,
33536 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33537 // GIR_Coverage, 3790,
33538 GIR_Done,
33539 // Label 1622: @90420
33540 GIM_Try, /*On fail goto*//*Label 1623*/ 90532, // Rule ID 3792 //
33541 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33542 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33543 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33544 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33545 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33546 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33547 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33548 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33549 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33553 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33554 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33555 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33556 // MIs[1] Operand 1
33557 // No operand predicates
33558 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33559 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33560 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33561 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33562 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33563 GIM_CheckIsSafeToFold, /*InsnID*/1,
33564 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32bh,
33566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33569 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33570 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33571 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33572 GIR_EraseFromParent, /*InsnID*/0,
33573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33574 // GIR_Coverage, 3792,
33575 GIR_Done,
33576 // Label 1623: @90532
33577 GIM_Try, /*On fail goto*//*Label 1624*/ 90644, // Rule ID 3794 //
33578 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33579 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33580 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33581 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33582 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33583 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33584 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33585 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33586 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33587 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33590 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33591 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33592 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33593 // MIs[1] Operand 1
33594 // No operand predicates
33595 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33596 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
33597 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33598 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33599 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33600 GIM_CheckIsSafeToFold, /*InsnID*/1,
33601 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSHRUNs32th,
33603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33606 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33607 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33608 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33609 GIR_EraseFromParent, /*InsnID*/0,
33610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33611 // GIR_Coverage, 3794,
33612 GIR_Done,
33613 // Label 1624: @90644
33614 GIM_Try, /*On fail goto*//*Label 1625*/ 90756, // Rule ID 3796 //
33615 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33617 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33618 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33619 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33620 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33621 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33622 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33623 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33627 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33628 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33629 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33630 // MIs[1] Operand 1
33631 // No operand predicates
33632 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33633 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33634 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33635 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33636 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33637 GIM_CheckIsSafeToFold, /*InsnID*/1,
33638 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16bh,
33640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33643 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33644 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33645 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33646 GIR_EraseFromParent, /*InsnID*/0,
33647 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33648 // GIR_Coverage, 3796,
33649 GIR_Done,
33650 // Label 1625: @90756
33651 GIM_Try, /*On fail goto*//*Label 1626*/ 90868, // Rule ID 3798 //
33652 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
33653 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
33654 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
33655 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33656 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33657 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33658 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33659 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33660 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33665 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33666 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm8,
33667 // MIs[1] Operand 1
33668 // No operand predicates
33669 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33670 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33671 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33672 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33673 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33674 GIM_CheckIsSafeToFold, /*InsnID*/1,
33675 // (intrinsic_wo_chain:{ *:[v16i8] } 2104:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs16th,
33677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33680 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33681 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33682 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33683 GIR_EraseFromParent, /*InsnID*/0,
33684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33685 // GIR_Coverage, 3798,
33686 GIR_Done,
33687 // Label 1626: @90868
33688 GIM_Try, /*On fail goto*//*Label 1627*/ 90980, // Rule ID 3800 //
33689 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33690 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33691 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33692 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33693 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33694 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33695 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33696 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33697 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33701 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33702 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33703 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33704 // MIs[1] Operand 1
33705 // No operand predicates
33706 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33707 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33708 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33709 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33710 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 0,
33711 GIM_CheckIsSafeToFold, /*InsnID*/1,
33712 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32bh,
33714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33717 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33718 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33719 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33720 GIR_EraseFromParent, /*InsnID*/0,
33721 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33722 // GIR_Coverage, 3800,
33723 GIR_Done,
33724 // Label 1627: @90980
33725 GIM_Try, /*On fail goto*//*Label 1628*/ 91092, // Rule ID 3802 //
33726 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
33727 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
33728 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
33729 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
33730 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
33731 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
33732 GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
33733 GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
33734 GIM_CheckType, /*MI*/0, /*Op*/9, /*Type*/GILLT_s32,
33735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
33736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
33737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
33738 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33739 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33740 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_shr_imm16,
33741 // MIs[1] Operand 1
33742 // No operand predicates
33743 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
33744 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
33745 GIM_CheckConstantInt, /*MI*/0, /*Op*/7, 1,
33746 GIM_CheckConstantInt, /*MI*/0, /*Op*/8, 0,
33747 GIM_CheckConstantInt, /*MI*/0, /*Op*/9, 1,
33748 GIM_CheckIsSafeToFold, /*InsnID*/1,
33749 // (intrinsic_wo_chain:{ *:[v8i16] } 2104:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33750 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQRSHRUNs32th,
33751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
33752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // QdSrc
33753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Qm
33754 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33755 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
33756 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33757 GIR_EraseFromParent, /*InsnID*/0,
33758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33759 // GIR_Coverage, 3802,
33760 GIR_Done,
33761 // Label 1628: @91092
33762 GIM_Reject,
33763 // Label 1588: @91093
33764 GIM_Reject,
33765 // Label 13: @91094
33766 GIM_Try, /*On fail goto*//*Label 1629*/ 91143,
33767 GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
33768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_clrex,
33769 GIM_Try, /*On fail goto*//*Label 1630*/ 91119, // Rule ID 252 //
33770 GIM_CheckFeatures, GIFBS_HasV6K_IsARM,
33771 // (intrinsic_void 1889:{ *:[iPTR] }) => (CLREX)
33772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLREX,
33773 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
33774 GIR_EraseFromParent, /*InsnID*/0,
33775 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33776 // GIR_Coverage, 252,
33777 GIR_Done,
33778 // Label 1630: @91119
33779 GIM_Try, /*On fail goto*//*Label 1631*/ 91142, // Rule ID 590 //
33780 GIM_CheckFeatures, GIFBS_HasV7Clrex_IsThumb,
33781 // (intrinsic_void 1889:{ *:[iPTR] }) => (t2CLREX)
33782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLREX,
33783 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33784 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33785 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
33786 GIR_EraseFromParent, /*InsnID*/0,
33787 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33788 // GIR_Coverage, 590,
33789 GIR_Done,
33790 // Label 1631: @91142
33791 GIM_Reject,
33792 // Label 1629: @91143
33793 GIM_Try, /*On fail goto*//*Label 1632*/ 91871,
33794 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
33795 GIM_Try, /*On fail goto*//*Label 1633*/ 91176, // Rule ID 351 //
33796 GIM_CheckFeatures, GIFBS_IsThumb_IsWindows,
33797 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
33798 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33799 GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 249,
33800 // (intrinsic_void 2328:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0)
33801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t__brkdiv0,
33802 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
33803 GIR_EraseFromParent, /*InsnID*/0,
33804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33805 // GIR_Coverage, 351,
33806 GIR_Done,
33807 // Label 1633: @91176
33808 GIM_Try, /*On fail goto*//*Label 1634*/ 91223, // Rule ID 2 //
33809 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
33810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
33811 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33812 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33813 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33814 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
33815 // MIs[1] Operand 1
33816 // No operand predicates
33817 GIM_CheckIsSafeToFold, /*InsnID*/1,
33818 // (intrinsic_void 1907:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm)
33819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::HINT,
33820 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33821 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33822 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33823 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33824 GIR_EraseFromParent, /*InsnID*/0,
33825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33826 // GIR_Coverage, 2,
33827 GIR_Done,
33828 // Label 1634: @91223
33829 GIM_Try, /*On fail goto*//*Label 1635*/ 91270, // Rule ID 10 //
33830 GIM_CheckFeatures, GIFBS_HasV7_IsARM,
33831 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
33832 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33833 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33834 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33835 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
33836 // MIs[1] Operand 1
33837 // No operand predicates
33838 GIM_CheckIsSafeToFold, /*InsnID*/1,
33839 // (intrinsic_void 1902:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt)
33840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DBG,
33841 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33842 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33843 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33844 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33845 GIR_EraseFromParent, /*InsnID*/0,
33846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33847 // GIR_Coverage, 10,
33848 GIR_Done,
33849 // Label 1635: @91270
33850 GIM_Try, /*On fail goto*//*Label 1636*/ 91310, // Rule ID 11 //
33851 GIM_CheckFeatures, GIFBS_IsARM,
33852 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
33853 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33854 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33855 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33856 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
33857 // MIs[1] Operand 1
33858 // No operand predicates
33859 GIM_CheckIsSafeToFold, /*InsnID*/1,
33860 // (intrinsic_void 2328:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16)
33861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDF,
33862 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
33863 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33864 GIR_EraseFromParent, /*InsnID*/0,
33865 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33866 // GIR_Coverage, 11,
33867 GIR_Done,
33868 // Label 1636: @91310
33869 GIM_Try, /*On fail goto*//*Label 1637*/ 91350, // Rule ID 235 //
33870 GIM_CheckFeatures, GIFBS_HasDB_IsARM,
33871 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
33872 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33873 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33874 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33875 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
33876 // MIs[1] Operand 1
33877 // No operand predicates
33878 GIM_CheckIsSafeToFold, /*InsnID*/1,
33879 // (intrinsic_void 1903:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt)
33880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DMB,
33881 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33882 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33883 GIR_EraseFromParent, /*InsnID*/0,
33884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33885 // GIR_Coverage, 235,
33886 GIR_Done,
33887 // Label 1637: @91350
33888 GIM_Try, /*On fail goto*//*Label 1638*/ 91390, // Rule ID 236 //
33889 GIM_CheckFeatures, GIFBS_HasDB_IsARM,
33890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
33891 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33892 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33893 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33894 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
33895 // MIs[1] Operand 1
33896 // No operand predicates
33897 GIM_CheckIsSafeToFold, /*InsnID*/1,
33898 // (intrinsic_void 1904:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt)
33899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DSB,
33900 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33901 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33902 GIR_EraseFromParent, /*InsnID*/0,
33903 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33904 // GIR_Coverage, 236,
33905 GIR_Done,
33906 // Label 1638: @91390
33907 GIM_Try, /*On fail goto*//*Label 1639*/ 91430, // Rule ID 237 //
33908 GIM_CheckFeatures, GIFBS_HasDB_IsARM,
33909 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
33910 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33912 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33913 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
33914 // MIs[1] Operand 1
33915 // No operand predicates
33916 GIM_CheckIsSafeToFold, /*InsnID*/1,
33917 // (intrinsic_void 1908:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt)
33918 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ISB,
33919 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33920 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33921 GIR_EraseFromParent, /*InsnID*/0,
33922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33923 // GIR_Coverage, 237,
33924 GIR_Done,
33925 // Label 1639: @91430
33926 GIM_Try, /*On fail goto*//*Label 1640*/ 91477, // Rule ID 283 //
33927 GIM_CheckFeatures, GIFBS_HasV6M_IsThumb,
33928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
33929 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33931 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33932 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
33933 // MIs[1] Operand 1
33934 // No operand predicates
33935 GIM_CheckIsSafeToFold, /*InsnID*/1,
33936 // (intrinsic_void 1907:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm)
33937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tHINT,
33938 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33939 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33940 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
33941 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33942 GIR_EraseFromParent, /*InsnID*/0,
33943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33944 // GIR_Coverage, 283,
33945 GIR_Done,
33946 // Label 1640: @91477
33947 GIM_Try, /*On fail goto*//*Label 1641*/ 91517, // Rule ID 350 //
33948 GIM_CheckFeatures, GIFBS_IsThumb,
33949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
33950 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33951 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33952 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33953 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_255,
33954 // MIs[1] Operand 1
33955 // No operand predicates
33956 GIM_CheckIsSafeToFold, /*InsnID*/1,
33957 // (intrinsic_void 2328:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8)
33958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUDF,
33959 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
33960 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33961 GIR_EraseFromParent, /*InsnID*/0,
33962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33963 // GIR_Coverage, 350,
33964 GIR_Done,
33965 // Label 1641: @91517
33966 GIM_Try, /*On fail goto*//*Label 1642*/ 91557, // Rule ID 501 //
33967 GIM_CheckFeatures, GIFBS_IsThumb2,
33968 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
33969 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33970 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33971 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33972 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
33973 // MIs[1] Operand 1
33974 // No operand predicates
33975 GIM_CheckIsSafeToFold, /*InsnID*/1,
33976 // (intrinsic_void 2328:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16)
33977 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDF,
33978 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
33979 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
33980 GIR_EraseFromParent, /*InsnID*/0,
33981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
33982 // GIR_Coverage, 501,
33983 GIR_Done,
33984 // Label 1642: @91557
33985 GIM_Try, /*On fail goto*//*Label 1643*/ 91604, // Rule ID 575 //
33986 GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
33987 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
33988 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
33989 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33990 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
33991 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
33992 // MIs[1] Operand 1
33993 // No operand predicates
33994 GIM_CheckIsSafeToFold, /*InsnID*/1,
33995 // (intrinsic_void 1903:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt)
33996 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DMB,
33997 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33998 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
33999 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34000 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34001 GIR_EraseFromParent, /*InsnID*/0,
34002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34003 // GIR_Coverage, 575,
34004 GIR_Done,
34005 // Label 1643: @91604
34006 GIM_Try, /*On fail goto*//*Label 1644*/ 91651, // Rule ID 576 //
34007 GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
34008 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
34009 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34011 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34012 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
34013 // MIs[1] Operand 1
34014 // No operand predicates
34015 GIM_CheckIsSafeToFold, /*InsnID*/1,
34016 // (intrinsic_void 1904:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt)
34017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DSB,
34018 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
34019 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34020 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34021 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34022 GIR_EraseFromParent, /*InsnID*/0,
34023 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34024 // GIR_Coverage, 576,
34025 GIR_Done,
34026 // Label 1644: @91651
34027 GIM_Try, /*On fail goto*//*Label 1645*/ 91698, // Rule ID 577 //
34028 GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
34029 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
34030 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34031 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34032 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34033 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
34034 // MIs[1] Operand 1
34035 // No operand predicates
34036 GIM_CheckIsSafeToFold, /*InsnID*/1,
34037 // (intrinsic_void 1908:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt)
34038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ISB,
34039 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
34040 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34041 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34042 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34043 GIR_EraseFromParent, /*InsnID*/0,
34044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34045 // GIR_Coverage, 577,
34046 GIR_Done,
34047 // Label 1645: @91698
34048 GIM_Try, /*On fail goto*//*Label 1646*/ 91745, // Rule ID 595 //
34049 GIM_CheckFeatures, GIFBS_IsThumb2,
34050 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
34051 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34052 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34053 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34054 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
34055 // MIs[1] Operand 1
34056 // No operand predicates
34057 GIM_CheckIsSafeToFold, /*InsnID*/1,
34058 // (intrinsic_void 1907:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm)
34059 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2HINT,
34060 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34061 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34062 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34063 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34064 GIR_EraseFromParent, /*InsnID*/0,
34065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34066 // GIR_Coverage, 595,
34067 GIR_Done,
34068 // Label 1646: @91745
34069 GIM_Try, /*On fail goto*//*Label 1647*/ 91792, // Rule ID 596 //
34070 GIM_CheckFeatures, GIFBS_IsThumb2,
34071 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
34072 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34073 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
34074 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34075 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
34076 // MIs[1] Operand 1
34077 // No operand predicates
34078 GIM_CheckIsSafeToFold, /*InsnID*/1,
34079 // (intrinsic_void 1902:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt)
34080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DBG,
34081 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
34082 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34083 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34084 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34085 GIR_EraseFromParent, /*InsnID*/0,
34086 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34087 // GIR_Coverage, 596,
34088 GIR_Done,
34089 // Label 1647: @91792
34090 GIM_Try, /*On fail goto*//*Label 1648*/ 91831, // Rule ID 739 //
34091 GIM_CheckFeatures, GIFBS_HasFPRegs,
34092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_get_fpscr,
34093 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34095 // (intrinsic_w_chain:{ *:[i32] } 1905:{ *:[iPTR] }) => (VMRS:{ *:[i32] })
34096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS,
34097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
34098 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34099 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34100 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34101 GIR_EraseFromParent, /*InsnID*/0,
34102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34103 // GIR_Coverage, 739,
34104 GIR_Done,
34105 // Label 1648: @91831
34106 GIM_Try, /*On fail goto*//*Label 1649*/ 91870, // Rule ID 740 //
34107 GIM_CheckFeatures, GIFBS_HasFPRegs,
34108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_set_fpscr,
34109 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
34110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
34111 // (intrinsic_void 2272:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR GPRnopc:{ *:[i32] }:$Rt)
34112 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMSR,
34113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
34114 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34115 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34116 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34117 GIR_EraseFromParent, /*InsnID*/0,
34118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34119 // GIR_Coverage, 740,
34120 GIR_Done,
34121 // Label 1649: @91870
34122 GIM_Reject,
34123 // Label 1632: @91871
34124 GIM_Try, /*On fail goto*//*Label 1650*/ 91918, // Rule ID 619 //
34125 GIM_CheckFeatures, GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
34126 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
34127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::start_loop_iterations,
34128 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34129 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRlrRegClassID,
34131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34132 // (intrinsic_w_chain:{ *:[i32] } 261:{ *:[iPTR] }, rGPR:{ *:[i32] }:$elts) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$elts)
34133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DoLoopStart,
34134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // X
34135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // elts
34136 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34137 GIR_EraseFromParent, /*InsnID*/0,
34138 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34139 // GIR_Coverage, 619,
34140 GIR_Done,
34141 // Label 1650: @91918
34142 GIM_Try, /*On fail goto*//*Label 1651*/ 94083,
34143 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
34144 GIM_Try, /*On fail goto*//*Label 1652*/ 91982, // Rule ID 4931 //
34145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
34146 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
34147 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
34148 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34151 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34152 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34153 // MIs[1] Operand 1
34154 // No operand predicates
34155 GIM_CheckIsSafeToFold, /*InsnID*/1,
34156 // (intrinsic_w_chain:{ *:[v4i32] } 2038:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
34157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi,
34158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34160 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34161 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34162 GIR_EraseFromParent, /*InsnID*/0,
34163 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34164 // GIR_Coverage, 4931,
34165 GIR_Done,
34166 // Label 1652: @91982
34167 GIM_Try, /*On fail goto*//*Label 1653*/ 92041, // Rule ID 4937 //
34168 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
34169 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
34170 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
34171 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34174 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34175 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34176 // MIs[1] Operand 1
34177 // No operand predicates
34178 GIM_CheckIsSafeToFold, /*InsnID*/1,
34179 // (intrinsic_w_chain:{ *:[v4f32] } 2038:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
34180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_qi,
34181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34183 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34184 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34185 GIR_EraseFromParent, /*InsnID*/0,
34186 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34187 // GIR_Coverage, 4937,
34188 GIR_Done,
34189 // Label 1653: @92041
34190 GIM_Try, /*On fail goto*//*Label 1654*/ 92100, // Rule ID 4939 //
34191 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
34192 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
34193 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
34194 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34197 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34198 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34199 // MIs[1] Operand 1
34200 // No operand predicates
34201 GIM_CheckIsSafeToFold, /*InsnID*/1,
34202 // (intrinsic_w_chain:{ *:[v2i64] } 2038:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
34203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi,
34204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34206 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34207 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34208 GIR_EraseFromParent, /*InsnID*/0,
34209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34210 // GIR_Coverage, 4939,
34211 GIR_Done,
34212 // Label 1654: @92100
34213 GIM_Try, /*On fail goto*//*Label 1655*/ 92159, // Rule ID 4941 //
34214 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_base,
34215 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
34216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
34217 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34220 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34221 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34222 // MIs[1] Operand 1
34223 // No operand predicates
34224 GIM_CheckIsSafeToFold, /*InsnID*/1,
34225 // (intrinsic_w_chain:{ *:[v2f64] } 2038:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
34226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_qi,
34227 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
34228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34229 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34230 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34231 GIR_EraseFromParent, /*InsnID*/0,
34232 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34233 // GIR_Coverage, 4941,
34234 GIR_Done,
34235 // Label 1655: @92159
34236 GIM_Try, /*On fail goto*//*Label 1656*/ 92208, // Rule ID 1757 //
34237 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_space,
34238 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34239 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
34241 // MIs[0] size
34242 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
34244 // (intrinsic_w_chain:{ *:[i32] } 2303:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
34245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SPACE,
34246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // size
34248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
34249 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34250 GIR_EraseFromParent, /*InsnID*/0,
34251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34252 // GIR_Coverage, 1757,
34253 GIR_Done,
34254 // Label 1656: @92208
34255 GIM_Try, /*On fail goto*//*Label 1657*/ 92267, // Rule ID 4933 //
34256 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
34257 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
34258 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34259 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
34261 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34262 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34263 // MIs[1] Operand 1
34264 // No operand predicates
34265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34266 GIM_CheckIsSafeToFold, /*InsnID*/1,
34267 // (intrinsic_void 2112:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
34268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi,
34269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
34270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
34271 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34272 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34273 GIR_EraseFromParent, /*InsnID*/0,
34274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34275 // GIR_Coverage, 4933,
34276 GIR_Done,
34277 // Label 1657: @92267
34278 GIM_Try, /*On fail goto*//*Label 1658*/ 92326, // Rule ID 4943 //
34279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
34280 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
34281 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34282 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
34283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
34284 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34285 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34286 // MIs[1] Operand 1
34287 // No operand predicates
34288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34289 GIM_CheckIsSafeToFold, /*InsnID*/1,
34290 // (intrinsic_void 2112:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
34291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi,
34292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
34293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
34294 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34295 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34296 GIR_EraseFromParent, /*InsnID*/0,
34297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34298 // GIR_Coverage, 4943,
34299 GIR_Done,
34300 // Label 1658: @92326
34301 GIM_Try, /*On fail goto*//*Label 1659*/ 92385, // Rule ID 4947 //
34302 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
34303 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
34304 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34305 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
34306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
34307 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34308 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34309 // MIs[1] Operand 1
34310 // No operand predicates
34311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34312 GIM_CheckIsSafeToFold, /*InsnID*/1,
34313 // (intrinsic_void 2112:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
34314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi,
34315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
34316 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
34317 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34318 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34319 GIR_EraseFromParent, /*InsnID*/0,
34320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34321 // GIR_Coverage, 4947,
34322 GIR_Done,
34323 // Label 1659: @92385
34324 GIM_Try, /*On fail goto*//*Label 1660*/ 92444, // Rule ID 4951 //
34325 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_base,
34326 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
34327 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34328 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
34329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
34330 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
34331 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34332 // MIs[1] Operand 1
34333 // No operand predicates
34334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
34335 GIM_CheckIsSafeToFold, /*InsnID*/1,
34336 // (intrinsic_void 2112:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
34337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi,
34338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
34339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
34340 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34341 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34342 GIR_EraseFromParent, /*InsnID*/0,
34343 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34344 // GIR_Coverage, 4951,
34345 GIR_Done,
34346 // Label 1660: @92444
34347 GIM_Try, /*On fail goto*//*Label 1661*/ 92507, // Rule ID 3 //
34348 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
34349 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
34350 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34351 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34352 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
34354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
34355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
34356 // (intrinsic_w_chain:{ *:[i32] } 2271:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
34357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SEL,
34358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34361 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34362 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34363 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34364 GIR_EraseFromParent, /*InsnID*/0,
34365 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34366 // GIR_Coverage, 3,
34367 GIR_Done,
34368 // Label 1661: @92507
34369 GIM_Try, /*On fail goto*//*Label 1662*/ 92570, // Rule ID 121 //
34370 GIM_CheckFeatures, GIFBS_IsARM,
34371 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
34372 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34373 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34374 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34378 // (intrinsic_w_chain:{ *:[i32] } 2270:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SASX,
34380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34383 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34384 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34385 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34386 GIR_EraseFromParent, /*InsnID*/0,
34387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34388 // GIR_Coverage, 121,
34389 GIR_Done,
34390 // Label 1662: @92570
34391 GIM_Try, /*On fail goto*//*Label 1663*/ 92633, // Rule ID 122 //
34392 GIM_CheckFeatures, GIFBS_IsARM,
34393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
34394 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34396 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34400 // (intrinsic_w_chain:{ *:[i32] } 2268:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34401 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD16,
34402 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34405 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34406 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34407 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34408 GIR_EraseFromParent, /*InsnID*/0,
34409 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34410 // GIR_Coverage, 122,
34411 GIR_Done,
34412 // Label 1663: @92633
34413 GIM_Try, /*On fail goto*//*Label 1664*/ 92696, // Rule ID 123 //
34414 GIM_CheckFeatures, GIFBS_IsARM,
34415 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
34416 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34417 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34418 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34422 // (intrinsic_w_chain:{ *:[i32] } 2269:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34423 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD8,
34424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34427 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34428 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34429 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34430 GIR_EraseFromParent, /*InsnID*/0,
34431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34432 // GIR_Coverage, 123,
34433 GIR_Done,
34434 // Label 1664: @92696
34435 GIM_Try, /*On fail goto*//*Label 1665*/ 92759, // Rule ID 124 //
34436 GIM_CheckFeatures, GIFBS_IsARM,
34437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
34438 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34439 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34440 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34444 // (intrinsic_w_chain:{ *:[i32] } 2306:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSAX,
34446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34449 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34450 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34451 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34452 GIR_EraseFromParent, /*InsnID*/0,
34453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34454 // GIR_Coverage, 124,
34455 GIR_Done,
34456 // Label 1665: @92759
34457 GIM_Try, /*On fail goto*//*Label 1666*/ 92822, // Rule ID 125 //
34458 GIM_CheckFeatures, GIFBS_IsARM,
34459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
34460 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34461 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34462 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34466 // (intrinsic_w_chain:{ *:[i32] } 2307:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB16,
34468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34471 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34472 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34473 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34474 GIR_EraseFromParent, /*InsnID*/0,
34475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34476 // GIR_Coverage, 125,
34477 GIR_Done,
34478 // Label 1666: @92822
34479 GIM_Try, /*On fail goto*//*Label 1667*/ 92885, // Rule ID 126 //
34480 GIM_CheckFeatures, GIFBS_IsARM,
34481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
34482 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34483 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34484 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34488 // (intrinsic_w_chain:{ *:[i32] } 2308:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB8,
34490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34493 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34494 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34495 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34496 GIR_EraseFromParent, /*InsnID*/0,
34497 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34498 // GIR_Coverage, 126,
34499 GIR_Done,
34500 // Label 1667: @92885
34501 GIM_Try, /*On fail goto*//*Label 1668*/ 92948, // Rule ID 127 //
34502 GIM_CheckFeatures, GIFBS_IsARM,
34503 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
34504 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34505 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34506 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34510 // (intrinsic_w_chain:{ *:[i32] } 2321:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UASX,
34512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34515 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34516 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34517 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34518 GIR_EraseFromParent, /*InsnID*/0,
34519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34520 // GIR_Coverage, 127,
34521 GIR_Done,
34522 // Label 1668: @92948
34523 GIM_Try, /*On fail goto*//*Label 1669*/ 93011, // Rule ID 128 //
34524 GIM_CheckFeatures, GIFBS_IsARM,
34525 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
34526 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34527 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34528 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34532 // (intrinsic_w_chain:{ *:[i32] } 2319:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD16,
34534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34537 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34538 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34539 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34540 GIR_EraseFromParent, /*InsnID*/0,
34541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34542 // GIR_Coverage, 128,
34543 GIR_Done,
34544 // Label 1669: @93011
34545 GIM_Try, /*On fail goto*//*Label 1670*/ 93074, // Rule ID 129 //
34546 GIM_CheckFeatures, GIFBS_IsARM,
34547 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
34548 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34549 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34550 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34554 // (intrinsic_w_chain:{ *:[i32] } 2320:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34555 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD8,
34556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34559 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34560 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34561 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34562 GIR_EraseFromParent, /*InsnID*/0,
34563 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34564 // GIR_Coverage, 129,
34565 GIR_Done,
34566 // Label 1670: @93074
34567 GIM_Try, /*On fail goto*//*Label 1671*/ 93137, // Rule ID 130 //
34568 GIM_CheckFeatures, GIFBS_IsARM,
34569 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
34570 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34571 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34572 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34576 // (intrinsic_w_chain:{ *:[i32] } 2339:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAX,
34578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34581 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34582 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34583 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34584 GIR_EraseFromParent, /*InsnID*/0,
34585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34586 // GIR_Coverage, 130,
34587 GIR_Done,
34588 // Label 1671: @93137
34589 GIM_Try, /*On fail goto*//*Label 1672*/ 93200, // Rule ID 131 //
34590 GIM_CheckFeatures, GIFBS_IsARM,
34591 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
34592 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34593 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34594 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34598 // (intrinsic_w_chain:{ *:[i32] } 2340:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB16,
34600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34603 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34604 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34605 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34606 GIR_EraseFromParent, /*InsnID*/0,
34607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34608 // GIR_Coverage, 131,
34609 GIR_Done,
34610 // Label 1672: @93200
34611 GIM_Try, /*On fail goto*//*Label 1673*/ 93263, // Rule ID 132 //
34612 GIM_CheckFeatures, GIFBS_IsARM,
34613 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
34614 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34615 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34616 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
34618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
34619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
34620 // (intrinsic_w_chain:{ *:[i32] } 2341:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
34621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB8,
34622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34625 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34626 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34627 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34628 GIR_EraseFromParent, /*InsnID*/0,
34629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34630 // GIR_Coverage, 132,
34631 GIR_Done,
34632 // Label 1673: @93263
34633 GIM_Try, /*On fail goto*//*Label 1674*/ 93326, // Rule ID 438 //
34634 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
34636 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34637 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34638 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
34640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
34641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
34642 // (intrinsic_w_chain:{ *:[i32] } 2271:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
34643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SEL,
34644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34647 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34648 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34649 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34650 GIR_EraseFromParent, /*InsnID*/0,
34651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34652 // GIR_Coverage, 438,
34653 GIR_Done,
34654 // Label 1674: @93326
34655 GIM_Try, /*On fail goto*//*Label 1675*/ 93389, // Rule ID 451 //
34656 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
34658 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34659 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34660 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34664 // (intrinsic_w_chain:{ *:[i32] } 2270:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SASX,
34666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34669 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34670 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34671 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34672 GIR_EraseFromParent, /*InsnID*/0,
34673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34674 // GIR_Coverage, 451,
34675 GIR_Done,
34676 // Label 1675: @93389
34677 GIM_Try, /*On fail goto*//*Label 1676*/ 93452, // Rule ID 452 //
34678 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34679 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
34680 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34681 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34682 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34686 // (intrinsic_w_chain:{ *:[i32] } 2268:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD16,
34688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34691 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34692 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34693 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34694 GIR_EraseFromParent, /*InsnID*/0,
34695 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34696 // GIR_Coverage, 452,
34697 GIR_Done,
34698 // Label 1676: @93452
34699 GIM_Try, /*On fail goto*//*Label 1677*/ 93515, // Rule ID 453 //
34700 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34701 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
34702 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34703 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34704 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34708 // (intrinsic_w_chain:{ *:[i32] } 2269:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34709 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD8,
34710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34713 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34714 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34715 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34716 GIR_EraseFromParent, /*InsnID*/0,
34717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34718 // GIR_Coverage, 453,
34719 GIR_Done,
34720 // Label 1677: @93515
34721 GIM_Try, /*On fail goto*//*Label 1678*/ 93578, // Rule ID 454 //
34722 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34723 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
34724 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34725 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34726 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34730 // (intrinsic_w_chain:{ *:[i32] } 2306:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34731 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSAX,
34732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34735 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34736 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34737 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34738 GIR_EraseFromParent, /*InsnID*/0,
34739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34740 // GIR_Coverage, 454,
34741 GIR_Done,
34742 // Label 1678: @93578
34743 GIM_Try, /*On fail goto*//*Label 1679*/ 93641, // Rule ID 455 //
34744 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34745 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
34746 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34747 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34748 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34752 // (intrinsic_w_chain:{ *:[i32] } 2307:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB16,
34754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34757 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34758 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34759 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34760 GIR_EraseFromParent, /*InsnID*/0,
34761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34762 // GIR_Coverage, 455,
34763 GIR_Done,
34764 // Label 1679: @93641
34765 GIM_Try, /*On fail goto*//*Label 1680*/ 93704, // Rule ID 456 //
34766 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34767 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
34768 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34769 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34770 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34774 // (intrinsic_w_chain:{ *:[i32] } 2308:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB8,
34776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34779 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34780 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34781 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34782 GIR_EraseFromParent, /*InsnID*/0,
34783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34784 // GIR_Coverage, 456,
34785 GIR_Done,
34786 // Label 1680: @93704
34787 GIM_Try, /*On fail goto*//*Label 1681*/ 93767, // Rule ID 457 //
34788 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34789 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
34790 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34791 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34792 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34796 // (intrinsic_w_chain:{ *:[i32] } 2321:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UASX,
34798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34801 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34802 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34803 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34804 GIR_EraseFromParent, /*InsnID*/0,
34805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34806 // GIR_Coverage, 457,
34807 GIR_Done,
34808 // Label 1681: @93767
34809 GIM_Try, /*On fail goto*//*Label 1682*/ 93830, // Rule ID 458 //
34810 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34811 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
34812 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34813 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34814 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34818 // (intrinsic_w_chain:{ *:[i32] } 2319:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34819 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD16,
34820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34822 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34823 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34824 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34825 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34826 GIR_EraseFromParent, /*InsnID*/0,
34827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34828 // GIR_Coverage, 458,
34829 GIR_Done,
34830 // Label 1682: @93830
34831 GIM_Try, /*On fail goto*//*Label 1683*/ 93893, // Rule ID 459 //
34832 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34833 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
34834 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34835 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34836 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34840 // (intrinsic_w_chain:{ *:[i32] } 2320:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD8,
34842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34845 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34846 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34847 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34848 GIR_EraseFromParent, /*InsnID*/0,
34849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34850 // GIR_Coverage, 459,
34851 GIR_Done,
34852 // Label 1683: @93893
34853 GIM_Try, /*On fail goto*//*Label 1684*/ 93956, // Rule ID 460 //
34854 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34855 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
34856 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34857 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34858 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34862 // (intrinsic_w_chain:{ *:[i32] } 2339:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34863 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAX,
34864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34867 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34868 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34869 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34870 GIR_EraseFromParent, /*InsnID*/0,
34871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34872 // GIR_Coverage, 460,
34873 GIR_Done,
34874 // Label 1684: @93956
34875 GIM_Try, /*On fail goto*//*Label 1685*/ 94019, // Rule ID 461 //
34876 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34877 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
34878 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34879 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34880 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34884 // (intrinsic_w_chain:{ *:[i32] } 2340:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB16,
34886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34889 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34890 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34891 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34892 GIR_EraseFromParent, /*InsnID*/0,
34893 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34894 // GIR_Coverage, 461,
34895 GIR_Done,
34896 // Label 1685: @94019
34897 GIM_Try, /*On fail goto*//*Label 1686*/ 94082, // Rule ID 462 //
34898 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
34899 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
34900 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
34901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
34902 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
34904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
34905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
34906 // (intrinsic_w_chain:{ *:[i32] } 2341:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
34907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB8,
34908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
34909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
34910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
34911 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
34912 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
34913 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
34914 GIR_EraseFromParent, /*InsnID*/0,
34915 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34916 // GIR_Coverage, 462,
34917 GIR_Done,
34918 // Label 1686: @94082
34919 GIM_Reject,
34920 // Label 1651: @94083
34921 GIM_Try, /*On fail goto*//*Label 1687*/ 94361,
34922 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
34923 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vstr_scatter_base_wb,
34924 GIM_Try, /*On fail goto*//*Label 1688*/ 94159, // Rule ID 4935 //
34925 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
34926 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
34927 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34928 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
34929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34932 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34933 // MIs[1] Operand 1
34934 // No operand predicates
34935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
34936 GIM_CheckIsSafeToFold, /*InsnID*/1,
34937 // (intrinsic_w_chain:{ *:[v4i32] } 2114:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
34938 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre,
34939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
34940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
34941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34942 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34943 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34944 GIR_EraseFromParent, /*InsnID*/0,
34945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34946 // GIR_Coverage, 4935,
34947 GIR_Done,
34948 // Label 1688: @94159
34949 GIM_Try, /*On fail goto*//*Label 1689*/ 94226, // Rule ID 4945 //
34950 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
34951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
34952 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34953 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
34954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34956 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34957 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34958 // MIs[1] Operand 1
34959 // No operand predicates
34960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
34961 GIM_CheckIsSafeToFold, /*InsnID*/1,
34962 // (intrinsic_w_chain:{ *:[v4i32] } 2114:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
34963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_qi_pre,
34964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
34965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
34966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34967 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34968 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34969 GIR_EraseFromParent, /*InsnID*/0,
34970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34971 // GIR_Coverage, 4945,
34972 GIR_Done,
34973 // Label 1689: @94226
34974 GIM_Try, /*On fail goto*//*Label 1690*/ 94293, // Rule ID 4949 //
34975 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
34976 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
34977 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
34978 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
34979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
34980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
34981 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
34982 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
34983 // MIs[1] Operand 1
34984 // No operand predicates
34985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
34986 GIM_CheckIsSafeToFold, /*InsnID*/1,
34987 // (intrinsic_w_chain:{ *:[v2i64] } 2114:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
34988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre,
34989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
34990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
34991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
34992 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
34993 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
34994 GIR_EraseFromParent, /*InsnID*/0,
34995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
34996 // GIR_Coverage, 4949,
34997 GIR_Done,
34998 // Label 1690: @94293
34999 GIM_Try, /*On fail goto*//*Label 1691*/ 94360, // Rule ID 4953 //
35000 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
35001 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35002 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35003 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
35004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35006 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35007 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
35008 // MIs[1] Operand 1
35009 // No operand predicates
35010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::MQPRRegClassID,
35011 GIM_CheckIsSafeToFold, /*InsnID*/1,
35012 // (intrinsic_w_chain:{ *:[v2i64] } 2114:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_qi_pre,
35014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wb
35015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // data
35016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
35017 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35018 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
35019 GIR_EraseFromParent, /*InsnID*/0,
35020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35021 // GIR_Coverage, 4953,
35022 GIR_Done,
35023 // Label 1691: @94360
35024 GIM_Reject,
35025 // Label 1687: @94361
35026 GIM_Try, /*On fail goto*//*Label 1692*/ 95698,
35027 GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
35028 GIM_Try, /*On fail goto*//*Label 1693*/ 94436, // Rule ID 4823 //
35029 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35030 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
35031 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35032 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35033 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35034 // MIs[0] base
35035 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35039 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35040 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35041 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u,
35043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35046 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35047 GIR_EraseFromParent, /*InsnID*/0,
35048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35049 // GIR_Coverage, 4823,
35050 GIR_Done,
35051 // Label 1693: @94436
35052 GIM_Try, /*On fail goto*//*Label 1694*/ 94506, // Rule ID 4824 //
35053 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
35055 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35056 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35057 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35058 // MIs[0] base
35059 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35063 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35064 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35065 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq,
35067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35070 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35071 GIR_EraseFromParent, /*InsnID*/0,
35072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35073 // GIR_Coverage, 4824,
35074 GIR_Done,
35075 // Label 1694: @94506
35076 GIM_Try, /*On fail goto*//*Label 1695*/ 94576, // Rule ID 4827 //
35077 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35078 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
35079 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
35080 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35081 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35082 // MIs[0] base
35083 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35087 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35088 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35089 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
35090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB8_rq,
35091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35094 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35095 GIR_EraseFromParent, /*InsnID*/0,
35096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35097 // GIR_Coverage, 4827,
35098 GIR_Done,
35099 // Label 1695: @94576
35100 GIM_Try, /*On fail goto*//*Label 1696*/ 94646, // Rule ID 4907 //
35101 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35102 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
35103 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35104 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35105 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35106 // MIs[0] base
35107 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35111 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35112 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35113 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB16_rq,
35115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35118 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35119 GIR_EraseFromParent, /*InsnID*/0,
35120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35121 // GIR_Coverage, 4907,
35122 GIR_Done,
35123 // Label 1696: @94646
35124 GIM_Try, /*On fail goto*//*Label 1697*/ 94716, // Rule ID 4909 //
35125 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35126 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35127 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35128 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35129 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35130 // MIs[0] base
35131 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35135 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35136 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35137 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRB32_rq,
35139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35142 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35143 GIR_EraseFromParent, /*InsnID*/0,
35144 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35145 // GIR_Coverage, 4909,
35146 GIR_Done,
35147 // Label 1697: @94716
35148 GIM_Try, /*On fail goto*//*Label 1698*/ 94786, // Rule ID 4911 //
35149 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35150 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
35151 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35152 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35153 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35154 // MIs[0] base
35155 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35159 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35160 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35161 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq_u,
35163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35166 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35167 GIR_EraseFromParent, /*InsnID*/0,
35168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35169 // GIR_Coverage, 4911,
35170 GIR_Done,
35171 // Label 1698: @94786
35172 GIM_Try, /*On fail goto*//*Label 1699*/ 94856, // Rule ID 4912 //
35173 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35174 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
35175 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35176 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35177 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35178 // MIs[0] base
35179 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35183 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35184 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35185 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH16_rq,
35187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35190 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35191 GIR_EraseFromParent, /*InsnID*/0,
35192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35193 // GIR_Coverage, 4912,
35194 GIR_Done,
35195 // Label 1699: @94856
35196 GIM_Try, /*On fail goto*//*Label 1700*/ 94926, // Rule ID 4915 //
35197 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35198 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35199 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35200 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35201 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35202 // MIs[0] base
35203 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35207 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35208 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35209 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq_u,
35211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35214 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35215 GIR_EraseFromParent, /*InsnID*/0,
35216 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35217 // GIR_Coverage, 4915,
35218 GIR_Done,
35219 // Label 1700: @94926
35220 GIM_Try, /*On fail goto*//*Label 1701*/ 94996, // Rule ID 4916 //
35221 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35223 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35224 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35225 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35226 // MIs[0] base
35227 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35231 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35232 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35233 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRH32_rq,
35235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35238 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35239 GIR_EraseFromParent, /*InsnID*/0,
35240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35241 // GIR_Coverage, 4916,
35242 GIR_Done,
35243 // Label 1701: @94996
35244 GIM_Try, /*On fail goto*//*Label 1702*/ 95066, // Rule ID 4919 //
35245 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35246 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35247 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35248 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35249 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35250 // MIs[0] base
35251 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35255 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
35256 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35257 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u,
35259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35260 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35262 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35263 GIR_EraseFromParent, /*InsnID*/0,
35264 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35265 // GIR_Coverage, 4919,
35266 GIR_Done,
35267 // Label 1702: @95066
35268 GIM_Try, /*On fail goto*//*Label 1703*/ 95136, // Rule ID 4920 //
35269 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35270 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35271 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35272 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35273 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35274 // MIs[0] base
35275 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35279 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
35280 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
35281 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq,
35283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35286 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35287 GIR_EraseFromParent, /*InsnID*/0,
35288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35289 // GIR_Coverage, 4920,
35290 GIR_Done,
35291 // Label 1703: @95136
35292 GIM_Try, /*On fail goto*//*Label 1704*/ 95206, // Rule ID 4923 //
35293 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35294 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35295 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35296 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35297 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35298 // MIs[0] base
35299 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35303 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
35304 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35305 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq_u,
35307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35310 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35311 GIR_EraseFromParent, /*InsnID*/0,
35312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35313 // GIR_Coverage, 4923,
35314 GIR_Done,
35315 // Label 1704: @95206
35316 GIM_Try, /*On fail goto*//*Label 1705*/ 95276, // Rule ID 4924 //
35317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35318 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
35319 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35320 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35321 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35322 // MIs[0] base
35323 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35327 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
35328 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
35329 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35330 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRW32_rq,
35331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35334 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35335 GIR_EraseFromParent, /*InsnID*/0,
35336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35337 // GIR_Coverage, 4924,
35338 GIR_Done,
35339 // Label 1705: @95276
35340 GIM_Try, /*On fail goto*//*Label 1706*/ 95346, // Rule ID 4927 //
35341 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35342 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35343 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
35344 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35345 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35346 // MIs[0] base
35347 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35351 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
35352 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35353 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq_u,
35355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35358 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35359 GIR_EraseFromParent, /*InsnID*/0,
35360 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35361 // GIR_Coverage, 4927,
35362 GIR_Done,
35363 // Label 1706: @95346
35364 GIM_Try, /*On fail goto*//*Label 1707*/ 95416, // Rule ID 4928 //
35365 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mve_vstr_scatter_offset,
35366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
35367 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
35368 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35369 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35370 // MIs[0] base
35371 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
35372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
35373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
35374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35375 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
35376 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
35377 // (intrinsic_void 2116:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSTRD64_rq,
35379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
35380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // base
35381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // offsets
35382 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35383 GIR_EraseFromParent, /*InsnID*/0,
35384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35385 // GIR_Coverage, 4928,
35386 GIR_Done,
35387 // Label 1707: @95416
35388 GIM_Try, /*On fail goto*//*Label 1708*/ 95488, // Rule ID 265 //
35389 GIM_CheckFeatures, GIFBS_IsARM,
35390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
35391 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35392 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35393 // MIs[0] cop
35394 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35395 // MIs[0] opc1
35396 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
35399 // MIs[0] CRm
35400 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35401 // (intrinsic_void 1919:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
35402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR,
35403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
35406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
35407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35408 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35409 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35410 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35411 GIR_EraseFromParent, /*InsnID*/0,
35412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35413 // GIR_Coverage, 265,
35414 GIR_Done,
35415 // Label 1708: @95488
35416 GIM_Try, /*On fail goto*//*Label 1709*/ 95553, // Rule ID 266 //
35417 GIM_CheckFeatures, GIFBS_IsARM_PreV8,
35418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
35419 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35420 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35421 // MIs[0] cop
35422 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35423 // MIs[0] opc1
35424 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
35426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
35427 // MIs[0] CRm
35428 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35429 // (intrinsic_void 1920:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
35430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR2,
35431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
35434 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
35435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35436 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35437 GIR_EraseFromParent, /*InsnID*/0,
35438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35439 // GIR_Coverage, 266,
35440 GIR_Done,
35441 // Label 1709: @95553
35442 GIM_Try, /*On fail goto*//*Label 1710*/ 95625, // Rule ID 611 //
35443 GIM_CheckFeatures, GIFBS_IsThumb2,
35444 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
35445 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35446 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35447 // MIs[0] cop
35448 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35449 // MIs[0] opc1
35450 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
35452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
35453 // MIs[0] CRm
35454 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35455 // (intrinsic_void 1919:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
35456 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR,
35457 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
35460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
35461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35462 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35463 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35464 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35465 GIR_EraseFromParent, /*InsnID*/0,
35466 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35467 // GIR_Coverage, 611,
35468 GIR_Done,
35469 // Label 1710: @95625
35470 GIM_Try, /*On fail goto*//*Label 1711*/ 95697, // Rule ID 612 //
35471 GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
35472 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
35473 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
35474 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35475 // MIs[0] cop
35476 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35477 // MIs[0] opc1
35478 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
35480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
35481 // MIs[0] CRm
35482 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35483 // (intrinsic_void 1920:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
35484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR2,
35485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
35488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
35489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35490 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35491 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35492 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35493 GIR_EraseFromParent, /*InsnID*/0,
35494 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35495 // GIR_Coverage, 612,
35496 GIR_Done,
35497 // Label 1711: @95697
35498 GIM_Reject,
35499 // Label 1692: @95698
35500 GIM_Try, /*On fail goto*//*Label 1712*/ 99538,
35501 GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
35502 GIM_Try, /*On fail goto*//*Label 1713*/ 95772, // Rule ID 253 //
35503 GIM_CheckFeatures, GIFBS_IsARM_PreV8,
35504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
35505 // MIs[0] cop
35506 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35507 // MIs[0] opc1
35508 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35509 // MIs[0] CRd
35510 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
35511 // MIs[0] CRn
35512 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35513 // MIs[0] CRm
35514 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35515 // MIs[0] opc2
35516 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35517 // (intrinsic_void 1887:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35518 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP,
35519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
35522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
35523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
35525 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35526 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35527 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35528 GIR_EraseFromParent, /*InsnID*/0,
35529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35530 // GIR_Coverage, 253,
35531 GIR_Done,
35532 // Label 1713: @95772
35533 GIM_Try, /*On fail goto*//*Label 1714*/ 95834, // Rule ID 254 //
35534 GIM_CheckFeatures, GIFBS_IsARM_PreV8,
35535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
35536 // MIs[0] cop
35537 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35538 // MIs[0] opc1
35539 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35540 // MIs[0] CRd
35541 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
35542 // MIs[0] CRn
35543 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35544 // MIs[0] CRm
35545 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35546 // MIs[0] opc2
35547 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35548 // (intrinsic_void 1888:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP2,
35550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
35553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
35554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
35556 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35557 GIR_EraseFromParent, /*InsnID*/0,
35558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35559 // GIR_Coverage, 254,
35560 GIR_Done,
35561 // Label 1714: @95834
35562 GIM_Try, /*On fail goto*//*Label 1715*/ 95903, // Rule ID 613 //
35563 GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
35564 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
35565 // MIs[0] cop
35566 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35567 // MIs[0] opc1
35568 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35569 // MIs[0] CRd
35570 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
35571 // MIs[0] CRn
35572 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35573 // MIs[0] CRm
35574 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35575 // MIs[0] opc2
35576 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35577 // (intrinsic_void 1887:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP,
35579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
35582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
35583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
35585 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35586 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35587 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35588 GIR_EraseFromParent, /*InsnID*/0,
35589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35590 // GIR_Coverage, 613,
35591 GIR_Done,
35592 // Label 1715: @95903
35593 GIM_Try, /*On fail goto*//*Label 1716*/ 95972, // Rule ID 614 //
35594 GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
35595 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
35596 // MIs[0] cop
35597 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35598 // MIs[0] opc1
35599 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35600 // MIs[0] CRd
35601 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
35602 // MIs[0] CRn
35603 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35604 // MIs[0] CRm
35605 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35606 // MIs[0] opc2
35607 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35608 // (intrinsic_void 1888:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP2,
35610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
35611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
35612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // CRd
35613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
35614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
35615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
35616 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
35617 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
35618 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35619 GIR_EraseFromParent, /*InsnID*/0,
35620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35621 // GIR_Coverage, 614,
35622 GIR_Done,
35623 // Label 1716: @95972
35624 GIM_Try, /*On fail goto*//*Label 1717*/ 96050, // Rule ID 4817 //
35625 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35626 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35627 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35628 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35629 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35630 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35632 // MIs[0] base
35633 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35636 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35637 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35638 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35639 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
35641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35644 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35645 GIR_EraseFromParent, /*InsnID*/0,
35646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35647 // GIR_Coverage, 4817,
35648 GIR_Done,
35649 // Label 1717: @96050
35650 GIM_Try, /*On fail goto*//*Label 1718*/ 96128, // Rule ID 4818 //
35651 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35652 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35653 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35654 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35655 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35656 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35658 // MIs[0] base
35659 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35662 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35663 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35664 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35665 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
35667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35670 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35671 GIR_EraseFromParent, /*InsnID*/0,
35672 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35673 // GIR_Coverage, 4818,
35674 GIR_Done,
35675 // Label 1718: @96128
35676 GIM_Try, /*On fail goto*//*Label 1719*/ 96206, // Rule ID 4821 //
35677 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35678 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
35679 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
35680 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35681 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35682 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35684 // MIs[0] base
35685 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35688 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35689 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35690 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35691 // (intrinsic_w_chain:{ *:[v16i8] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
35692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq,
35693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35696 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35697 GIR_EraseFromParent, /*InsnID*/0,
35698 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35699 // GIR_Coverage, 4821,
35700 GIR_Done,
35701 // Label 1719: @96206
35702 GIM_Try, /*On fail goto*//*Label 1720*/ 96284, // Rule ID 4829 //
35703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35704 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
35705 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
35706 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35707 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35708 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35710 // MIs[0] base
35711 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35714 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35715 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35716 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35717 // (intrinsic_w_chain:{ *:[v16i8] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
35718 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU8_rq,
35719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35722 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35723 GIR_EraseFromParent, /*InsnID*/0,
35724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35725 // GIR_Coverage, 4829,
35726 GIR_Done,
35727 // Label 1720: @96284
35728 GIM_Try, /*On fail goto*//*Label 1721*/ 96362, // Rule ID 4831 //
35729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35730 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35731 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35732 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35733 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35734 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35736 // MIs[0] base
35737 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35740 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35741 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35742 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35743 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35744 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU16_rq,
35745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35748 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35749 GIR_EraseFromParent, /*InsnID*/0,
35750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35751 // GIR_Coverage, 4831,
35752 GIR_Done,
35753 // Label 1721: @96362
35754 GIM_Try, /*On fail goto*//*Label 1722*/ 96440, // Rule ID 4833 //
35755 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35756 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35757 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35758 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35759 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35760 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35762 // MIs[0] base
35763 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35766 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35767 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35768 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35769 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35770 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS16_rq,
35771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35774 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35775 GIR_EraseFromParent, /*InsnID*/0,
35776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35777 // GIR_Coverage, 4833,
35778 GIR_Done,
35779 // Label 1722: @96440
35780 GIM_Try, /*On fail goto*//*Label 1723*/ 96518, // Rule ID 4835 //
35781 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35782 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
35783 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35784 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35785 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35786 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35788 // MIs[0] base
35789 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35792 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35793 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35794 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35795 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35796 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBU32_rq,
35797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35800 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35801 GIR_EraseFromParent, /*InsnID*/0,
35802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35803 // GIR_Coverage, 4835,
35804 GIR_Done,
35805 // Label 1723: @96518
35806 GIM_Try, /*On fail goto*//*Label 1724*/ 96596, // Rule ID 4837 //
35807 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35808 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
35809 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
35810 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35811 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35812 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35814 // MIs[0] base
35815 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35818 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 8,
35819 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35820 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35821 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
35822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRBS32_rq,
35823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35826 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35827 GIR_EraseFromParent, /*InsnID*/0,
35828 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35829 // GIR_Coverage, 4837,
35830 GIR_Done,
35831 // Label 1724: @96596
35832 GIM_Try, /*On fail goto*//*Label 1725*/ 96674, // Rule ID 4839 //
35833 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35834 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35835 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35836 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35837 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35838 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35840 // MIs[0] base
35841 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35844 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35845 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35846 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35847 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35848 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
35849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35852 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35853 GIR_EraseFromParent, /*InsnID*/0,
35854 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35855 // GIR_Coverage, 4839,
35856 GIR_Done,
35857 // Label 1725: @96674
35858 GIM_Try, /*On fail goto*//*Label 1726*/ 96752, // Rule ID 4840 //
35859 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35860 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35861 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35862 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35863 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35864 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35866 // MIs[0] base
35867 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35870 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35871 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35872 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35873 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
35875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35878 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35879 GIR_EraseFromParent, /*InsnID*/0,
35880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35881 // GIR_Coverage, 4840,
35882 GIR_Done,
35883 // Label 1726: @96752
35884 GIM_Try, /*On fail goto*//*Label 1727*/ 96830, // Rule ID 4843 //
35885 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35886 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35887 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35888 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35889 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35890 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35892 // MIs[0] base
35893 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35896 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35897 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35898 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35899 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
35901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35904 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35905 GIR_EraseFromParent, /*InsnID*/0,
35906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35907 // GIR_Coverage, 4843,
35908 GIR_Done,
35909 // Label 1727: @96830
35910 GIM_Try, /*On fail goto*//*Label 1728*/ 96908, // Rule ID 4844 //
35911 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35912 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35913 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35914 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35915 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35916 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35918 // MIs[0] base
35919 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35922 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35923 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35924 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
35925 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35926 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
35927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35930 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35931 GIR_EraseFromParent, /*InsnID*/0,
35932 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35933 // GIR_Coverage, 4844,
35934 GIR_Done,
35935 // Label 1728: @96908
35936 GIM_Try, /*On fail goto*//*Label 1729*/ 96986, // Rule ID 4847 //
35937 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35938 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35939 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35940 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35941 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35942 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35944 // MIs[0] base
35945 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35948 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35949 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
35950 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35951 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
35953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35956 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35957 GIR_EraseFromParent, /*InsnID*/0,
35958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35959 // GIR_Coverage, 4847,
35960 GIR_Done,
35961 // Label 1729: @96986
35962 GIM_Try, /*On fail goto*//*Label 1730*/ 97064, // Rule ID 4848 //
35963 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35964 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35965 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35966 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35967 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35968 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35970 // MIs[0] base
35971 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
35974 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
35975 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
35976 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
35977 // (intrinsic_w_chain:{ *:[v8i16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
35978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
35979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
35980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
35981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
35982 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
35983 GIR_EraseFromParent, /*InsnID*/0,
35984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
35985 // GIR_Coverage, 4848,
35986 GIR_Done,
35987 // Label 1730: @97064
35988 GIM_Try, /*On fail goto*//*Label 1731*/ 97142, // Rule ID 4851 //
35989 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
35990 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
35991 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
35992 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
35993 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
35994 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
35995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
35996 // MIs[0] base
35997 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
35998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
35999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36000 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36001 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36002 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36003 // (intrinsic_w_chain:{ *:[v8f16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
36005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36008 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36009 GIR_EraseFromParent, /*InsnID*/0,
36010 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36011 // GIR_Coverage, 4851,
36012 GIR_Done,
36013 // Label 1731: @97142
36014 GIM_Try, /*On fail goto*//*Label 1732*/ 97220, // Rule ID 4852 //
36015 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36016 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36017 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36018 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36019 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36020 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36022 // MIs[0] base
36023 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36026 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36027 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36028 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36029 // (intrinsic_w_chain:{ *:[v8f16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
36031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36034 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36035 GIR_EraseFromParent, /*InsnID*/0,
36036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36037 // GIR_Coverage, 4852,
36038 GIR_Done,
36039 // Label 1732: @97220
36040 GIM_Try, /*On fail goto*//*Label 1733*/ 97298, // Rule ID 4855 //
36041 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36042 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36043 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36044 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36045 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36046 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36048 // MIs[0] base
36049 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36052 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36053 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36054 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36055 // (intrinsic_w_chain:{ *:[v8f16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36056 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq_u,
36057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36060 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36061 GIR_EraseFromParent, /*InsnID*/0,
36062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36063 // GIR_Coverage, 4855,
36064 GIR_Done,
36065 // Label 1733: @97298
36066 GIM_Try, /*On fail goto*//*Label 1734*/ 97376, // Rule ID 4856 //
36067 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36068 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
36069 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
36070 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36071 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36072 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36074 // MIs[0] base
36075 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36078 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36079 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36080 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36081 // (intrinsic_w_chain:{ *:[v8f16] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36082 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU16_rq,
36083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36086 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36087 GIR_EraseFromParent, /*InsnID*/0,
36088 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36089 // GIR_Coverage, 4856,
36090 GIR_Done,
36091 // Label 1734: @97376
36092 GIM_Try, /*On fail goto*//*Label 1735*/ 97454, // Rule ID 4859 //
36093 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36094 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36095 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36096 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36097 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36098 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36100 // MIs[0] base
36101 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36104 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36105 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36106 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36107 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq_u,
36109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36112 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36113 GIR_EraseFromParent, /*InsnID*/0,
36114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36115 // GIR_Coverage, 4859,
36116 GIR_Done,
36117 // Label 1735: @97454
36118 GIM_Try, /*On fail goto*//*Label 1736*/ 97532, // Rule ID 4860 //
36119 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36120 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36121 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36122 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36123 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36124 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36126 // MIs[0] base
36127 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36130 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36131 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36132 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36133 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHU32_rq,
36135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36138 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36139 GIR_EraseFromParent, /*InsnID*/0,
36140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36141 // GIR_Coverage, 4860,
36142 GIR_Done,
36143 // Label 1736: @97532
36144 GIM_Try, /*On fail goto*//*Label 1737*/ 97610, // Rule ID 4863 //
36145 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36146 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36147 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36148 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36149 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36150 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36152 // MIs[0] base
36153 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36156 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36157 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36158 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36159 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq_u,
36161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36164 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36165 GIR_EraseFromParent, /*InsnID*/0,
36166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36167 // GIR_Coverage, 4863,
36168 GIR_Done,
36169 // Label 1737: @97610
36170 GIM_Try, /*On fail goto*//*Label 1738*/ 97688, // Rule ID 4864 //
36171 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36172 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36173 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36174 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36175 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36176 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36178 // MIs[0] base
36179 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36182 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 16,
36183 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 1,
36184 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36185 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRHS32_rq,
36187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36190 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36191 GIR_EraseFromParent, /*InsnID*/0,
36192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36193 // GIR_Coverage, 4864,
36194 GIR_Done,
36195 // Label 1738: @97688
36196 GIM_Try, /*On fail goto*//*Label 1739*/ 97766, // Rule ID 4867 //
36197 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36198 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36199 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36200 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36201 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36202 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36204 // MIs[0] base
36205 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36208 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36209 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36210 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36211 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36212 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
36213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36216 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36217 GIR_EraseFromParent, /*InsnID*/0,
36218 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36219 // GIR_Coverage, 4867,
36220 GIR_Done,
36221 // Label 1739: @97766
36222 GIM_Try, /*On fail goto*//*Label 1740*/ 97844, // Rule ID 4868 //
36223 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36224 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36225 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36226 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36227 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36228 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36230 // MIs[0] base
36231 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36234 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36235 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36236 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36237 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
36239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36242 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36243 GIR_EraseFromParent, /*InsnID*/0,
36244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36245 // GIR_Coverage, 4868,
36246 GIR_Done,
36247 // Label 1740: @97844
36248 GIM_Try, /*On fail goto*//*Label 1741*/ 97922, // Rule ID 4871 //
36249 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36250 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36251 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36252 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36253 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36254 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36256 // MIs[0] base
36257 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36260 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36261 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36262 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36263 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
36265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36268 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36269 GIR_EraseFromParent, /*InsnID*/0,
36270 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36271 // GIR_Coverage, 4871,
36272 GIR_Done,
36273 // Label 1741: @97922
36274 GIM_Try, /*On fail goto*//*Label 1742*/ 98000, // Rule ID 4872 //
36275 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36276 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36277 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36278 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36279 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36280 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36282 // MIs[0] base
36283 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36286 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36287 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36288 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36289 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
36291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36294 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36295 GIR_EraseFromParent, /*InsnID*/0,
36296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36297 // GIR_Coverage, 4872,
36298 GIR_Done,
36299 // Label 1742: @98000
36300 GIM_Try, /*On fail goto*//*Label 1743*/ 98078, // Rule ID 4875 //
36301 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36302 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36303 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36304 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36305 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36306 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36308 // MIs[0] base
36309 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36312 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36313 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36314 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36315 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
36317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36320 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36321 GIR_EraseFromParent, /*InsnID*/0,
36322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36323 // GIR_Coverage, 4875,
36324 GIR_Done,
36325 // Label 1743: @98078
36326 GIM_Try, /*On fail goto*//*Label 1744*/ 98156, // Rule ID 4876 //
36327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36328 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36329 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36330 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36331 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36332 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36334 // MIs[0] base
36335 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36338 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36339 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36340 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36341 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36342 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
36343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36346 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36347 GIR_EraseFromParent, /*InsnID*/0,
36348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36349 // GIR_Coverage, 4876,
36350 GIR_Done,
36351 // Label 1744: @98156
36352 GIM_Try, /*On fail goto*//*Label 1745*/ 98234, // Rule ID 4879 //
36353 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36354 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36355 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36356 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36357 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36358 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36360 // MIs[0] base
36361 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36364 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36365 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36366 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36367 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36368 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
36369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36372 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36373 GIR_EraseFromParent, /*InsnID*/0,
36374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36375 // GIR_Coverage, 4879,
36376 GIR_Done,
36377 // Label 1745: @98234
36378 GIM_Try, /*On fail goto*//*Label 1746*/ 98312, // Rule ID 4880 //
36379 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36380 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36381 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36382 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36383 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36384 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36386 // MIs[0] base
36387 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36390 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36391 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36392 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36393 // (intrinsic_w_chain:{ *:[v4i32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
36395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36398 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36399 GIR_EraseFromParent, /*InsnID*/0,
36400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36401 // GIR_Coverage, 4880,
36402 GIR_Done,
36403 // Label 1746: @98312
36404 GIM_Try, /*On fail goto*//*Label 1747*/ 98390, // Rule ID 4883 //
36405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36406 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36407 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36408 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36409 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36410 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36412 // MIs[0] base
36413 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36416 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36417 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36418 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36419 // (intrinsic_w_chain:{ *:[v4f32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
36421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36424 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36425 GIR_EraseFromParent, /*InsnID*/0,
36426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36427 // GIR_Coverage, 4883,
36428 GIR_Done,
36429 // Label 1747: @98390
36430 GIM_Try, /*On fail goto*//*Label 1748*/ 98468, // Rule ID 4884 //
36431 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36432 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36433 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36434 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36435 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36436 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36438 // MIs[0] base
36439 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36442 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36443 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36444 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36445 // (intrinsic_w_chain:{ *:[v4f32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
36447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36450 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36451 GIR_EraseFromParent, /*InsnID*/0,
36452 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36453 // GIR_Coverage, 4884,
36454 GIR_Done,
36455 // Label 1748: @98468
36456 GIM_Try, /*On fail goto*//*Label 1749*/ 98546, // Rule ID 4887 //
36457 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36458 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36459 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36460 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36461 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36462 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36464 // MIs[0] base
36465 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36468 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36469 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36470 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36471 // (intrinsic_w_chain:{ *:[v4f32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq_u,
36473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36476 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36477 GIR_EraseFromParent, /*InsnID*/0,
36478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36479 // GIR_Coverage, 4887,
36480 GIR_Done,
36481 // Label 1749: @98546
36482 GIM_Try, /*On fail goto*//*Label 1750*/ 98624, // Rule ID 4888 //
36483 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36484 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
36485 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
36486 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36487 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36488 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36490 // MIs[0] base
36491 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36494 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 32,
36495 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 2,
36496 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36497 // (intrinsic_w_chain:{ *:[v4f32] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRWU32_rq,
36499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36502 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36503 GIR_EraseFromParent, /*InsnID*/0,
36504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36505 // GIR_Coverage, 4888,
36506 GIR_Done,
36507 // Label 1750: @98624
36508 GIM_Try, /*On fail goto*//*Label 1751*/ 98702, // Rule ID 4891 //
36509 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36510 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36511 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36512 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36513 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36514 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36516 // MIs[0] base
36517 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36520 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36521 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36522 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36523 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
36525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36528 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36529 GIR_EraseFromParent, /*InsnID*/0,
36530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36531 // GIR_Coverage, 4891,
36532 GIR_Done,
36533 // Label 1751: @98702
36534 GIM_Try, /*On fail goto*//*Label 1752*/ 98780, // Rule ID 4892 //
36535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36536 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36537 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36538 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36539 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36540 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36542 // MIs[0] base
36543 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36546 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36547 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
36548 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36549 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
36551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36554 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36555 GIR_EraseFromParent, /*InsnID*/0,
36556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36557 // GIR_Coverage, 4892,
36558 GIR_Done,
36559 // Label 1752: @98780
36560 GIM_Try, /*On fail goto*//*Label 1753*/ 98858, // Rule ID 4895 //
36561 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36562 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36563 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36564 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36565 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36566 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36568 // MIs[0] base
36569 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36572 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36573 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36574 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36575 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
36577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36580 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36581 GIR_EraseFromParent, /*InsnID*/0,
36582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36583 // GIR_Coverage, 4895,
36584 GIR_Done,
36585 // Label 1753: @98858
36586 GIM_Try, /*On fail goto*//*Label 1754*/ 98936, // Rule ID 4896 //
36587 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36588 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36589 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36590 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36591 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36592 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36594 // MIs[0] base
36595 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36598 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36599 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
36600 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36601 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
36603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36606 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36607 GIR_EraseFromParent, /*InsnID*/0,
36608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36609 // GIR_Coverage, 4896,
36610 GIR_Done,
36611 // Label 1754: @98936
36612 GIM_Try, /*On fail goto*//*Label 1755*/ 99014, // Rule ID 4899 //
36613 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36614 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36615 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36616 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36617 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36618 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36620 // MIs[0] base
36621 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36624 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36625 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36626 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36627 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
36629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36632 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36633 GIR_EraseFromParent, /*InsnID*/0,
36634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36635 // GIR_Coverage, 4899,
36636 GIR_Done,
36637 // Label 1755: @99014
36638 GIM_Try, /*On fail goto*//*Label 1756*/ 99092, // Rule ID 4900 //
36639 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36640 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36641 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36642 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36643 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36644 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36646 // MIs[0] base
36647 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36650 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36651 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
36652 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 0,
36653 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
36655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36658 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36659 GIR_EraseFromParent, /*InsnID*/0,
36660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36661 // GIR_Coverage, 4900,
36662 GIR_Done,
36663 // Label 1756: @99092
36664 GIM_Try, /*On fail goto*//*Label 1757*/ 99170, // Rule ID 4903 //
36665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36667 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36668 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36669 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36670 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36672 // MIs[0] base
36673 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36676 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36677 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 0,
36678 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36679 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36680 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq_u,
36681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36684 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36685 GIR_EraseFromParent, /*InsnID*/0,
36686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36687 // GIR_Coverage, 4903,
36688 GIR_Done,
36689 // Label 1757: @99170
36690 GIM_Try, /*On fail goto*//*Label 1758*/ 99248, // Rule ID 4904 //
36691 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mve_vldr_gather_offset,
36692 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
36693 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
36694 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
36695 GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
36696 GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
36697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
36698 // MIs[0] base
36699 GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
36701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::MQPRRegClassID,
36702 GIM_CheckConstantInt, /*MI*/0, /*Op*/4, 64,
36703 GIM_CheckConstantInt, /*MI*/0, /*Op*/5, 3,
36704 GIM_CheckConstantInt, /*MI*/0, /*Op*/6, 1,
36705 // (intrinsic_w_chain:{ *:[v2i64] } 2042:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VLDRDU64_rq,
36707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
36708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // base
36709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // offsets
36710 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36711 GIR_EraseFromParent, /*InsnID*/0,
36712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36713 // GIR_Coverage, 4904,
36714 GIR_Done,
36715 // Label 1758: @99248
36716 GIM_Try, /*On fail goto*//*Label 1759*/ 99322, // Rule ID 263 //
36717 GIM_CheckFeatures, GIFBS_IsARM,
36718 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
36719 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36720 // MIs[0] cop
36721 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36722 // MIs[0] opc1
36723 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
36725 // MIs[0] CRn
36726 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36727 // MIs[0] CRm
36728 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36729 // MIs[0] opc2
36730 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36731 // (intrinsic_void 1917:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR,
36733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36739 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36740 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36741 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36742 GIR_EraseFromParent, /*InsnID*/0,
36743 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36744 // GIR_Coverage, 263,
36745 GIR_Done,
36746 // Label 1759: @99322
36747 GIM_Try, /*On fail goto*//*Label 1760*/ 99389, // Rule ID 264 //
36748 GIM_CheckFeatures, GIFBS_IsARM_PreV8,
36749 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
36750 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36751 // MIs[0] cop
36752 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36753 // MIs[0] opc1
36754 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
36756 // MIs[0] CRn
36757 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36758 // MIs[0] CRm
36759 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36760 // MIs[0] opc2
36761 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36762 // (intrinsic_void 1918:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR2,
36764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36766 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36770 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36771 GIR_EraseFromParent, /*InsnID*/0,
36772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36773 // GIR_Coverage, 264,
36774 GIR_Done,
36775 // Label 1760: @99389
36776 GIM_Try, /*On fail goto*//*Label 1761*/ 99463, // Rule ID 609 //
36777 GIM_CheckFeatures, GIFBS_IsThumb2,
36778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
36779 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36780 // MIs[0] cop
36781 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36782 // MIs[0] opc1
36783 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
36785 // MIs[0] CRn
36786 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36787 // MIs[0] CRm
36788 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36789 // MIs[0] opc2
36790 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36791 // (intrinsic_void 1917:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR,
36793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36799 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36800 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36801 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36802 GIR_EraseFromParent, /*InsnID*/0,
36803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36804 // GIR_Coverage, 609,
36805 GIR_Done,
36806 // Label 1761: @99463
36807 GIM_Try, /*On fail goto*//*Label 1762*/ 99537, // Rule ID 610 //
36808 GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
36809 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
36810 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
36811 // MIs[0] cop
36812 GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36813 // MIs[0] opc1
36814 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
36816 // MIs[0] CRn
36817 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36818 // MIs[0] CRm
36819 GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36820 // MIs[0] opc2
36821 GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36822 // (intrinsic_void 1918:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36823 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR2,
36824 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cop
36825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // opc1
36826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
36827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // CRn
36828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // CRm
36829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // opc2
36830 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36831 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36832 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
36833 GIR_EraseFromParent, /*InsnID*/0,
36834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36835 // GIR_Coverage, 610,
36836 GIR_Done,
36837 // Label 1762: @99537
36838 GIM_Reject,
36839 // Label 1712: @99538
36840 GIM_Reject,
36841 // Label 14: @99539
36842 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1766*/ 99673,
36843 /*GILLT_v2s64*//*Label 1763*/ 99553, 0, 0,
36844 /*GILLT_v4s32*//*Label 1764*/ 99593, 0, 0, 0,
36845 /*GILLT_v8s16*//*Label 1765*/ 99633,
36846 // Label 1763: @99553
36847 GIM_Try, /*On fail goto*//*Label 1767*/ 99592, // Rule ID 2585 //
36848 GIM_CheckFeatures, GIFBS_HasNEON,
36849 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
36850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36852 // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
36853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
36854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36856 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36857 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36858 GIR_EraseFromParent, /*InsnID*/0,
36859 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36860 // GIR_Coverage, 2585,
36861 GIR_Done,
36862 // Label 1767: @99592
36863 GIM_Reject,
36864 // Label 1764: @99593
36865 GIM_Try, /*On fail goto*//*Label 1768*/ 99632, // Rule ID 2584 //
36866 GIM_CheckFeatures, GIFBS_HasNEON,
36867 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
36868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36870 // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
36871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
36872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36874 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36875 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36876 GIR_EraseFromParent, /*InsnID*/0,
36877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36878 // GIR_Coverage, 2584,
36879 GIR_Done,
36880 // Label 1768: @99632
36881 GIM_Reject,
36882 // Label 1765: @99633
36883 GIM_Try, /*On fail goto*//*Label 1769*/ 99672, // Rule ID 2583 //
36884 GIM_CheckFeatures, GIFBS_HasNEON,
36885 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
36886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
36887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
36888 // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
36889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
36890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36892 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36893 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36894 GIR_EraseFromParent, /*InsnID*/0,
36895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36896 // GIR_Coverage, 2583,
36897 GIR_Done,
36898 // Label 1769: @99672
36899 GIM_Reject,
36900 // Label 1766: @99673
36901 GIM_Reject,
36902 // Label 15: @99674
36903 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 11, /*)*//*default:*//*Label 1773*/ 99808,
36904 /*GILLT_v2s32*//*Label 1770*/ 99688, 0, 0,
36905 /*GILLT_v4s16*//*Label 1771*/ 99728, 0, 0, 0,
36906 /*GILLT_v8s8*//*Label 1772*/ 99768,
36907 // Label 1770: @99688
36908 GIM_Try, /*On fail goto*//*Label 1774*/ 99727, // Rule ID 1604 //
36909 GIM_CheckFeatures, GIFBS_HasNEON,
36910 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
36911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36913 // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
36914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv2i32,
36915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36917 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36918 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36919 GIR_EraseFromParent, /*InsnID*/0,
36920 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36921 // GIR_Coverage, 1604,
36922 GIR_Done,
36923 // Label 1774: @99727
36924 GIM_Reject,
36925 // Label 1771: @99728
36926 GIM_Try, /*On fail goto*//*Label 1775*/ 99767, // Rule ID 1603 //
36927 GIM_CheckFeatures, GIFBS_HasNEON,
36928 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
36929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36931 // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
36932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv4i16,
36933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36935 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36936 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36937 GIR_EraseFromParent, /*InsnID*/0,
36938 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36939 // GIR_Coverage, 1603,
36940 GIR_Done,
36941 // Label 1775: @99767
36942 GIM_Reject,
36943 // Label 1772: @99768
36944 GIM_Try, /*On fail goto*//*Label 1776*/ 99807, // Rule ID 1602 //
36945 GIM_CheckFeatures, GIFBS_HasNEON,
36946 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
36947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
36948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
36949 // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
36950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv8i8,
36951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
36952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
36953 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36954 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36955 GIR_EraseFromParent, /*InsnID*/0,
36956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36957 // GIR_Coverage, 1602,
36958 GIR_Done,
36959 // Label 1776: @99807
36960 GIM_Reject,
36961 // Label 1773: @99808
36962 GIM_Reject,
36963 // Label 16: @99809
36964 GIM_Try, /*On fail goto*//*Label 1777*/ 100005,
36965 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
36966 GIM_Try, /*On fail goto*//*Label 1778*/ 99852, // Rule ID 411 //
36967 GIM_CheckFeatures, GIFBS_IsThumb2,
36968 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
36969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
36970 // MIs[0] Operand 1
36971 // No operand predicates
36972 // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
36973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi,
36974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
36975 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
36976 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36977 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36978 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36979 GIR_EraseFromParent, /*InsnID*/0,
36980 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36981 // GIR_Coverage, 411,
36982 GIR_Done,
36983 // Label 1778: @99852
36984 GIM_Try, /*On fail goto*//*Label 1779*/ 99889, // Rule ID 57 //
36985 GIM_CheckFeatures, GIFBS_IsARM,
36986 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
36987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
36988 // MIs[0] Operand 1
36989 // No operand predicates
36990 // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
36991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi,
36992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
36993 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
36994 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
36995 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36996 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
36997 GIR_EraseFromParent, /*InsnID*/0,
36998 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
36999 // GIR_Coverage, 57,
37000 GIR_Done,
37001 // Label 1779: @99889
37002 GIM_Try, /*On fail goto*//*Label 1780*/ 99922, // Rule ID 58 //
37003 GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
37004 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
37005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
37006 // MIs[0] Operand 1
37007 // No operand predicates
37008 // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
37009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi16,
37010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37011 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
37012 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37013 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37014 GIR_EraseFromParent, /*InsnID*/0,
37015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37016 // GIR_Coverage, 58,
37017 GIR_Done,
37018 // Label 1780: @99922
37019 GIM_Try, /*On fail goto*//*Label 1781*/ 99948, // Rule ID 275 //
37020 GIM_CheckFeatures, GIFBS_IsARM,
37021 GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APInt_Predicate_arm_i32imm,
37022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
37023 // MIs[0] Operand 1
37024 // No operand predicates
37025 // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
37026 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi32imm,
37027 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
37028 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
37029 GIR_EraseFromParent, /*InsnID*/0,
37030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37031 // GIR_Coverage, 275,
37032 GIR_Done,
37033 // Label 1781: @99948
37034 GIM_Try, /*On fail goto*//*Label 1782*/ 99981, // Rule ID 412 //
37035 GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
37036 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
37037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37038 // MIs[0] Operand 1
37039 // No operand predicates
37040 // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
37041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi16,
37042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37043 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
37044 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37045 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37046 GIR_EraseFromParent, /*InsnID*/0,
37047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37048 // GIR_Coverage, 412,
37049 GIR_Done,
37050 // Label 1782: @99981
37051 GIM_Try, /*On fail goto*//*Label 1783*/ 100004, // Rule ID 598 //
37052 GIM_CheckFeatures, GIFBS_IsThumb_UseMovt,
37053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37054 // MIs[0] Operand 1
37055 // No operand predicates
37056 // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
37057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi32imm,
37058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
37059 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
37060 GIR_EraseFromParent, /*InsnID*/0,
37061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37062 // GIR_Coverage, 598,
37063 GIR_Done,
37064 // Label 1783: @100004
37065 GIM_Reject,
37066 // Label 1777: @100005
37067 GIM_Reject,
37068 // Label 17: @100006
37069 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1786*/ 100084,
37070 /*GILLT_s32*//*Label 1784*/ 100014,
37071 /*GILLT_s64*//*Label 1785*/ 100049,
37072 // Label 1784: @100014
37073 GIM_Try, /*On fail goto*//*Label 1787*/ 100048, // Rule ID 742 //
37074 GIM_CheckFeatures, GIFBS_HasVFP3,
37075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
37076 // MIs[0] Operand 1
37077 // No operand predicates
37078 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f32imm,
37079 // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
37080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTS,
37081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
37082 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF32Imm, // imm
37083 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37084 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37085 GIR_EraseFromParent, /*InsnID*/0,
37086 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37087 // GIR_Coverage, 742,
37088 GIR_Done,
37089 // Label 1787: @100048
37090 GIM_Reject,
37091 // Label 1785: @100049
37092 GIM_Try, /*On fail goto*//*Label 1788*/ 100083, // Rule ID 741 //
37093 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP3,
37094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37095 // MIs[0] Operand 1
37096 // No operand predicates
37097 GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_vfp_f64imm,
37098 // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
37099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::FCONSTD,
37100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
37101 GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderVFPF64Imm, // imm
37102 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37103 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37104 GIR_EraseFromParent, /*InsnID*/0,
37105 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37106 // GIR_Coverage, 741,
37107 GIR_Done,
37108 // Label 1788: @100083
37109 GIM_Reject,
37110 // Label 1786: @100084
37111 GIM_Reject,
37112 // Label 18: @100085
37113 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1792*/ 100219,
37114 /*GILLT_v2s64*//*Label 1789*/ 100099, 0, 0,
37115 /*GILLT_v4s32*//*Label 1790*/ 100139, 0, 0, 0,
37116 /*GILLT_v8s16*//*Label 1791*/ 100179,
37117 // Label 1789: @100099
37118 GIM_Try, /*On fail goto*//*Label 1793*/ 100138, // Rule ID 1616 //
37119 GIM_CheckFeatures, GIFBS_HasNEON,
37120 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37123 // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
37124 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv2i64,
37125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37127 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37128 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37129 GIR_EraseFromParent, /*InsnID*/0,
37130 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37131 // GIR_Coverage, 1616,
37132 GIR_Done,
37133 // Label 1793: @100138
37134 GIM_Reject,
37135 // Label 1790: @100139
37136 GIM_Try, /*On fail goto*//*Label 1794*/ 100178, // Rule ID 1615 //
37137 GIM_CheckFeatures, GIFBS_HasNEON,
37138 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37141 // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
37142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv4i32,
37143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37145 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37146 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37147 GIR_EraseFromParent, /*InsnID*/0,
37148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37149 // GIR_Coverage, 1615,
37150 GIR_Done,
37151 // Label 1794: @100178
37152 GIM_Reject,
37153 // Label 1791: @100179
37154 GIM_Try, /*On fail goto*//*Label 1795*/ 100218, // Rule ID 1614 //
37155 GIM_CheckFeatures, GIFBS_HasNEON,
37156 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37159 // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
37160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv8i16,
37161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37163 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37164 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37165 GIR_EraseFromParent, /*InsnID*/0,
37166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37167 // GIR_Coverage, 1614,
37168 GIR_Done,
37169 // Label 1795: @100218
37170 GIM_Reject,
37171 // Label 1792: @100219
37172 GIM_Reject,
37173 // Label 19: @100220
37174 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 12, /*)*//*default:*//*Label 1799*/ 100741,
37175 /*GILLT_v2s64*//*Label 1796*/ 100234, 0, 0,
37176 /*GILLT_v4s32*//*Label 1797*/ 100403, 0, 0, 0,
37177 /*GILLT_v8s16*//*Label 1798*/ 100572,
37178 // Label 1796: @100234
37179 GIM_Try, /*On fail goto*//*Label 1800*/ 100402,
37180 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37182 GIM_Try, /*On fail goto*//*Label 1801*/ 100307, // Rule ID 1191 //
37183 GIM_CheckFeatures, GIFBS_HasNEON,
37184 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37185 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
37186 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37187 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
37188 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37189 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37190 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37191 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
37192 GIM_CheckIsSafeToFold, /*InsnID*/1,
37193 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2142:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37194 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv2i64,
37195 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37196 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37197 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37198 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37199 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37200 GIR_EraseFromParent, /*InsnID*/0,
37201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37202 // GIR_Coverage, 1191,
37203 GIR_Done,
37204 // Label 1801: @100307
37205 GIM_Try, /*On fail goto*//*Label 1802*/ 100370, // Rule ID 1194 //
37206 GIM_CheckFeatures, GIFBS_HasNEON,
37207 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37208 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
37209 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37210 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
37211 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37212 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37213 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37214 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
37215 GIM_CheckIsSafeToFold, /*InsnID*/1,
37216 // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2143:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv2i64,
37218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37221 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37222 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37223 GIR_EraseFromParent, /*InsnID*/0,
37224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37225 // GIR_Coverage, 1194,
37226 GIR_Done,
37227 // Label 1802: @100370
37228 GIM_Try, /*On fail goto*//*Label 1803*/ 100401, // Rule ID 1619 //
37229 GIM_CheckFeatures, GIFBS_HasNEON,
37230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37231 // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
37232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
37233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37235 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37236 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37237 GIR_EraseFromParent, /*InsnID*/0,
37238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37239 // GIR_Coverage, 1619,
37240 GIR_Done,
37241 // Label 1803: @100401
37242 GIM_Reject,
37243 // Label 1800: @100402
37244 GIM_Reject,
37245 // Label 1797: @100403
37246 GIM_Try, /*On fail goto*//*Label 1804*/ 100571,
37247 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37249 GIM_Try, /*On fail goto*//*Label 1805*/ 100476, // Rule ID 1190 //
37250 GIM_CheckFeatures, GIFBS_HasNEON,
37251 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37252 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
37253 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37254 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
37255 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37256 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37257 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37258 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
37259 GIM_CheckIsSafeToFold, /*InsnID*/1,
37260 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2142:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv4i32,
37262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37265 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37266 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37267 GIR_EraseFromParent, /*InsnID*/0,
37268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37269 // GIR_Coverage, 1190,
37270 GIR_Done,
37271 // Label 1805: @100476
37272 GIM_Try, /*On fail goto*//*Label 1806*/ 100539, // Rule ID 1193 //
37273 GIM_CheckFeatures, GIFBS_HasNEON,
37274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37275 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
37276 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37277 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
37278 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37279 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37280 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37281 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
37282 GIM_CheckIsSafeToFold, /*InsnID*/1,
37283 // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 2143:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
37285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37288 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37289 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37290 GIR_EraseFromParent, /*InsnID*/0,
37291 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37292 // GIR_Coverage, 1193,
37293 GIR_Done,
37294 // Label 1806: @100539
37295 GIM_Try, /*On fail goto*//*Label 1807*/ 100570, // Rule ID 1618 //
37296 GIM_CheckFeatures, GIFBS_HasNEON,
37297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37298 // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
37299 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
37300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37302 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37303 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37304 GIR_EraseFromParent, /*InsnID*/0,
37305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37306 // GIR_Coverage, 1618,
37307 GIR_Done,
37308 // Label 1807: @100570
37309 GIM_Reject,
37310 // Label 1804: @100571
37311 GIM_Reject,
37312 // Label 1798: @100572
37313 GIM_Try, /*On fail goto*//*Label 1808*/ 100740,
37314 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37316 GIM_Try, /*On fail goto*//*Label 1809*/ 100645, // Rule ID 1189 //
37317 GIM_CheckFeatures, GIFBS_HasNEON,
37318 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37319 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
37320 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37321 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
37322 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
37323 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
37324 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37325 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
37326 GIM_CheckIsSafeToFold, /*InsnID*/1,
37327 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2142:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv8i16,
37329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37332 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37333 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37334 GIR_EraseFromParent, /*InsnID*/0,
37335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37336 // GIR_Coverage, 1189,
37337 GIR_Done,
37338 // Label 1809: @100645
37339 GIM_Try, /*On fail goto*//*Label 1810*/ 100708, // Rule ID 1192 //
37340 GIM_CheckFeatures, GIFBS_HasNEON,
37341 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37342 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
37343 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37344 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
37345 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
37346 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
37347 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37348 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
37349 GIM_CheckIsSafeToFold, /*InsnID*/1,
37350 // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 2143:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
37352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37355 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37356 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37357 GIR_EraseFromParent, /*InsnID*/0,
37358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37359 // GIR_Coverage, 1192,
37360 GIR_Done,
37361 // Label 1810: @100708
37362 GIM_Try, /*On fail goto*//*Label 1811*/ 100739, // Rule ID 1617 //
37363 GIM_CheckFeatures, GIFBS_HasNEON,
37364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37365 // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
37366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
37367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
37369 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37370 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37371 GIR_EraseFromParent, /*InsnID*/0,
37372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37373 // GIR_Coverage, 1617,
37374 GIR_Done,
37375 // Label 1811: @100739
37376 GIM_Reject,
37377 // Label 1808: @100740
37378 GIM_Reject,
37379 // Label 1799: @100741
37380 GIM_Reject,
37381 // Label 20: @100742
37382 GIM_Try, /*On fail goto*//*Label 1812*/ 100850,
37383 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
37384 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
37385 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
37386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37388 GIM_Try, /*On fail goto*//*Label 1813*/ 100810, // Rule ID 477 //
37389 GIM_CheckFeatures, GIFBS_IsThumb2,
37390 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37391 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
37392 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm1_31,
37393 // MIs[1] Operand 1
37394 // No operand predicates
37395 GIM_CheckIsSafeToFold, /*InsnID*/1,
37396 // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
37397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLri,
37398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
37400 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
37401 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37402 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37403 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37404 GIR_EraseFromParent, /*InsnID*/0,
37405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37406 // GIR_Coverage, 477,
37407 GIR_Done,
37408 // Label 1813: @100810
37409 GIM_Try, /*On fail goto*//*Label 1814*/ 100849, // Rule ID 478 //
37410 GIM_CheckFeatures, GIFBS_IsThumb2,
37411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37412 // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
37413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr,
37414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
37416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37417 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37418 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37419 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37420 GIR_EraseFromParent, /*InsnID*/0,
37421 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37422 // GIR_Coverage, 478,
37423 GIR_Done,
37424 // Label 1814: @100849
37425 GIM_Reject,
37426 // Label 1812: @100850
37427 GIM_Reject,
37428 // Label 21: @100851
37429 GIM_Try, /*On fail goto*//*Label 1815*/ 100910, // Rule ID 480 //
37430 GIM_CheckFeatures, GIFBS_IsThumb2,
37431 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
37432 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
37433 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
37434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37437 // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
37438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSRrr,
37439 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
37441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37442 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37443 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37444 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37445 GIR_EraseFromParent, /*InsnID*/0,
37446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37447 // GIR_Coverage, 480,
37448 GIR_Done,
37449 // Label 1815: @100910
37450 GIM_Reject,
37451 // Label 22: @100911
37452 GIM_Try, /*On fail goto*//*Label 1816*/ 101128,
37453 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
37454 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
37455 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
37456 GIM_Try, /*On fail goto*//*Label 1817*/ 100977, // Rule ID 201 //
37457 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
37458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
37459 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37460 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
37461 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37462 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
37463 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
37464 GIM_CheckIsSafeToFold, /*InsnID*/1,
37465 // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
37466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
37467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
37469 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37470 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37471 GIR_EraseFromParent, /*InsnID*/0,
37472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37473 // GIR_Coverage, 201,
37474 GIR_Done,
37475 // Label 1817: @100977
37476 GIM_Try, /*On fail goto*//*Label 1818*/ 101029, // Rule ID 335 //
37477 GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
37478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
37479 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37480 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
37481 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37482 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
37483 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
37484 GIM_CheckIsSafeToFold, /*InsnID*/1,
37485 // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
37486 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREVSH,
37487 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
37489 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37490 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37491 GIR_EraseFromParent, /*InsnID*/0,
37492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37493 // GIR_Coverage, 335,
37494 GIR_Done,
37495 // Label 1818: @101029
37496 GIM_Try, /*On fail goto*//*Label 1819*/ 101127,
37497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37498 GIM_Try, /*On fail goto*//*Label 1820*/ 101083, // Rule ID 545 //
37499 GIM_CheckFeatures, GIFBS_IsThumb2,
37500 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37501 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
37502 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37503 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37504 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
37505 GIM_CheckIsSafeToFold, /*InsnID*/1,
37506 // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
37507 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
37508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
37510 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37511 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37512 GIR_EraseFromParent, /*InsnID*/0,
37513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37514 // GIR_Coverage, 545,
37515 GIR_Done,
37516 // Label 1820: @101083
37517 GIM_Try, /*On fail goto*//*Label 1821*/ 101126, // Rule ID 482 //
37518 GIM_CheckFeatures, GIFBS_IsThumb2,
37519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37521 // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
37522 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ASRrr,
37523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
37525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37526 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37527 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37528 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37529 GIR_EraseFromParent, /*InsnID*/0,
37530 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37531 // GIR_Coverage, 482,
37532 GIR_Done,
37533 // Label 1821: @101126
37534 GIM_Reject,
37535 // Label 1819: @101127
37536 GIM_Reject,
37537 // Label 1816: @101128
37538 GIM_Reject,
37539 // Label 23: @101129
37540 GIM_Try, /*On fail goto*//*Label 1822*/ 101230,
37541 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
37542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
37543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
37544 GIM_Try, /*On fail goto*//*Label 1823*/ 101186, // Rule ID 178 //
37545 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
37546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
37547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
37548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37549 // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
37550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMUL,
37551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
37553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37554 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37555 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37556 GIR_EraseFromParent, /*InsnID*/0,
37557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37558 // GIR_Coverage, 178,
37559 GIR_Done,
37560 // Label 1823: @101186
37561 GIM_Try, /*On fail goto*//*Label 1824*/ 101229, // Rule ID 514 //
37562 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
37563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37566 // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
37567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMUL,
37568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
37570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37571 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37572 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37573 GIR_EraseFromParent, /*InsnID*/0,
37574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37575 // GIR_Coverage, 514,
37576 GIR_Done,
37577 // Label 1824: @101229
37578 GIM_Reject,
37579 // Label 1822: @101230
37580 GIM_Reject,
37581 // Label 24: @101231
37582 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 15, /*)*//*default:*//*Label 1833*/ 101846,
37583 /*GILLT_s64*//*Label 1825*/ 101250,
37584 /*GILLT_v2s32*//*Label 1826*/ 101302,
37585 /*GILLT_v2s64*//*Label 1827*/ 101354, 0,
37586 /*GILLT_v4s16*//*Label 1828*/ 101406,
37587 /*GILLT_v4s32*//*Label 1829*/ 101458, 0, 0,
37588 /*GILLT_v8s8*//*Label 1830*/ 101570,
37589 /*GILLT_v8s16*//*Label 1831*/ 101622, 0, 0,
37590 /*GILLT_v16s8*//*Label 1832*/ 101734,
37591 // Label 1825: @101250
37592 GIM_Try, /*On fail goto*//*Label 1834*/ 101301, // Rule ID 844 //
37593 GIM_CheckFeatures, GIFBS_HasNEON,
37594 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
37595 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
37596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37599 // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
37600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv1i64,
37601 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37604 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37605 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37606 GIR_EraseFromParent, /*InsnID*/0,
37607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37608 // GIR_Coverage, 844,
37609 GIR_Done,
37610 // Label 1834: @101301
37611 GIM_Reject,
37612 // Label 1826: @101302
37613 GIM_Try, /*On fail goto*//*Label 1835*/ 101353, // Rule ID 839 //
37614 GIM_CheckFeatures, GIFBS_HasNEON,
37615 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
37616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
37617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37620 // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i32,
37622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37625 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37626 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37627 GIR_EraseFromParent, /*InsnID*/0,
37628 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37629 // GIR_Coverage, 839,
37630 GIR_Done,
37631 // Label 1835: @101353
37632 GIM_Reject,
37633 // Label 1827: @101354
37634 GIM_Try, /*On fail goto*//*Label 1836*/ 101405, // Rule ID 845 //
37635 GIM_CheckFeatures, GIFBS_HasNEON,
37636 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
37637 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
37638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37641 // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37642 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i64,
37643 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37646 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37647 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37648 GIR_EraseFromParent, /*InsnID*/0,
37649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37650 // GIR_Coverage, 845,
37651 GIR_Done,
37652 // Label 1836: @101405
37653 GIM_Reject,
37654 // Label 1828: @101406
37655 GIM_Try, /*On fail goto*//*Label 1837*/ 101457, // Rule ID 838 //
37656 GIM_CheckFeatures, GIFBS_HasNEON,
37657 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
37658 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
37659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37662 // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i16,
37664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37667 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37668 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37669 GIR_EraseFromParent, /*InsnID*/0,
37670 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37671 // GIR_Coverage, 838,
37672 GIR_Done,
37673 // Label 1837: @101457
37674 GIM_Reject,
37675 // Label 1829: @101458
37676 GIM_Try, /*On fail goto*//*Label 1838*/ 101569,
37677 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
37678 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
37679 GIM_Try, /*On fail goto*//*Label 1839*/ 101511, // Rule ID 841 //
37680 GIM_CheckFeatures, GIFBS_HasNEON,
37681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37684 // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i32,
37686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37689 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37690 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37691 GIR_EraseFromParent, /*InsnID*/0,
37692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37693 // GIR_Coverage, 841,
37694 GIR_Done,
37695 // Label 1839: @101511
37696 GIM_Try, /*On fail goto*//*Label 1840*/ 101568, // Rule ID 3517 //
37697 GIM_CheckFeatures, GIFBS_HasMVEInt,
37698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37701 // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37702 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37703 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37704 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDu32,
37706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37709 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37710 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37711 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37712 GIR_EraseFromParent, /*InsnID*/0,
37713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37714 // GIR_Coverage, 3517,
37715 GIR_Done,
37716 // Label 1840: @101568
37717 GIM_Reject,
37718 // Label 1838: @101569
37719 GIM_Reject,
37720 // Label 1830: @101570
37721 GIM_Try, /*On fail goto*//*Label 1841*/ 101621, // Rule ID 842 //
37722 GIM_CheckFeatures, GIFBS_HasNEON,
37723 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
37724 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
37725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37728 // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i8,
37730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37733 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37734 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37735 GIR_EraseFromParent, /*InsnID*/0,
37736 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37737 // GIR_Coverage, 842,
37738 GIR_Done,
37739 // Label 1841: @101621
37740 GIM_Reject,
37741 // Label 1831: @101622
37742 GIM_Try, /*On fail goto*//*Label 1842*/ 101733,
37743 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
37744 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
37745 GIM_Try, /*On fail goto*//*Label 1843*/ 101675, // Rule ID 840 //
37746 GIM_CheckFeatures, GIFBS_HasNEON,
37747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37750 // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i16,
37752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37755 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37756 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37757 GIR_EraseFromParent, /*InsnID*/0,
37758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37759 // GIR_Coverage, 840,
37760 GIR_Done,
37761 // Label 1843: @101675
37762 GIM_Try, /*On fail goto*//*Label 1844*/ 101732, // Rule ID 3514 //
37763 GIM_CheckFeatures, GIFBS_HasMVEInt,
37764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37767 // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37768 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37769 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37770 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDu16,
37772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37775 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37776 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37777 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37778 GIR_EraseFromParent, /*InsnID*/0,
37779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37780 // GIR_Coverage, 3514,
37781 GIR_Done,
37782 // Label 1844: @101732
37783 GIM_Reject,
37784 // Label 1842: @101733
37785 GIM_Reject,
37786 // Label 1832: @101734
37787 GIM_Try, /*On fail goto*//*Label 1845*/ 101845,
37788 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
37789 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
37790 GIM_Try, /*On fail goto*//*Label 1846*/ 101787, // Rule ID 843 //
37791 GIM_CheckFeatures, GIFBS_HasNEON,
37792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
37793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
37794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
37795 // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37796 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv16i8,
37797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37800 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37801 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37802 GIR_EraseFromParent, /*InsnID*/0,
37803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37804 // GIR_Coverage, 843,
37805 GIR_Done,
37806 // Label 1846: @101787
37807 GIM_Try, /*On fail goto*//*Label 1847*/ 101844, // Rule ID 3511 //
37808 GIM_CheckFeatures, GIFBS_HasMVEInt,
37809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
37810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
37811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
37812 // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37813 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37814 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
37815 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
37816 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDu8,
37817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
37818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
37819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
37820 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
37821 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37822 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
37823 GIR_EraseFromParent, /*InsnID*/0,
37824 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37825 // GIR_Coverage, 3511,
37826 GIR_Done,
37827 // Label 1847: @101844
37828 GIM_Reject,
37829 // Label 1845: @101845
37830 GIM_Reject,
37831 // Label 1833: @101846
37832 GIM_Reject,
37833 // Label 25: @101847
37834 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 1857*/ 103690,
37835 /*GILLT_s32*//*Label 1848*/ 101867,
37836 /*GILLT_s64*//*Label 1849*/ 102209,
37837 /*GILLT_v2s32*//*Label 1850*/ 102261,
37838 /*GILLT_v2s64*//*Label 1851*/ 102458, 0,
37839 /*GILLT_v4s16*//*Label 1852*/ 102655,
37840 /*GILLT_v4s32*//*Label 1853*/ 102852, 0, 0,
37841 /*GILLT_v8s8*//*Label 1854*/ 103264,
37842 /*GILLT_v8s16*//*Label 1855*/ 103316, 0, 0,
37843 /*GILLT_v16s8*//*Label 1856*/ 103578,
37844 // Label 1848: @101867
37845 GIM_Try, /*On fail goto*//*Label 1858*/ 102208,
37846 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
37847 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
37848 GIM_Try, /*On fail goto*//*Label 1859*/ 101938, // Rule ID 5527 //
37849 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
37850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
37851 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37852 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
37853 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37854 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37855 // MIs[1] Rn
37856 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37858 GIM_CheckIsSafeToFold, /*InsnID*/1,
37859 // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
37861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37864 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37865 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37866 GIR_EraseFromParent, /*InsnID*/0,
37867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37868 // GIR_Coverage, 5527,
37869 GIR_Done,
37870 // Label 1859: @101938
37871 GIM_Try, /*On fail goto*//*Label 1860*/ 101999, // Rule ID 5561 //
37872 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
37873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37875 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
37876 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37877 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37878 // MIs[1] Rn
37879 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37881 GIM_CheckIsSafeToFold, /*InsnID*/1,
37882 // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
37884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
37886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37887 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37888 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37889 GIR_EraseFromParent, /*InsnID*/0,
37890 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37891 // GIR_Coverage, 5561,
37892 GIR_Done,
37893 // Label 1860: @101999
37894 GIM_Try, /*On fail goto*//*Label 1861*/ 102060, // Rule ID 1888 //
37895 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
37896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
37897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37898 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37899 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
37900 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37901 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37902 // MIs[1] Rn
37903 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37904 GIM_CheckIsSafeToFold, /*InsnID*/1,
37905 // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
37907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37908 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
37909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37910 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37911 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37912 GIR_EraseFromParent, /*InsnID*/0,
37913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37914 // GIR_Coverage, 1888,
37915 GIR_Done,
37916 // Label 1861: @102060
37917 GIM_Try, /*On fail goto*//*Label 1862*/ 102121, // Rule ID 2132 //
37918 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
37919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37921 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37922 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
37923 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37924 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37925 // MIs[1] Rn
37926 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37927 GIM_CheckIsSafeToFold, /*InsnID*/1,
37928 // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
37930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37931 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
37932 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37933 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37934 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37935 GIR_EraseFromParent, /*InsnID*/0,
37936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37937 // GIR_Coverage, 2132,
37938 GIR_Done,
37939 // Label 1862: @102121
37940 GIM_Try, /*On fail goto*//*Label 1863*/ 102164, // Rule ID 1886 //
37941 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
37942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
37943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
37944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
37945 // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
37946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
37947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
37949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
37950 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37951 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37952 GIR_EraseFromParent, /*InsnID*/0,
37953 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37954 // GIR_Coverage, 1886,
37955 GIR_Done,
37956 // Label 1863: @102164
37957 GIM_Try, /*On fail goto*//*Label 1864*/ 102207, // Rule ID 2130 //
37958 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
37959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
37960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
37961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
37962 // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
37964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
37965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
37966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
37967 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37968 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37969 GIR_EraseFromParent, /*InsnID*/0,
37970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37971 // GIR_Coverage, 2130,
37972 GIR_Done,
37973 // Label 1864: @102207
37974 GIM_Reject,
37975 // Label 1858: @102208
37976 GIM_Reject,
37977 // Label 1849: @102209
37978 GIM_Try, /*On fail goto*//*Label 1865*/ 102260, // Rule ID 836 //
37979 GIM_CheckFeatures, GIFBS_HasNEON,
37980 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
37981 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
37982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
37983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
37984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
37985 // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
37986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv1i64,
37987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
37988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
37989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
37990 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
37991 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
37992 GIR_EraseFromParent, /*InsnID*/0,
37993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
37994 // GIR_Coverage, 836,
37995 GIR_Done,
37996 // Label 1865: @102260
37997 GIM_Reject,
37998 // Label 1850: @102261
37999 GIM_Try, /*On fail goto*//*Label 1866*/ 102457,
38000 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38001 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
38002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38003 GIM_Try, /*On fail goto*//*Label 1867*/ 102346, // Rule ID 5617 //
38004 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38005 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38006 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38007 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38008 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38009 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38010 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38011 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38012 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38014 GIM_CheckIsSafeToFold, /*InsnID*/1,
38015 // (saddsat:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2210:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
38017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
38019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38021 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38022 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38023 GIR_EraseFromParent, /*InsnID*/0,
38024 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38025 // GIR_Coverage, 5617,
38026 GIR_Done,
38027 // Label 1867: @102346
38028 GIM_Try, /*On fail goto*//*Label 1868*/ 102417, // Rule ID 2420 //
38029 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38031 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38032 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38033 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38034 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38035 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38036 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38037 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38038 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38039 GIM_CheckIsSafeToFold, /*InsnID*/1,
38040 // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2210:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
38042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38046 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38047 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38048 GIR_EraseFromParent, /*InsnID*/0,
38049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38050 // GIR_Coverage, 2420,
38051 GIR_Done,
38052 // Label 1868: @102417
38053 GIM_Try, /*On fail goto*//*Label 1869*/ 102456, // Rule ID 831 //
38054 GIM_CheckFeatures, GIFBS_HasNEON,
38055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38057 // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i32,
38059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38062 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38063 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38064 GIR_EraseFromParent, /*InsnID*/0,
38065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38066 // GIR_Coverage, 831,
38067 GIR_Done,
38068 // Label 1869: @102456
38069 GIM_Reject,
38070 // Label 1866: @102457
38071 GIM_Reject,
38072 // Label 1851: @102458
38073 GIM_Try, /*On fail goto*//*Label 1870*/ 102654,
38074 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
38075 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
38076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38077 GIM_Try, /*On fail goto*//*Label 1871*/ 102543, // Rule ID 5637 //
38078 GIM_CheckFeatures, GIFBS_HasNEON,
38079 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38080 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38081 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38082 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
38083 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38084 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38085 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38086 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38088 GIM_CheckIsSafeToFold, /*InsnID*/1,
38089 // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 2205:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
38091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
38093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38095 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38096 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38097 GIR_EraseFromParent, /*InsnID*/0,
38098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38099 // GIR_Coverage, 5637,
38100 GIR_Done,
38101 // Label 1871: @102543
38102 GIM_Try, /*On fail goto*//*Label 1872*/ 102614, // Rule ID 2436 //
38103 GIM_CheckFeatures, GIFBS_HasNEON,
38104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38105 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38106 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38107 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38108 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
38109 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38110 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38111 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38112 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38113 GIM_CheckIsSafeToFold, /*InsnID*/1,
38114 // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 2205:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
38116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38120 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38121 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38122 GIR_EraseFromParent, /*InsnID*/0,
38123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38124 // GIR_Coverage, 2436,
38125 GIR_Done,
38126 // Label 1872: @102614
38127 GIM_Try, /*On fail goto*//*Label 1873*/ 102653, // Rule ID 837 //
38128 GIM_CheckFeatures, GIFBS_HasNEON,
38129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38131 // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
38132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i64,
38133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38136 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38137 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38138 GIR_EraseFromParent, /*InsnID*/0,
38139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38140 // GIR_Coverage, 837,
38141 GIR_Done,
38142 // Label 1873: @102653
38143 GIM_Reject,
38144 // Label 1870: @102654
38145 GIM_Reject,
38146 // Label 1852: @102655
38147 GIM_Try, /*On fail goto*//*Label 1874*/ 102851,
38148 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38149 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
38150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38151 GIM_Try, /*On fail goto*//*Label 1875*/ 102740, // Rule ID 5616 //
38152 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38153 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38154 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38155 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38156 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38157 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38158 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38159 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38160 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38162 GIM_CheckIsSafeToFold, /*InsnID*/1,
38163 // (saddsat:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 2210:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38164 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
38165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
38167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38169 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38170 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38171 GIR_EraseFromParent, /*InsnID*/0,
38172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38173 // GIR_Coverage, 5616,
38174 GIR_Done,
38175 // Label 1875: @102740
38176 GIM_Try, /*On fail goto*//*Label 1876*/ 102811, // Rule ID 2419 //
38177 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38179 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38180 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38181 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38182 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38183 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38184 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38185 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38186 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38187 GIM_CheckIsSafeToFold, /*InsnID*/1,
38188 // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 2210:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
38190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38192 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38194 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38195 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38196 GIR_EraseFromParent, /*InsnID*/0,
38197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38198 // GIR_Coverage, 2419,
38199 GIR_Done,
38200 // Label 1876: @102811
38201 GIM_Try, /*On fail goto*//*Label 1877*/ 102850, // Rule ID 830 //
38202 GIM_CheckFeatures, GIFBS_HasNEON,
38203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38205 // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38206 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i16,
38207 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38210 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38211 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38212 GIR_EraseFromParent, /*InsnID*/0,
38213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38214 // GIR_Coverage, 830,
38215 GIR_Done,
38216 // Label 1877: @102850
38217 GIM_Reject,
38218 // Label 1874: @102851
38219 GIM_Reject,
38220 // Label 1853: @102852
38221 GIM_Try, /*On fail goto*//*Label 1878*/ 103263,
38222 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38223 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
38224 GIM_Try, /*On fail goto*//*Label 1879*/ 102937, // Rule ID 5619 //
38225 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38227 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38228 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38229 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38230 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38231 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
38232 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
38233 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38234 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
38235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38236 GIM_CheckIsSafeToFold, /*InsnID*/1,
38237 // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2210:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
38238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
38239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
38241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38243 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38244 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38245 GIR_EraseFromParent, /*InsnID*/0,
38246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38247 // GIR_Coverage, 5619,
38248 GIR_Done,
38249 // Label 1879: @102937
38250 GIM_Try, /*On fail goto*//*Label 1880*/ 103012, // Rule ID 5636 //
38251 GIM_CheckFeatures, GIFBS_HasNEON,
38252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38253 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38254 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38255 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38256 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
38257 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38258 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38259 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38260 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38262 GIM_CheckIsSafeToFold, /*InsnID*/1,
38263 // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 2205:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
38265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
38267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38269 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38270 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38271 GIR_EraseFromParent, /*InsnID*/0,
38272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38273 // GIR_Coverage, 5636,
38274 GIR_Done,
38275 // Label 1880: @103012
38276 GIM_Try, /*On fail goto*//*Label 1881*/ 103087, // Rule ID 2422 //
38277 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38281 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38282 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38283 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38284 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
38285 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
38286 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38287 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
38288 GIM_CheckIsSafeToFold, /*InsnID*/1,
38289 // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2210:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
38290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
38291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38295 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38296 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38297 GIR_EraseFromParent, /*InsnID*/0,
38298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38299 // GIR_Coverage, 2422,
38300 GIR_Done,
38301 // Label 1881: @103087
38302 GIM_Try, /*On fail goto*//*Label 1882*/ 103162, // Rule ID 2435 //
38303 GIM_CheckFeatures, GIFBS_HasNEON,
38304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38306 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38307 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38308 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38309 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
38310 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38311 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
38312 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38313 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38314 GIM_CheckIsSafeToFold, /*InsnID*/1,
38315 // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2205:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
38317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38321 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38322 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38323 GIR_EraseFromParent, /*InsnID*/0,
38324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38325 // GIR_Coverage, 2435,
38326 GIR_Done,
38327 // Label 1882: @103162
38328 GIM_Try, /*On fail goto*//*Label 1883*/ 103205, // Rule ID 833 //
38329 GIM_CheckFeatures, GIFBS_HasNEON,
38330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38333 // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
38334 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i32,
38335 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38336 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38337 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38338 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38339 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38340 GIR_EraseFromParent, /*InsnID*/0,
38341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38342 // GIR_Coverage, 833,
38343 GIR_Done,
38344 // Label 1883: @103205
38345 GIM_Try, /*On fail goto*//*Label 1884*/ 103262, // Rule ID 3508 //
38346 GIM_CheckFeatures, GIFBS_HasMVEInt,
38347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38350 // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
38351 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38352 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38353 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38354 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDs32,
38355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38356 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38358 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38359 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38360 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38361 GIR_EraseFromParent, /*InsnID*/0,
38362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38363 // GIR_Coverage, 3508,
38364 GIR_Done,
38365 // Label 1884: @103262
38366 GIM_Reject,
38367 // Label 1878: @103263
38368 GIM_Reject,
38369 // Label 1854: @103264
38370 GIM_Try, /*On fail goto*//*Label 1885*/ 103315, // Rule ID 834 //
38371 GIM_CheckFeatures, GIFBS_HasNEON,
38372 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38373 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
38374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38377 // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i8,
38379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38382 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38383 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38384 GIR_EraseFromParent, /*InsnID*/0,
38385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38386 // GIR_Coverage, 834,
38387 GIR_Done,
38388 // Label 1885: @103315
38389 GIM_Reject,
38390 // Label 1855: @103316
38391 GIM_Try, /*On fail goto*//*Label 1886*/ 103577,
38392 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38393 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
38394 GIM_Try, /*On fail goto*//*Label 1887*/ 103401, // Rule ID 5618 //
38395 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38397 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38398 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38399 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38400 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38401 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38402 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
38403 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38404 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
38405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38406 GIM_CheckIsSafeToFold, /*InsnID*/1,
38407 // (saddsat:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 2210:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
38408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
38409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
38411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38412 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38413 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38414 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38415 GIR_EraseFromParent, /*InsnID*/0,
38416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38417 // GIR_Coverage, 5618,
38418 GIR_Done,
38419 // Label 1887: @103401
38420 GIM_Try, /*On fail goto*//*Label 1888*/ 103476, // Rule ID 2421 //
38421 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38424 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38425 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38426 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38427 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38428 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38429 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
38430 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38431 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
38432 GIM_CheckIsSafeToFold, /*InsnID*/1,
38433 // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 2210:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
38434 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
38435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38439 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38440 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38441 GIR_EraseFromParent, /*InsnID*/0,
38442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38443 // GIR_Coverage, 2421,
38444 GIR_Done,
38445 // Label 1888: @103476
38446 GIM_Try, /*On fail goto*//*Label 1889*/ 103519, // Rule ID 832 //
38447 GIM_CheckFeatures, GIFBS_HasNEON,
38448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38451 // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
38452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i16,
38453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38456 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38457 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38458 GIR_EraseFromParent, /*InsnID*/0,
38459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38460 // GIR_Coverage, 832,
38461 GIR_Done,
38462 // Label 1889: @103519
38463 GIM_Try, /*On fail goto*//*Label 1890*/ 103576, // Rule ID 3505 //
38464 GIM_CheckFeatures, GIFBS_HasMVEInt,
38465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38468 // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
38469 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38470 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38471 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDs16,
38473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38476 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38477 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38478 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38479 GIR_EraseFromParent, /*InsnID*/0,
38480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38481 // GIR_Coverage, 3505,
38482 GIR_Done,
38483 // Label 1890: @103576
38484 GIM_Reject,
38485 // Label 1886: @103577
38486 GIM_Reject,
38487 // Label 1856: @103578
38488 GIM_Try, /*On fail goto*//*Label 1891*/ 103689,
38489 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38490 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
38491 GIM_Try, /*On fail goto*//*Label 1892*/ 103631, // Rule ID 835 //
38492 GIM_CheckFeatures, GIFBS_HasNEON,
38493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38496 // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
38497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv16i8,
38498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38501 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38502 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38503 GIR_EraseFromParent, /*InsnID*/0,
38504 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38505 // GIR_Coverage, 835,
38506 GIR_Done,
38507 // Label 1892: @103631
38508 GIM_Try, /*On fail goto*//*Label 1893*/ 103688, // Rule ID 3502 //
38509 GIM_CheckFeatures, GIFBS_HasMVEInt,
38510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38513 // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
38514 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38515 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38516 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQADDs8,
38518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38521 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38522 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38523 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38524 GIR_EraseFromParent, /*InsnID*/0,
38525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38526 // GIR_Coverage, 3502,
38527 GIR_Done,
38528 // Label 1893: @103688
38529 GIM_Reject,
38530 // Label 1891: @103689
38531 GIM_Reject,
38532 // Label 1857: @103690
38533 GIM_Reject,
38534 // Label 26: @103691
38535 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 15, /*)*//*default:*//*Label 1902*/ 104306,
38536 /*GILLT_s64*//*Label 1894*/ 103710,
38537 /*GILLT_v2s32*//*Label 1895*/ 103762,
38538 /*GILLT_v2s64*//*Label 1896*/ 103814, 0,
38539 /*GILLT_v4s16*//*Label 1897*/ 103866,
38540 /*GILLT_v4s32*//*Label 1898*/ 103918, 0, 0,
38541 /*GILLT_v8s8*//*Label 1899*/ 104030,
38542 /*GILLT_v8s16*//*Label 1900*/ 104082, 0, 0,
38543 /*GILLT_v16s8*//*Label 1901*/ 104194,
38544 // Label 1894: @103710
38545 GIM_Try, /*On fail goto*//*Label 1903*/ 103761, // Rule ID 1036 //
38546 GIM_CheckFeatures, GIFBS_HasNEON,
38547 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38548 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
38549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38552 // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
38553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv1i64,
38554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38557 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38558 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38559 GIR_EraseFromParent, /*InsnID*/0,
38560 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38561 // GIR_Coverage, 1036,
38562 GIR_Done,
38563 // Label 1903: @103761
38564 GIM_Reject,
38565 // Label 1895: @103762
38566 GIM_Try, /*On fail goto*//*Label 1904*/ 103813, // Rule ID 1031 //
38567 GIM_CheckFeatures, GIFBS_HasNEON,
38568 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38569 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
38570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38573 // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38574 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i32,
38575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38578 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38579 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38580 GIR_EraseFromParent, /*InsnID*/0,
38581 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38582 // GIR_Coverage, 1031,
38583 GIR_Done,
38584 // Label 1904: @103813
38585 GIM_Reject,
38586 // Label 1896: @103814
38587 GIM_Try, /*On fail goto*//*Label 1905*/ 103865, // Rule ID 1037 //
38588 GIM_CheckFeatures, GIFBS_HasNEON,
38589 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
38590 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
38591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38594 // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
38595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i64,
38596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38599 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38600 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38601 GIR_EraseFromParent, /*InsnID*/0,
38602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38603 // GIR_Coverage, 1037,
38604 GIR_Done,
38605 // Label 1905: @103865
38606 GIM_Reject,
38607 // Label 1897: @103866
38608 GIM_Try, /*On fail goto*//*Label 1906*/ 103917, // Rule ID 1030 //
38609 GIM_CheckFeatures, GIFBS_HasNEON,
38610 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
38611 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
38612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38615 // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i16,
38617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38620 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38621 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38622 GIR_EraseFromParent, /*InsnID*/0,
38623 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38624 // GIR_Coverage, 1030,
38625 GIR_Done,
38626 // Label 1906: @103917
38627 GIM_Reject,
38628 // Label 1898: @103918
38629 GIM_Try, /*On fail goto*//*Label 1907*/ 104029,
38630 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
38631 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
38632 GIM_Try, /*On fail goto*//*Label 1908*/ 103971, // Rule ID 1033 //
38633 GIM_CheckFeatures, GIFBS_HasNEON,
38634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38637 // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
38638 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i32,
38639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38642 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38643 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38644 GIR_EraseFromParent, /*InsnID*/0,
38645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38646 // GIR_Coverage, 1033,
38647 GIR_Done,
38648 // Label 1908: @103971
38649 GIM_Try, /*On fail goto*//*Label 1909*/ 104028, // Rule ID 3535 //
38650 GIM_CheckFeatures, GIFBS_HasMVEInt,
38651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38654 // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
38655 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38656 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38657 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBu32,
38659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38662 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38663 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38664 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38665 GIR_EraseFromParent, /*InsnID*/0,
38666 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38667 // GIR_Coverage, 3535,
38668 GIR_Done,
38669 // Label 1909: @104028
38670 GIM_Reject,
38671 // Label 1907: @104029
38672 GIM_Reject,
38673 // Label 1899: @104030
38674 GIM_Try, /*On fail goto*//*Label 1910*/ 104081, // Rule ID 1034 //
38675 GIM_CheckFeatures, GIFBS_HasNEON,
38676 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
38677 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
38678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38681 // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i8,
38683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38686 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38687 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38688 GIR_EraseFromParent, /*InsnID*/0,
38689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38690 // GIR_Coverage, 1034,
38691 GIR_Done,
38692 // Label 1910: @104081
38693 GIM_Reject,
38694 // Label 1900: @104082
38695 GIM_Try, /*On fail goto*//*Label 1911*/ 104193,
38696 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
38697 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
38698 GIM_Try, /*On fail goto*//*Label 1912*/ 104135, // Rule ID 1032 //
38699 GIM_CheckFeatures, GIFBS_HasNEON,
38700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38703 // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
38704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i16,
38705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38708 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38709 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38710 GIR_EraseFromParent, /*InsnID*/0,
38711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38712 // GIR_Coverage, 1032,
38713 GIR_Done,
38714 // Label 1912: @104135
38715 GIM_Try, /*On fail goto*//*Label 1913*/ 104192, // Rule ID 3532 //
38716 GIM_CheckFeatures, GIFBS_HasMVEInt,
38717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38718 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38720 // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
38721 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38722 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38723 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBu16,
38725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38728 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38729 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38730 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38731 GIR_EraseFromParent, /*InsnID*/0,
38732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38733 // GIR_Coverage, 3532,
38734 GIR_Done,
38735 // Label 1913: @104192
38736 GIM_Reject,
38737 // Label 1911: @104193
38738 GIM_Reject,
38739 // Label 1901: @104194
38740 GIM_Try, /*On fail goto*//*Label 1914*/ 104305,
38741 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
38742 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
38743 GIM_Try, /*On fail goto*//*Label 1915*/ 104247, // Rule ID 1035 //
38744 GIM_CheckFeatures, GIFBS_HasNEON,
38745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38748 // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
38749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv16i8,
38750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38753 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38754 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38755 GIR_EraseFromParent, /*InsnID*/0,
38756 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38757 // GIR_Coverage, 1035,
38758 GIR_Done,
38759 // Label 1915: @104247
38760 GIM_Try, /*On fail goto*//*Label 1916*/ 104304, // Rule ID 3529 //
38761 GIM_CheckFeatures, GIFBS_HasMVEInt,
38762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
38763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
38764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
38765 // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
38766 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38767 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
38768 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
38769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBu8,
38770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
38771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
38772 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
38773 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
38774 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38775 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
38776 GIR_EraseFromParent, /*InsnID*/0,
38777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38778 // GIR_Coverage, 3529,
38779 GIR_Done,
38780 // Label 1916: @104304
38781 GIM_Reject,
38782 // Label 1914: @104305
38783 GIM_Reject,
38784 // Label 1902: @104306
38785 GIM_Reject,
38786 // Label 27: @104307
38787 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 1926*/ 105578,
38788 /*GILLT_s32*//*Label 1917*/ 104327,
38789 /*GILLT_s64*//*Label 1918*/ 104547,
38790 /*GILLT_v2s32*//*Label 1919*/ 104599,
38791 /*GILLT_v2s64*//*Label 1920*/ 104721, 0,
38792 /*GILLT_v4s16*//*Label 1921*/ 104843,
38793 /*GILLT_v4s32*//*Label 1922*/ 104965, 0, 0,
38794 /*GILLT_v8s8*//*Label 1923*/ 105227,
38795 /*GILLT_v8s16*//*Label 1924*/ 105279, 0, 0,
38796 /*GILLT_v16s8*//*Label 1925*/ 105466,
38797 // Label 1917: @104327
38798 GIM_Try, /*On fail goto*//*Label 1927*/ 104546,
38799 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
38800 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
38801 GIM_Try, /*On fail goto*//*Label 1928*/ 104398, // Rule ID 1889 //
38802 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
38803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
38804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38805 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38806 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
38807 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38808 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38809 // MIs[1] Rn
38810 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
38811 GIM_CheckIsSafeToFold, /*InsnID*/1,
38812 // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
38813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
38814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
38817 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38818 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38819 GIR_EraseFromParent, /*InsnID*/0,
38820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38821 // GIR_Coverage, 1889,
38822 GIR_Done,
38823 // Label 1928: @104398
38824 GIM_Try, /*On fail goto*//*Label 1929*/ 104459, // Rule ID 2133 //
38825 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
38826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38828 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38829 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SADDSAT,
38830 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38831 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38832 // MIs[1] Rn
38833 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
38834 GIM_CheckIsSafeToFold, /*InsnID*/1,
38835 // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
38836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
38837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
38840 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38841 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38842 GIR_EraseFromParent, /*InsnID*/0,
38843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38844 // GIR_Coverage, 2133,
38845 GIR_Done,
38846 // Label 1929: @104459
38847 GIM_Try, /*On fail goto*//*Label 1930*/ 104502, // Rule ID 1887 //
38848 GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
38849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
38850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
38851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
38852 // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
38853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
38854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
38856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
38857 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38858 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38859 GIR_EraseFromParent, /*InsnID*/0,
38860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38861 // GIR_Coverage, 1887,
38862 GIR_Done,
38863 // Label 1930: @104502
38864 GIM_Try, /*On fail goto*//*Label 1931*/ 104545, // Rule ID 2131 //
38865 GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
38866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
38867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
38868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
38869 // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
38870 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
38871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
38872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
38873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
38874 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38875 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38876 GIR_EraseFromParent, /*InsnID*/0,
38877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38878 // GIR_Coverage, 2131,
38879 GIR_Done,
38880 // Label 1931: @104545
38881 GIM_Reject,
38882 // Label 1927: @104546
38883 GIM_Reject,
38884 // Label 1918: @104547
38885 GIM_Try, /*On fail goto*//*Label 1932*/ 104598, // Rule ID 1028 //
38886 GIM_CheckFeatures, GIFBS_HasNEON,
38887 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
38888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
38889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38892 // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
38893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv1i64,
38894 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38897 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38898 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38899 GIR_EraseFromParent, /*InsnID*/0,
38900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38901 // GIR_Coverage, 1028,
38902 GIR_Done,
38903 // Label 1932: @104598
38904 GIM_Reject,
38905 // Label 1919: @104599
38906 GIM_Try, /*On fail goto*//*Label 1933*/ 104720,
38907 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
38908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
38909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
38910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
38911 GIM_Try, /*On fail goto*//*Label 1934*/ 104684, // Rule ID 2428 //
38912 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
38913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38914 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38915 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38916 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
38917 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38918 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38919 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38920 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38921 GIM_CheckIsSafeToFold, /*InsnID*/1,
38922 // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2210:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv2i32,
38924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38928 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38929 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38930 GIR_EraseFromParent, /*InsnID*/0,
38931 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38932 // GIR_Coverage, 2428,
38933 GIR_Done,
38934 // Label 1934: @104684
38935 GIM_Try, /*On fail goto*//*Label 1935*/ 104719, // Rule ID 1023 //
38936 GIM_CheckFeatures, GIFBS_HasNEON,
38937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38938 // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i32,
38940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38942 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38943 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38944 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38945 GIR_EraseFromParent, /*InsnID*/0,
38946 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38947 // GIR_Coverage, 1023,
38948 GIR_Done,
38949 // Label 1935: @104719
38950 GIM_Reject,
38951 // Label 1933: @104720
38952 GIM_Reject,
38953 // Label 1920: @104721
38954 GIM_Try, /*On fail goto*//*Label 1936*/ 104842,
38955 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
38956 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
38957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
38958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
38959 GIM_Try, /*On fail goto*//*Label 1937*/ 104806, // Rule ID 2443 //
38960 GIM_CheckFeatures, GIFBS_HasNEON,
38961 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38962 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
38963 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
38964 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
38965 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38966 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
38967 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
38968 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
38969 GIM_CheckIsSafeToFold, /*InsnID*/1,
38970 // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 2205:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv2i64,
38972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
38974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
38975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
38976 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38977 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38978 GIR_EraseFromParent, /*InsnID*/0,
38979 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38980 // GIR_Coverage, 2443,
38981 GIR_Done,
38982 // Label 1937: @104806
38983 GIM_Try, /*On fail goto*//*Label 1938*/ 104841, // Rule ID 1029 //
38984 GIM_CheckFeatures, GIFBS_HasNEON,
38985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
38986 // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
38987 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i64,
38988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
38989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
38990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
38991 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
38992 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
38993 GIR_EraseFromParent, /*InsnID*/0,
38994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
38995 // GIR_Coverage, 1029,
38996 GIR_Done,
38997 // Label 1938: @104841
38998 GIM_Reject,
38999 // Label 1936: @104842
39000 GIM_Reject,
39001 // Label 1921: @104843
39002 GIM_Try, /*On fail goto*//*Label 1939*/ 104964,
39003 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39004 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39007 GIM_Try, /*On fail goto*//*Label 1940*/ 104928, // Rule ID 2427 //
39008 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
39009 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39010 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39011 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39012 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
39013 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39014 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39015 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39016 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
39017 GIM_CheckIsSafeToFold, /*InsnID*/1,
39018 // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 2210:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39019 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i16,
39020 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39022 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39024 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39025 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39026 GIR_EraseFromParent, /*InsnID*/0,
39027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39028 // GIR_Coverage, 2427,
39029 GIR_Done,
39030 // Label 1940: @104928
39031 GIM_Try, /*On fail goto*//*Label 1941*/ 104963, // Rule ID 1022 //
39032 GIM_CheckFeatures, GIFBS_HasNEON,
39033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39034 // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i16,
39036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39039 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39040 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39041 GIR_EraseFromParent, /*InsnID*/0,
39042 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39043 // GIR_Coverage, 1022,
39044 GIR_Done,
39045 // Label 1941: @104963
39046 GIM_Reject,
39047 // Label 1939: @104964
39048 GIM_Reject,
39049 // Label 1922: @104965
39050 GIM_Try, /*On fail goto*//*Label 1942*/ 105226,
39051 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39052 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39053 GIM_Try, /*On fail goto*//*Label 1943*/ 105050, // Rule ID 2430 //
39054 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
39055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39057 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39058 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39059 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39060 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
39061 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
39062 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
39063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
39065 GIM_CheckIsSafeToFold, /*InsnID*/1,
39066 // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2210:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39067 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i32,
39068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39072 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39073 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39074 GIR_EraseFromParent, /*InsnID*/0,
39075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39076 // GIR_Coverage, 2430,
39077 GIR_Done,
39078 // Label 1943: @105050
39079 GIM_Try, /*On fail goto*//*Label 1944*/ 105125, // Rule ID 2442 //
39080 GIM_CheckFeatures, GIFBS_HasNEON,
39081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39083 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39084 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39085 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39086 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
39087 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39088 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39089 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39090 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
39091 GIM_CheckIsSafeToFold, /*InsnID*/1,
39092 // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 2205:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39093 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv4i32,
39094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39095 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39096 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39098 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39099 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39100 GIR_EraseFromParent, /*InsnID*/0,
39101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39102 // GIR_Coverage, 2442,
39103 GIR_Done,
39104 // Label 1944: @105125
39105 GIM_Try, /*On fail goto*//*Label 1945*/ 105168, // Rule ID 1025 //
39106 GIM_CheckFeatures, GIFBS_HasNEON,
39107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39110 // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i32,
39112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39115 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39116 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39117 GIR_EraseFromParent, /*InsnID*/0,
39118 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39119 // GIR_Coverage, 1025,
39120 GIR_Done,
39121 // Label 1945: @105168
39122 GIM_Try, /*On fail goto*//*Label 1946*/ 105225, // Rule ID 3526 //
39123 GIM_CheckFeatures, GIFBS_HasMVEInt,
39124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39127 // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39128 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39129 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39130 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBs32,
39132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39134 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39135 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39136 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39137 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39138 GIR_EraseFromParent, /*InsnID*/0,
39139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39140 // GIR_Coverage, 3526,
39141 GIR_Done,
39142 // Label 1946: @105225
39143 GIM_Reject,
39144 // Label 1942: @105226
39145 GIM_Reject,
39146 // Label 1923: @105227
39147 GIM_Try, /*On fail goto*//*Label 1947*/ 105278, // Rule ID 1026 //
39148 GIM_CheckFeatures, GIFBS_HasNEON,
39149 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
39150 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
39151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39154 // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i8,
39156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39159 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39160 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39161 GIR_EraseFromParent, /*InsnID*/0,
39162 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39163 // GIR_Coverage, 1026,
39164 GIR_Done,
39165 // Label 1947: @105278
39166 GIM_Reject,
39167 // Label 1924: @105279
39168 GIM_Try, /*On fail goto*//*Label 1948*/ 105465,
39169 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39170 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39171 GIM_Try, /*On fail goto*//*Label 1949*/ 105364, // Rule ID 2429 //
39172 GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
39173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39175 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39176 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
39177 GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39178 GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
39179 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
39180 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
39181 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39182 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
39183 GIM_CheckIsSafeToFold, /*InsnID*/1,
39184 // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 2210:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv8i16,
39186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39190 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39191 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39192 GIR_EraseFromParent, /*InsnID*/0,
39193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39194 // GIR_Coverage, 2429,
39195 GIR_Done,
39196 // Label 1949: @105364
39197 GIM_Try, /*On fail goto*//*Label 1950*/ 105407, // Rule ID 1024 //
39198 GIM_CheckFeatures, GIFBS_HasNEON,
39199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39202 // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i16,
39204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39207 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39208 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39209 GIR_EraseFromParent, /*InsnID*/0,
39210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39211 // GIR_Coverage, 1024,
39212 GIR_Done,
39213 // Label 1950: @105407
39214 GIM_Try, /*On fail goto*//*Label 1951*/ 105464, // Rule ID 3523 //
39215 GIM_CheckFeatures, GIFBS_HasMVEInt,
39216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39219 // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39220 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39221 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39222 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBs16,
39224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39225 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39227 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39228 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39229 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39230 GIR_EraseFromParent, /*InsnID*/0,
39231 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39232 // GIR_Coverage, 3523,
39233 GIR_Done,
39234 // Label 1951: @105464
39235 GIM_Reject,
39236 // Label 1948: @105465
39237 GIM_Reject,
39238 // Label 1925: @105466
39239 GIM_Try, /*On fail goto*//*Label 1952*/ 105577,
39240 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
39241 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
39242 GIM_Try, /*On fail goto*//*Label 1953*/ 105519, // Rule ID 1027 //
39243 GIM_CheckFeatures, GIFBS_HasNEON,
39244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39247 // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39248 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv16i8,
39249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39252 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39253 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39254 GIR_EraseFromParent, /*InsnID*/0,
39255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39256 // GIR_Coverage, 1027,
39257 GIR_Done,
39258 // Label 1953: @105519
39259 GIM_Try, /*On fail goto*//*Label 1954*/ 105576, // Rule ID 3520 //
39260 GIM_CheckFeatures, GIFBS_HasMVEInt,
39261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39264 // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39265 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39267 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VQSUBs8,
39269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39272 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39273 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39274 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39275 GIR_EraseFromParent, /*InsnID*/0,
39276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39277 // GIR_Coverage, 3520,
39278 GIR_Done,
39279 // Label 1954: @105576
39280 GIM_Reject,
39281 // Label 1952: @105577
39282 GIM_Reject,
39283 // Label 1926: @105578
39284 GIM_Reject,
39285 // Label 28: @105579
39286 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1962*/ 107715,
39287 /*GILLT_s16*//*Label 1955*/ 105597,
39288 /*GILLT_s32*//*Label 1956*/ 105649,
39289 /*GILLT_s64*//*Label 1957*/ 107068,
39290 /*GILLT_v2s32*//*Label 1958*/ 107120, 0, 0,
39291 /*GILLT_v4s16*//*Label 1959*/ 107172,
39292 /*GILLT_v4s32*//*Label 1960*/ 107355, 0, 0, 0,
39293 /*GILLT_v8s16*//*Label 1961*/ 107467,
39294 // Label 1955: @105597
39295 GIM_Try, /*On fail goto*//*Label 1963*/ 105648, // Rule ID 628 //
39296 GIM_CheckFeatures, GIFBS_HasFullFP16,
39297 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
39298 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
39299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
39300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
39301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
39302 // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDH,
39304 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
39305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
39306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
39307 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39308 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39309 GIR_EraseFromParent, /*InsnID*/0,
39310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39311 // GIR_Coverage, 628,
39312 GIR_Done,
39313 // Label 1963: @105648
39314 GIM_Reject,
39315 // Label 1956: @105649
39316 GIM_Try, /*On fail goto*//*Label 1964*/ 107067,
39317 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
39318 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
39319 GIM_Try, /*On fail goto*//*Label 1965*/ 105949, // Rule ID 5714 //
39320 GIM_CheckFeatures, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
39321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
39322 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39323 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39324 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39325 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39326 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39327 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39329 GIM_CheckIsSafeToFold, /*InsnID*/1,
39330 // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39331 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39332 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39333 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39334 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39335 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39336 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39337 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39338 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39339 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
39340 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
39341 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
39342 GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39343 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
39344 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
39345 GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
39346 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
39347 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
39348 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
39349 GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39350 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
39351 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
39352 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
39353 GIR_AddImm, /*InsnID*/9, /*Imm*/17,
39354 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
39355 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
39356 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
39357 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39358 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
39359 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39360 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
39361 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
39362 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
39363 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
39364 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39365 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
39366 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
39367 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
39368 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
39369 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
39370 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
39371 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
39372 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39373 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
39374 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39375 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
39376 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
39377 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
39378 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39379 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39380 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
39381 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
39382 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
39383 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
39384 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
39385 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
39386 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
39387 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMLAfd,
39388 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
39389 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
39390 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
39391 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
39392 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
39393 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39394 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39395 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
39396 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
39397 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
39398 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
39399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
39400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
39401 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
39402 GIR_EraseFromParent, /*InsnID*/0,
39403 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
39404 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
39405 // GIR_Coverage, 5714,
39406 GIR_Done,
39407 // Label 1965: @105949
39408 GIM_Try, /*On fail goto*//*Label 1966*/ 106239, // Rule ID 5715 //
39409 GIM_CheckFeatures, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
39410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
39411 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39412 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39413 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39414 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39415 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39416 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39417 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39418 GIM_CheckIsSafeToFold, /*InsnID*/1,
39419 // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39420 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39421 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39422 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39423 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39424 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39425 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39426 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39427 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39428 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
39429 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
39430 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
39431 GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39432 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
39433 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
39434 GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
39435 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
39436 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
39437 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
39438 GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39439 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
39440 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
39441 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
39442 GIR_AddImm, /*InsnID*/9, /*Imm*/17,
39443 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
39444 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
39445 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
39446 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39447 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
39448 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39449 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
39450 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
39451 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
39452 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
39453 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39454 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
39455 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
39456 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
39457 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
39458 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
39459 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
39460 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
39461 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39462 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
39463 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39464 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
39465 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
39466 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
39467 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39468 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39469 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
39470 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
39471 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
39472 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
39473 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
39474 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
39475 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
39476 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VFMAfd,
39477 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
39478 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
39479 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
39480 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
39481 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
39482 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39483 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39484 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
39485 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
39486 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
39487 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
39488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
39489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
39490 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
39491 GIR_EraseFromParent, /*InsnID*/0,
39492 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
39493 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
39494 // GIR_Coverage, 5715,
39495 GIR_Done,
39496 // Label 1966: @106239
39497 GIM_Try, /*On fail goto*//*Label 1967*/ 106529, // Rule ID 2615 //
39498 GIM_CheckFeatures, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
39499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
39500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39501 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39502 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39503 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39504 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39505 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39506 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39507 GIM_CheckIsSafeToFold, /*InsnID*/1,
39508 // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39509 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39510 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39511 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39512 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39513 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39514 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39515 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39516 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39517 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
39518 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
39519 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
39520 GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39521 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
39522 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
39523 GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
39524 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
39525 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
39526 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
39527 GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39528 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
39529 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
39530 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
39531 GIR_AddImm, /*InsnID*/9, /*Imm*/17,
39532 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
39533 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
39534 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
39535 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39536 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
39537 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39538 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
39539 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
39540 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
39541 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
39542 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39543 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
39544 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
39545 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
39546 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
39547 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
39548 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
39549 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
39550 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39551 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
39552 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39553 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
39554 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
39555 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
39556 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39557 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39558 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
39559 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
39560 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
39561 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
39562 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
39563 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
39564 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
39565 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMLAfd,
39566 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
39567 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
39568 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
39569 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
39570 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
39571 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39572 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39573 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
39574 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
39575 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
39576 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
39577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
39578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
39579 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
39580 GIR_EraseFromParent, /*InsnID*/0,
39581 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
39582 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
39583 // GIR_Coverage, 2615,
39584 GIR_Done,
39585 // Label 1967: @106529
39586 GIM_Try, /*On fail goto*//*Label 1968*/ 106819, // Rule ID 2617 //
39587 GIM_CheckFeatures, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
39588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
39589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39590 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39591 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39592 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39593 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
39594 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39595 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39596 GIM_CheckIsSafeToFold, /*InsnID*/1,
39597 // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39598 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39599 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39600 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39601 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39602 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39603 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39604 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39605 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39606 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
39607 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
39608 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
39609 GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39610 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
39611 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
39612 GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
39613 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
39614 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
39615 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
39616 GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39617 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
39618 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
39619 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
39620 GIR_AddImm, /*InsnID*/9, /*Imm*/17,
39621 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
39622 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
39623 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
39624 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39625 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
39626 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39627 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
39628 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
39629 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
39630 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
39631 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39632 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
39633 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
39634 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
39635 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
39636 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
39637 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
39638 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
39639 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39640 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
39641 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39642 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
39643 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
39644 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
39645 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39646 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39647 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
39648 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
39649 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
39650 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
39651 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
39652 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
39653 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
39654 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VFMAfd,
39655 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
39656 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
39657 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
39658 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
39659 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
39660 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39661 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39662 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
39663 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
39664 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
39665 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
39666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
39667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
39668 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
39669 GIR_EraseFromParent, /*InsnID*/0,
39670 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
39671 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
39672 // GIR_Coverage, 2617,
39673 GIR_Done,
39674 // Label 1968: @106819
39675 GIM_Try, /*On fail goto*//*Label 1969*/ 106862, // Rule ID 627 //
39676 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
39677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
39678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39680 // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDS,
39682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
39683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
39684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
39685 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39686 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39687 GIR_EraseFromParent, /*InsnID*/0,
39688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39689 // GIR_Coverage, 627,
39690 GIR_Done,
39691 // Label 1969: @106862
39692 GIM_Try, /*On fail goto*//*Label 1970*/ 107066, // Rule ID 2612 //
39693 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
39694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
39695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
39696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
39697 // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39698 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39699 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39700 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39701 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39702 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39703 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39704 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39705 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39706 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39707 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
39708 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39709 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
39710 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
39711 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
39712 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
39713 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39714 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
39715 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
39716 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
39717 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
39718 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
39719 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
39720 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
39721 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39722 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
39723 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39724 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
39725 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
39726 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
39727 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
39728 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
39729 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
39730 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
39731 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
39732 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
39733 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
39734 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
39735 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
39736 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VADDfd,
39737 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
39738 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
39739 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
39740 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
39741 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39742 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39743 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
39744 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
39745 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
39746 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
39747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
39748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
39749 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
39750 GIR_EraseFromParent, /*InsnID*/0,
39751 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
39752 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
39753 // GIR_Coverage, 2612,
39754 GIR_Done,
39755 // Label 1970: @107066
39756 GIM_Reject,
39757 // Label 1964: @107067
39758 GIM_Reject,
39759 // Label 1957: @107068
39760 GIM_Try, /*On fail goto*//*Label 1971*/ 107119, // Rule ID 626 //
39761 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
39762 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
39763 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
39764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39767 // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD,
39769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
39770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
39771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
39772 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39773 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39774 GIR_EraseFromParent, /*InsnID*/0,
39775 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39776 // GIR_Coverage, 626,
39777 GIR_Done,
39778 // Label 1971: @107119
39779 GIM_Reject,
39780 // Label 1958: @107120
39781 GIM_Try, /*On fail goto*//*Label 1972*/ 107171, // Rule ID 778 //
39782 GIM_CheckFeatures, GIFBS_HasNEON,
39783 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
39784 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
39785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39788 // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfd,
39790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39793 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39794 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39795 GIR_EraseFromParent, /*InsnID*/0,
39796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39797 // GIR_Coverage, 778,
39798 GIR_Done,
39799 // Label 1972: @107171
39800 GIM_Reject,
39801 // Label 1959: @107172
39802 GIM_Try, /*On fail goto*//*Label 1973*/ 107354,
39803 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
39804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
39805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
39806 GIM_Try, /*On fail goto*//*Label 1974*/ 107250, // Rule ID 5457 //
39807 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
39808 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39809 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39810 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
39811 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39812 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39813 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39815 GIM_CheckIsSafeToFold, /*InsnID*/1,
39816 // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39817 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
39818 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
39820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39822 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39823 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39824 GIR_EraseFromParent, /*InsnID*/0,
39825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39826 // GIR_Coverage, 5457,
39827 GIR_Done,
39828 // Label 1974: @107250
39829 GIM_Try, /*On fail goto*//*Label 1975*/ 107314, // Rule ID 959 //
39830 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
39831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39832 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39833 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39834 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
39835 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39836 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39837 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39838 GIM_CheckIsSafeToFold, /*InsnID*/1,
39839 // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
39841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39845 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39846 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39847 GIR_EraseFromParent, /*InsnID*/0,
39848 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39849 // GIR_Coverage, 959,
39850 GIR_Done,
39851 // Label 1975: @107314
39852 GIM_Try, /*On fail goto*//*Label 1976*/ 107353, // Rule ID 780 //
39853 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
39854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
39855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
39856 // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhd,
39858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39861 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39862 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39863 GIR_EraseFromParent, /*InsnID*/0,
39864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39865 // GIR_Coverage, 780,
39866 GIR_Done,
39867 // Label 1976: @107353
39868 GIM_Reject,
39869 // Label 1973: @107354
39870 GIM_Reject,
39871 // Label 1960: @107355
39872 GIM_Try, /*On fail goto*//*Label 1977*/ 107466,
39873 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
39874 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
39875 GIM_Try, /*On fail goto*//*Label 1978*/ 107408, // Rule ID 779 //
39876 GIM_CheckFeatures, GIFBS_HasNEON,
39877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39880 // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfq,
39882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39884 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39885 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39886 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39887 GIR_EraseFromParent, /*InsnID*/0,
39888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39889 // GIR_Coverage, 779,
39890 GIR_Done,
39891 // Label 1978: @107408
39892 GIM_Try, /*On fail goto*//*Label 1979*/ 107465, // Rule ID 3966 //
39893 GIM_CheckFeatures, GIFBS_HasMVEFloat,
39894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39897 // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
39898 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39899 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39900 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf32,
39902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39905 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39906 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39907 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
39908 GIR_EraseFromParent, /*InsnID*/0,
39909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39910 // GIR_Coverage, 3966,
39911 GIR_Done,
39912 // Label 1979: @107465
39913 GIM_Reject,
39914 // Label 1977: @107466
39915 GIM_Reject,
39916 // Label 1961: @107467
39917 GIM_Try, /*On fail goto*//*Label 1980*/ 107714,
39918 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
39919 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
39920 GIM_Try, /*On fail goto*//*Label 1981*/ 107545, // Rule ID 5458 //
39921 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
39922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39923 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39924 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39925 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39926 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
39927 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39928 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39930 GIM_CheckIsSafeToFold, /*InsnID*/1,
39931 // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
39933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
39935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39937 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39938 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39939 GIR_EraseFromParent, /*InsnID*/0,
39940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39941 // GIR_Coverage, 5458,
39942 GIR_Done,
39943 // Label 1981: @107545
39944 GIM_Try, /*On fail goto*//*Label 1982*/ 107613, // Rule ID 960 //
39945 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
39946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39948 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39949 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
39950 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39951 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
39952 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39953 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39954 GIM_CheckIsSafeToFold, /*InsnID*/1,
39955 // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
39957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
39959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39961 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39962 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39963 GIR_EraseFromParent, /*InsnID*/0,
39964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39965 // GIR_Coverage, 960,
39966 GIR_Done,
39967 // Label 1982: @107613
39968 GIM_Try, /*On fail goto*//*Label 1983*/ 107656, // Rule ID 781 //
39969 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
39970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
39971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
39972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
39973 // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhq,
39975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
39976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
39977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
39978 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
39979 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
39980 GIR_EraseFromParent, /*InsnID*/0,
39981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
39982 // GIR_Coverage, 781,
39983 GIR_Done,
39984 // Label 1983: @107656
39985 GIM_Try, /*On fail goto*//*Label 1984*/ 107713, // Rule ID 3969 //
39986 GIM_CheckFeatures, GIFBS_HasMVEFloat,
39987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
39988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
39989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
39990 // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
39991 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39992 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
39993 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
39994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VADDf16,
39995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
39996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
39997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
39998 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
39999 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40000 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40001 GIR_EraseFromParent, /*InsnID*/0,
40002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40003 // GIR_Coverage, 3969,
40004 GIR_Done,
40005 // Label 1984: @107713
40006 GIM_Reject,
40007 // Label 1980: @107714
40008 GIM_Reject,
40009 // Label 1962: @107715
40010 GIM_Reject,
40011 // Label 29: @107716
40012 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 1992*/ 109264,
40013 /*GILLT_s16*//*Label 1985*/ 107734,
40014 /*GILLT_s32*//*Label 1986*/ 107786,
40015 /*GILLT_s64*//*Label 1987*/ 108625,
40016 /*GILLT_v2s32*//*Label 1988*/ 108677, 0, 0,
40017 /*GILLT_v4s16*//*Label 1989*/ 108729,
40018 /*GILLT_v4s32*//*Label 1990*/ 108904, 0, 0, 0,
40019 /*GILLT_v8s16*//*Label 1991*/ 109016,
40020 // Label 1985: @107734
40021 GIM_Try, /*On fail goto*//*Label 1993*/ 107785, // Rule ID 631 //
40022 GIM_CheckFeatures, GIFBS_HasFullFP16,
40023 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
40024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
40025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
40026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
40028 // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBH,
40030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40033 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40034 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40035 GIR_EraseFromParent, /*InsnID*/0,
40036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40037 // GIR_Coverage, 631,
40038 GIR_Done,
40039 // Label 1993: @107785
40040 GIM_Reject,
40041 // Label 1986: @107786
40042 GIM_Try, /*On fail goto*//*Label 1994*/ 108624,
40043 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
40044 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
40045 GIM_Try, /*On fail goto*//*Label 1995*/ 108086, // Rule ID 2616 //
40046 GIM_CheckFeatures, GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
40047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40049 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40050 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40051 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40052 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40053 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40054 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40055 GIM_CheckIsSafeToFold, /*InsnID*/1,
40056 // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40057 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40058 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40059 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40060 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40061 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40062 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40063 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40064 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40065 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40066 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40067 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40068 GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40069 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
40070 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40071 GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
40072 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
40073 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
40074 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40075 GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40076 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
40077 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
40078 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40079 GIR_AddImm, /*InsnID*/9, /*Imm*/17,
40080 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
40081 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
40082 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
40083 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40084 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40085 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40086 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40087 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40088 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40089 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40090 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40091 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40092 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40093 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40094 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40095 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40096 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40097 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40098 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40099 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40100 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40101 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40102 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40103 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40104 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40105 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40106 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40107 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40108 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
40109 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40110 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40111 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40112 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40113 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMLSfd,
40114 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40115 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40116 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40117 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
40118 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40119 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40120 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40121 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40122 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40123 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40124 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40127 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40128 GIR_EraseFromParent, /*InsnID*/0,
40129 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40130 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40131 // GIR_Coverage, 2616,
40132 GIR_Done,
40133 // Label 1995: @108086
40134 GIM_Try, /*On fail goto*//*Label 1996*/ 108376, // Rule ID 2618 //
40135 GIM_CheckFeatures, GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
40136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40138 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40139 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40140 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40141 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40142 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40144 GIM_CheckIsSafeToFold, /*InsnID*/1,
40145 // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40146 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40147 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40148 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40149 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40150 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40151 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40152 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40153 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40154 GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40155 GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40156 GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40157 GIR_BuildMI, /*InsnID*/11, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40158 GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/RegState::Define,
40159 GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40160 GIR_BuildMI, /*InsnID*/10, /*Opcode*/TargetOpcode::COPY,
40161 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/RegState::Define,
40162 GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/10, /*TempRegFlags*/0,
40163 GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
40164 GIR_BuildMI, /*InsnID*/9, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40165 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/RegState::Define,
40166 GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/9, /*TempRegFlags*/0,
40167 GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40168 GIR_AddImm, /*InsnID*/9, /*Imm*/17,
40169 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, ARM::DPR_VFP2RegClassID,
40170 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, ARM::DPR_VFP2RegClassID,
40171 GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, ARM::SPRRegClassID,
40172 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40173 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40174 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40175 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40176 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40177 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40178 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40179 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40180 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40181 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40182 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40183 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40184 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40185 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40186 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40187 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40188 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40189 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40190 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40191 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40192 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40193 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40194 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40195 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40196 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40197 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
40198 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40199 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40200 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40201 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40202 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VFMSfd,
40203 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40204 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40205 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40206 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/8, /*TempRegFlags*/0,
40207 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40208 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40209 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40210 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40211 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40212 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40213 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40216 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40217 GIR_EraseFromParent, /*InsnID*/0,
40218 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40219 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40220 // GIR_Coverage, 2618,
40221 GIR_Done,
40222 // Label 1996: @108376
40223 GIM_Try, /*On fail goto*//*Label 1997*/ 108419, // Rule ID 630 //
40224 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
40225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
40226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40228 // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40229 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBS,
40230 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40233 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40234 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40235 GIR_EraseFromParent, /*InsnID*/0,
40236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40237 // GIR_Coverage, 630,
40238 GIR_Done,
40239 // Label 1997: @108419
40240 GIM_Try, /*On fail goto*//*Label 1998*/ 108623, // Rule ID 2613 //
40241 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
40242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40245 // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40246 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40247 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40248 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40249 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40250 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40251 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40252 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40253 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40254 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40255 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40256 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40257 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40258 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40259 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40260 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40261 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40262 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40263 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40264 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
40265 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40266 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40267 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40268 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40269 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40270 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40271 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40272 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40273 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40274 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40275 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40276 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40277 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40278 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40279 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
40280 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40281 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40282 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40283 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40284 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VSUBfd,
40285 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40286 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40287 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40288 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40289 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40290 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40291 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40292 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40293 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40294 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40295 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40297 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40298 GIR_EraseFromParent, /*InsnID*/0,
40299 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40300 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40301 // GIR_Coverage, 2613,
40302 GIR_Done,
40303 // Label 1998: @108623
40304 GIM_Reject,
40305 // Label 1994: @108624
40306 GIM_Reject,
40307 // Label 1987: @108625
40308 GIM_Try, /*On fail goto*//*Label 1999*/ 108676, // Rule ID 629 //
40309 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
40310 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
40311 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
40312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40315 // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBD,
40317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
40318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
40319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
40320 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40321 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40322 GIR_EraseFromParent, /*InsnID*/0,
40323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40324 // GIR_Coverage, 629,
40325 GIR_Done,
40326 // Label 1999: @108676
40327 GIM_Reject,
40328 // Label 1988: @108677
40329 GIM_Try, /*On fail goto*//*Label 2000*/ 108728, // Rule ID 982 //
40330 GIM_CheckFeatures, GIFBS_HasNEON,
40331 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
40332 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
40333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40336 // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40337 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfd,
40338 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40341 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40342 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40343 GIR_EraseFromParent, /*InsnID*/0,
40344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40345 // GIR_Coverage, 982,
40346 GIR_Done,
40347 // Label 2000: @108728
40348 GIM_Reject,
40349 // Label 1989: @108729
40350 GIM_Try, /*On fail goto*//*Label 2001*/ 108903,
40351 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
40352 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
40353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40355 GIM_Try, /*On fail goto*//*Label 2002*/ 108807, // Rule ID 937 //
40356 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
40357 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40358 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40359 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
40360 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40361 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40362 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40363 GIM_CheckIsSafeToFold, /*InsnID*/1,
40364 // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShd,
40366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40369 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40370 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40371 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40372 GIR_EraseFromParent, /*InsnID*/0,
40373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40374 // GIR_Coverage, 937,
40375 GIR_Done,
40376 // Label 2002: @108807
40377 GIM_Try, /*On fail goto*//*Label 2003*/ 108867, // Rule ID 963 //
40378 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
40379 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40380 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40381 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
40382 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40383 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40384 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40385 GIM_CheckIsSafeToFold, /*InsnID*/1,
40386 // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShd,
40388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40392 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40393 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40394 GIR_EraseFromParent, /*InsnID*/0,
40395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40396 // GIR_Coverage, 963,
40397 GIR_Done,
40398 // Label 2003: @108867
40399 GIM_Try, /*On fail goto*//*Label 2004*/ 108902, // Rule ID 984 //
40400 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
40401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40402 // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhd,
40404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40405 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40407 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40408 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40409 GIR_EraseFromParent, /*InsnID*/0,
40410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40411 // GIR_Coverage, 984,
40412 GIR_Done,
40413 // Label 2004: @108902
40414 GIM_Reject,
40415 // Label 2001: @108903
40416 GIM_Reject,
40417 // Label 1990: @108904
40418 GIM_Try, /*On fail goto*//*Label 2005*/ 109015,
40419 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
40420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
40421 GIM_Try, /*On fail goto*//*Label 2006*/ 108957, // Rule ID 983 //
40422 GIM_CheckFeatures, GIFBS_HasNEON,
40423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40426 // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
40427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfq,
40428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40431 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40432 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40433 GIR_EraseFromParent, /*InsnID*/0,
40434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40435 // GIR_Coverage, 983,
40436 GIR_Done,
40437 // Label 2006: @108957
40438 GIM_Try, /*On fail goto*//*Label 2007*/ 109014, // Rule ID 3972 //
40439 GIM_CheckFeatures, GIFBS_HasMVEFloat,
40440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40443 // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
40444 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40445 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40446 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf32,
40448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40451 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40452 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40453 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40454 GIR_EraseFromParent, /*InsnID*/0,
40455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40456 // GIR_Coverage, 3972,
40457 GIR_Done,
40458 // Label 2007: @109014
40459 GIM_Reject,
40460 // Label 2005: @109015
40461 GIM_Reject,
40462 // Label 1991: @109016
40463 GIM_Try, /*On fail goto*//*Label 2008*/ 109263,
40464 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
40465 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
40466 GIM_Try, /*On fail goto*//*Label 2009*/ 109094, // Rule ID 938 //
40467 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
40468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40470 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40471 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40472 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
40473 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
40474 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40475 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40476 GIM_CheckIsSafeToFold, /*InsnID*/1,
40477 // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
40478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShq,
40479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40483 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40484 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40485 GIR_EraseFromParent, /*InsnID*/0,
40486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40487 // GIR_Coverage, 938,
40488 GIR_Done,
40489 // Label 2009: @109094
40490 GIM_Try, /*On fail goto*//*Label 2010*/ 109162, // Rule ID 964 //
40491 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
40492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40494 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40495 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
40496 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
40497 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
40498 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40499 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40500 GIM_CheckIsSafeToFold, /*InsnID*/1,
40501 // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
40502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShq,
40503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
40505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
40506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
40507 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40508 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40509 GIR_EraseFromParent, /*InsnID*/0,
40510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40511 // GIR_Coverage, 964,
40512 GIR_Done,
40513 // Label 2010: @109162
40514 GIM_Try, /*On fail goto*//*Label 2011*/ 109205, // Rule ID 985 //
40515 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
40516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40519 // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
40520 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhq,
40521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40524 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40525 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40526 GIR_EraseFromParent, /*InsnID*/0,
40527 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40528 // GIR_Coverage, 985,
40529 GIR_Done,
40530 // Label 2011: @109205
40531 GIM_Try, /*On fail goto*//*Label 2012*/ 109262, // Rule ID 3975 //
40532 GIM_CheckFeatures, GIFBS_HasMVEFloat,
40533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40535 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40536 // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
40537 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40538 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40539 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VSUBf16,
40541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40544 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40545 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40547 GIR_EraseFromParent, /*InsnID*/0,
40548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40549 // GIR_Coverage, 3975,
40550 GIR_Done,
40551 // Label 2012: @109262
40552 GIM_Reject,
40553 // Label 2008: @109263
40554 GIM_Reject,
40555 // Label 1992: @109264
40556 GIM_Reject,
40557 // Label 30: @109265
40558 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2020*/ 110193,
40559 /*GILLT_s16*//*Label 2013*/ 109283,
40560 /*GILLT_s32*//*Label 2014*/ 109335,
40561 /*GILLT_s64*//*Label 2015*/ 109706,
40562 /*GILLT_v2s32*//*Label 2016*/ 109865, 0, 0,
40563 /*GILLT_v4s16*//*Label 2017*/ 109917,
40564 /*GILLT_v4s32*//*Label 2018*/ 109969, 0, 0, 0,
40565 /*GILLT_v8s16*//*Label 2019*/ 110081,
40566 // Label 2013: @109283
40567 GIM_Try, /*On fail goto*//*Label 2021*/ 109334, // Rule ID 637 //
40568 GIM_CheckFeatures, GIFBS_HasFullFP16,
40569 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
40570 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
40571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
40572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
40574 // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40575 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULH,
40576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40579 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40580 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40581 GIR_EraseFromParent, /*InsnID*/0,
40582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40583 // GIR_Coverage, 637,
40584 GIR_Done,
40585 // Label 2021: @109334
40586 GIM_Reject,
40587 // Label 2014: @109335
40588 GIM_Try, /*On fail goto*//*Label 2022*/ 109705,
40589 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
40590 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
40591 GIM_Try, /*On fail goto*//*Label 2023*/ 109401, // Rule ID 2263 //
40592 GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
40593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
40594 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40595 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40596 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40597 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40599 GIM_CheckIsSafeToFold, /*InsnID*/1,
40600 // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
40601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
40602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
40604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
40605 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40606 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40607 GIR_EraseFromParent, /*InsnID*/0,
40608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40609 // GIR_Coverage, 2263,
40610 GIR_Done,
40611 // Label 2023: @109401
40612 GIM_Try, /*On fail goto*//*Label 2024*/ 109457, // Rule ID 5583 //
40613 GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
40614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
40615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40616 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40617 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40618 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40619 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40620 GIM_CheckIsSafeToFold, /*InsnID*/1,
40621 // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
40622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
40623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
40625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
40626 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40627 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40628 GIR_EraseFromParent, /*InsnID*/0,
40629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40630 // GIR_Coverage, 5583,
40631 GIR_Done,
40632 // Label 2024: @109457
40633 GIM_Try, /*On fail goto*//*Label 2025*/ 109500, // Rule ID 636 //
40634 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
40635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
40636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40638 // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40639 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULS,
40640 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
40642 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40643 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40644 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40645 GIR_EraseFromParent, /*InsnID*/0,
40646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40647 // GIR_Coverage, 636,
40648 GIR_Done,
40649 // Label 2025: @109500
40650 GIM_Try, /*On fail goto*//*Label 2026*/ 109704, // Rule ID 2614 //
40651 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
40652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
40653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
40654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
40655 // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40656 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40657 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40658 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40659 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40660 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40661 GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40662 GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40663 GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40664 GIR_BuildMI, /*InsnID*/8, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40665 GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/RegState::Define,
40666 GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40667 GIR_BuildMI, /*InsnID*/7, /*Opcode*/TargetOpcode::COPY,
40668 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/RegState::Define,
40669 GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/0,
40670 GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
40671 GIR_BuildMI, /*InsnID*/6, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40672 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/RegState::Define,
40673 GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/6, /*TempRegFlags*/0,
40674 GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
40675 GIR_AddImm, /*InsnID*/6, /*Imm*/17,
40676 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, ARM::DPR_VFP2RegClassID,
40677 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, ARM::DPR_VFP2RegClassID,
40678 GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, ARM::SPRRegClassID,
40679 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40680 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
40681 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40682 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
40683 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
40684 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
40685 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
40686 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
40687 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
40688 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
40689 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
40690 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
40691 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
40692 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
40693 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
40694 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VMULfd,
40695 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
40696 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
40697 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/5, /*TempRegFlags*/0,
40698 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
40699 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40700 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40701 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
40702 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
40703 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
40704 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
40706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
40707 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
40708 GIR_EraseFromParent, /*InsnID*/0,
40709 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
40710 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
40711 // GIR_Coverage, 2614,
40712 GIR_Done,
40713 // Label 2026: @109704
40714 GIM_Reject,
40715 // Label 2022: @109705
40716 GIM_Reject,
40717 // Label 2015: @109706
40718 GIM_Try, /*On fail goto*//*Label 2027*/ 109864,
40719 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
40720 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
40721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40722 GIM_Try, /*On fail goto*//*Label 2028*/ 109772, // Rule ID 2262 //
40723 GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
40724 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40725 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40726 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40727 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40729 GIM_CheckIsSafeToFold, /*InsnID*/1,
40730 // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
40731 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
40732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
40733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
40734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
40735 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40736 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40737 GIR_EraseFromParent, /*InsnID*/0,
40738 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40739 // GIR_Coverage, 2262,
40740 GIR_Done,
40741 // Label 2028: @109772
40742 GIM_Try, /*On fail goto*//*Label 2029*/ 109824, // Rule ID 5582 //
40743 GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
40744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40745 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40746 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40747 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40748 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40749 GIM_CheckIsSafeToFold, /*InsnID*/1,
40750 // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
40751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
40752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
40753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
40754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
40755 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40756 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40757 GIR_EraseFromParent, /*InsnID*/0,
40758 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40759 // GIR_Coverage, 5582,
40760 GIR_Done,
40761 // Label 2029: @109824
40762 GIM_Try, /*On fail goto*//*Label 2030*/ 109863, // Rule ID 635 //
40763 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
40764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40766 // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40767 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULD,
40768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
40769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
40770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
40771 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40772 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40773 GIR_EraseFromParent, /*InsnID*/0,
40774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40775 // GIR_Coverage, 635,
40776 GIR_Done,
40777 // Label 2030: @109863
40778 GIM_Reject,
40779 // Label 2027: @109864
40780 GIM_Reject,
40781 // Label 2016: @109865
40782 GIM_Try, /*On fail goto*//*Label 2031*/ 109916, // Rule ID 857 //
40783 GIM_CheckFeatures, GIFBS_HasNEON,
40784 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
40785 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
40786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40789 // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
40790 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfd,
40791 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40794 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40795 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40796 GIR_EraseFromParent, /*InsnID*/0,
40797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40798 // GIR_Coverage, 857,
40799 GIR_Done,
40800 // Label 2031: @109916
40801 GIM_Reject,
40802 // Label 2017: @109917
40803 GIM_Try, /*On fail goto*//*Label 2032*/ 109968, // Rule ID 859 //
40804 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
40805 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
40806 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
40807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
40808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
40809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
40810 // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
40811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhd,
40812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40815 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40816 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40817 GIR_EraseFromParent, /*InsnID*/0,
40818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40819 // GIR_Coverage, 859,
40820 GIR_Done,
40821 // Label 2032: @109968
40822 GIM_Reject,
40823 // Label 2018: @109969
40824 GIM_Try, /*On fail goto*//*Label 2033*/ 110080,
40825 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
40826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
40827 GIM_Try, /*On fail goto*//*Label 2034*/ 110022, // Rule ID 858 //
40828 GIM_CheckFeatures, GIFBS_HasNEON,
40829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40832 // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
40833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfq,
40834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40837 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40838 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40839 GIR_EraseFromParent, /*InsnID*/0,
40840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40841 // GIR_Coverage, 858,
40842 GIR_Done,
40843 // Label 2034: @110022
40844 GIM_Try, /*On fail goto*//*Label 2035*/ 110079, // Rule ID 3942 //
40845 GIM_CheckFeatures, GIFBS_HasMVEFloat,
40846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40849 // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
40850 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40851 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40852 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf32,
40854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40857 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40858 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40859 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40860 GIR_EraseFromParent, /*InsnID*/0,
40861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40862 // GIR_Coverage, 3942,
40863 GIR_Done,
40864 // Label 2035: @110079
40865 GIM_Reject,
40866 // Label 2033: @110080
40867 GIM_Reject,
40868 // Label 2019: @110081
40869 GIM_Try, /*On fail goto*//*Label 2036*/ 110192,
40870 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
40871 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
40872 GIM_Try, /*On fail goto*//*Label 2037*/ 110134, // Rule ID 860 //
40873 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
40874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
40875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
40876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
40877 // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
40878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhq,
40879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
40880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
40881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
40882 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40883 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40884 GIR_EraseFromParent, /*InsnID*/0,
40885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40886 // GIR_Coverage, 860,
40887 GIR_Done,
40888 // Label 2037: @110134
40889 GIM_Try, /*On fail goto*//*Label 2038*/ 110191, // Rule ID 3945 //
40890 GIM_CheckFeatures, GIFBS_HasMVEFloat,
40891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
40892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
40893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
40894 // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
40895 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40896 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
40897 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
40898 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMULf16,
40899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
40900 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
40901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
40902 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
40903 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40904 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
40905 GIR_EraseFromParent, /*InsnID*/0,
40906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40907 // GIR_Coverage, 3945,
40908 GIR_Done,
40909 // Label 2038: @110191
40910 GIM_Reject,
40911 // Label 2036: @110192
40912 GIM_Reject,
40913 // Label 2020: @110193
40914 GIM_Reject,
40915 // Label 31: @110194
40916 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2046*/ 111893,
40917 /*GILLT_s16*//*Label 2039*/ 110212,
40918 /*GILLT_s32*//*Label 2040*/ 110605,
40919 /*GILLT_s64*//*Label 2041*/ 110998,
40920 /*GILLT_v2s32*//*Label 2042*/ 111391, 0, 0,
40921 /*GILLT_v4s16*//*Label 2043*/ 111578,
40922 /*GILLT_v4s32*//*Label 2044*/ 111642, 0, 0, 0,
40923 /*GILLT_v8s16*//*Label 2045*/ 111829,
40924 // Label 2039: @110212
40925 GIM_Try, /*On fail goto*//*Label 2047*/ 110604,
40926 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
40927 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
40928 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
40929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
40930 GIM_Try, /*On fail goto*//*Label 2048*/ 110303, // Rule ID 2359 //
40931 GIM_CheckFeatures, GIFBS_HasFullFP16,
40932 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40933 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40934 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40935 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
40937 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
40938 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
40939 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40940 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40941 GIM_CheckIsSafeToFold, /*InsnID*/1,
40942 GIM_CheckIsSafeToFold, /*InsnID*/2,
40943 // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
40945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
40947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40949 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40950 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40951 GIR_EraseFromParent, /*InsnID*/0,
40952 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40953 // GIR_Coverage, 2359,
40954 GIR_Done,
40955 // Label 2048: @110303
40956 GIM_Try, /*On fail goto*//*Label 2049*/ 110376, // Rule ID 5591 //
40957 GIM_CheckFeatures, GIFBS_HasFullFP16,
40958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40960 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40961 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40962 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40963 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
40964 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
40965 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40966 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40967 GIM_CheckIsSafeToFold, /*InsnID*/1,
40968 GIM_CheckIsSafeToFold, /*InsnID*/2,
40969 // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
40971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
40973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
40975 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40976 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40977 GIR_EraseFromParent, /*InsnID*/0,
40978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
40979 // GIR_Coverage, 5591,
40980 GIR_Done,
40981 // Label 2049: @110376
40982 GIM_Try, /*On fail goto*//*Label 2050*/ 110436, // Rule ID 2351 //
40983 GIM_CheckFeatures, GIFBS_HasFullFP16,
40984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40985 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
40986 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40987 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
40988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
40989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
40990 GIM_CheckIsSafeToFold, /*InsnID*/1,
40991 // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH,
40993 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
40994 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
40995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
40997 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
40998 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
40999 GIR_EraseFromParent, /*InsnID*/0,
41000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41001 // GIR_Coverage, 2351,
41002 GIR_Done,
41003 // Label 2050: @110436
41004 GIM_Try, /*On fail goto*//*Label 2051*/ 110496, // Rule ID 5588 //
41005 GIM_CheckFeatures, GIFBS_HasFullFP16,
41006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41007 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41008 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41009 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41010 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
41012 GIM_CheckIsSafeToFold, /*InsnID*/1,
41013 // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSH,
41015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41016 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
41017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41019 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41020 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41021 GIR_EraseFromParent, /*InsnID*/0,
41022 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41023 // GIR_Coverage, 5588,
41024 GIR_Done,
41025 // Label 2051: @110496
41026 GIM_Try, /*On fail goto*//*Label 2052*/ 110556, // Rule ID 2364 //
41027 GIM_CheckFeatures, GIFBS_HasFullFP16,
41028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41030 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
41031 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41032 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41033 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41034 GIM_CheckIsSafeToFold, /*InsnID*/1,
41035 // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
41037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
41039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41041 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41042 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41043 GIR_EraseFromParent, /*InsnID*/0,
41044 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41045 // GIR_Coverage, 2364,
41046 GIR_Done,
41047 // Label 2052: @110556
41048 GIM_Try, /*On fail goto*//*Label 2053*/ 110603, // Rule ID 2345 //
41049 GIM_CheckFeatures, GIFBS_HasFullFP16,
41050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41051 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41052 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::HPRRegClassID,
41053 // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAH,
41055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
41057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41059 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41060 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41061 GIR_EraseFromParent, /*InsnID*/0,
41062 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41063 // GIR_Coverage, 2345,
41064 GIR_Done,
41065 // Label 2053: @110603
41066 GIM_Reject,
41067 // Label 2047: @110604
41068 GIM_Reject,
41069 // Label 2040: @110605
41070 GIM_Try, /*On fail goto*//*Label 2054*/ 110997,
41071 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41072 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
41073 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
41074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41075 GIM_Try, /*On fail goto*//*Label 2055*/ 110696, // Rule ID 2358 //
41076 GIM_CheckFeatures, GIFBS_HasVFP4,
41077 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41078 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41079 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41080 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41082 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
41083 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41084 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
41085 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41086 GIM_CheckIsSafeToFold, /*InsnID*/1,
41087 GIM_CheckIsSafeToFold, /*InsnID*/2,
41088 // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
41090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
41092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41094 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41095 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41096 GIR_EraseFromParent, /*InsnID*/0,
41097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41098 // GIR_Coverage, 2358,
41099 GIR_Done,
41100 // Label 2055: @110696
41101 GIM_Try, /*On fail goto*//*Label 2056*/ 110769, // Rule ID 5590 //
41102 GIM_CheckFeatures, GIFBS_HasVFP4,
41103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41104 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41105 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41106 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41107 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41108 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
41109 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41110 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
41111 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41112 GIM_CheckIsSafeToFold, /*InsnID*/1,
41113 GIM_CheckIsSafeToFold, /*InsnID*/2,
41114 // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
41116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
41118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41120 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41121 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41122 GIR_EraseFromParent, /*InsnID*/0,
41123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41124 // GIR_Coverage, 5590,
41125 GIR_Done,
41126 // Label 2056: @110769
41127 GIM_Try, /*On fail goto*//*Label 2057*/ 110829, // Rule ID 2350 //
41128 GIM_CheckFeatures, GIFBS_HasVFP4,
41129 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41130 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41131 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41132 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
41135 GIM_CheckIsSafeToFold, /*InsnID*/1,
41136 // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41137 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
41138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
41140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41142 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41143 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41144 GIR_EraseFromParent, /*InsnID*/0,
41145 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41146 // GIR_Coverage, 2350,
41147 GIR_Done,
41148 // Label 2057: @110829
41149 GIM_Try, /*On fail goto*//*Label 2058*/ 110889, // Rule ID 5587 //
41150 GIM_CheckFeatures, GIFBS_HasVFP4,
41151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41153 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41154 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41155 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
41157 GIM_CheckIsSafeToFold, /*InsnID*/1,
41158 // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
41160 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
41162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41164 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41165 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41166 GIR_EraseFromParent, /*InsnID*/0,
41167 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41168 // GIR_Coverage, 5587,
41169 GIR_Done,
41170 // Label 2058: @110889
41171 GIM_Try, /*On fail goto*//*Label 2059*/ 110949, // Rule ID 2363 //
41172 GIM_CheckFeatures, GIFBS_HasVFP4,
41173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41175 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
41176 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41177 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41178 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41179 GIM_CheckIsSafeToFold, /*InsnID*/1,
41180 // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
41182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
41184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41186 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41187 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41188 GIR_EraseFromParent, /*InsnID*/0,
41189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41190 // GIR_Coverage, 2363,
41191 GIR_Done,
41192 // Label 2059: @110949
41193 GIM_Try, /*On fail goto*//*Label 2060*/ 110996, // Rule ID 2344 //
41194 GIM_CheckFeatures, GIFBS_HasVFP4,
41195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
41198 // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS,
41200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
41202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41204 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41205 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41206 GIR_EraseFromParent, /*InsnID*/0,
41207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41208 // GIR_Coverage, 2344,
41209 GIR_Done,
41210 // Label 2060: @110996
41211 GIM_Reject,
41212 // Label 2054: @110997
41213 GIM_Reject,
41214 // Label 2041: @110998
41215 GIM_Try, /*On fail goto*//*Label 2061*/ 111390,
41216 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41217 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
41218 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
41219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41220 GIM_Try, /*On fail goto*//*Label 2062*/ 111089, // Rule ID 2357 //
41221 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41222 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41223 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41224 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41225 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41227 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
41228 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41229 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
41230 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41231 GIM_CheckIsSafeToFold, /*InsnID*/1,
41232 GIM_CheckIsSafeToFold, /*InsnID*/2,
41233 // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
41235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
41237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
41238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41239 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41240 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41241 GIR_EraseFromParent, /*InsnID*/0,
41242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41243 // GIR_Coverage, 2357,
41244 GIR_Done,
41245 // Label 2062: @111089
41246 GIM_Try, /*On fail goto*//*Label 2063*/ 111162, // Rule ID 5589 //
41247 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41249 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41250 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41251 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41252 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41253 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
41254 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41255 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
41256 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41257 GIM_CheckIsSafeToFold, /*InsnID*/1,
41258 GIM_CheckIsSafeToFold, /*InsnID*/2,
41259 // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
41261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
41263 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
41264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
41265 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41266 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41267 GIR_EraseFromParent, /*InsnID*/0,
41268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41269 // GIR_Coverage, 5589,
41270 GIR_Done,
41271 // Label 2063: @111162
41272 GIM_Try, /*On fail goto*//*Label 2064*/ 111222, // Rule ID 2349 //
41273 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41275 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41276 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41277 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41280 GIM_CheckIsSafeToFold, /*InsnID*/1,
41281 // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41282 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
41283 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
41285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
41286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41287 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41288 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41289 GIR_EraseFromParent, /*InsnID*/0,
41290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41291 // GIR_Coverage, 2349,
41292 GIR_Done,
41293 // Label 2064: @111222
41294 GIM_Try, /*On fail goto*//*Label 2065*/ 111282, // Rule ID 5586 //
41295 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41297 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41298 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41299 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41300 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41302 GIM_CheckIsSafeToFold, /*InsnID*/1,
41303 // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
41305 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41306 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
41307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
41308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
41309 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41310 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41311 GIR_EraseFromParent, /*InsnID*/0,
41312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41313 // GIR_Coverage, 5586,
41314 GIR_Done,
41315 // Label 2065: @111282
41316 GIM_Try, /*On fail goto*//*Label 2066*/ 111342, // Rule ID 2362 //
41317 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41320 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
41321 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41322 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41323 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41324 GIM_CheckIsSafeToFold, /*InsnID*/1,
41325 // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
41327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
41329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41331 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41332 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41333 GIR_EraseFromParent, /*InsnID*/0,
41334 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41335 // GIR_Coverage, 2362,
41336 GIR_Done,
41337 // Label 2066: @111342
41338 GIM_Try, /*On fail goto*//*Label 2067*/ 111389, // Rule ID 2343 //
41339 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41343 // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD,
41345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
41347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41349 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41350 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41351 GIR_EraseFromParent, /*InsnID*/0,
41352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41353 // GIR_Coverage, 2343,
41354 GIR_Done,
41355 // Label 2067: @111389
41356 GIM_Reject,
41357 // Label 2061: @111390
41358 GIM_Reject,
41359 // Label 2042: @111391
41360 GIM_Try, /*On fail goto*//*Label 2068*/ 111577,
41361 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
41362 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
41363 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
41364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41365 GIM_Try, /*On fail goto*//*Label 2069*/ 111469, // Rule ID 2450 //
41366 GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
41367 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41368 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41369 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
41370 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41373 GIM_CheckIsSafeToFold, /*InsnID*/1,
41374 // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
41376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41380 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41381 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41382 GIR_EraseFromParent, /*InsnID*/0,
41383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41384 // GIR_Coverage, 2450,
41385 GIR_Done,
41386 // Label 2069: @111469
41387 GIM_Try, /*On fail goto*//*Label 2070*/ 111529, // Rule ID 5649 //
41388 GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
41389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41390 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41391 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41392 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
41393 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41395 GIM_CheckIsSafeToFold, /*InsnID*/1,
41396 // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41397 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
41398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41399 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
41402 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41403 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41404 GIR_EraseFromParent, /*InsnID*/0,
41405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41406 // GIR_Coverage, 5649,
41407 GIR_Done,
41408 // Label 2070: @111529
41409 GIM_Try, /*On fail goto*//*Label 2071*/ 111576, // Rule ID 2448 //
41410 GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
41411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41414 // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd,
41416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41420 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41421 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41422 GIR_EraseFromParent, /*InsnID*/0,
41423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41424 // GIR_Coverage, 2448,
41425 GIR_Done,
41426 // Label 2071: @111576
41427 GIM_Reject,
41428 // Label 2068: @111577
41429 GIM_Reject,
41430 // Label 2043: @111578
41431 GIM_Try, /*On fail goto*//*Label 2072*/ 111641, // Rule ID 2446 //
41432 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41433 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
41434 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
41435 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
41436 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41440 // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
41442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41446 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41447 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41448 GIR_EraseFromParent, /*InsnID*/0,
41449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41450 // GIR_Coverage, 2446,
41451 GIR_Done,
41452 // Label 2072: @111641
41453 GIM_Reject,
41454 // Label 2044: @111642
41455 GIM_Try, /*On fail goto*//*Label 2073*/ 111828,
41456 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
41457 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
41458 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
41459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41460 GIM_Try, /*On fail goto*//*Label 2074*/ 111720, // Rule ID 2451 //
41461 GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
41462 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41463 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41464 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
41465 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41466 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
41468 GIM_CheckIsSafeToFold, /*InsnID*/1,
41469 // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41470 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
41471 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41475 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41476 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41477 GIR_EraseFromParent, /*InsnID*/0,
41478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41479 // GIR_Coverage, 2451,
41480 GIR_Done,
41481 // Label 2074: @111720
41482 GIM_Try, /*On fail goto*//*Label 2075*/ 111780, // Rule ID 5650 //
41483 GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
41484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41486 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
41487 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
41488 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
41490 GIM_CheckIsSafeToFold, /*InsnID*/1,
41491 // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
41493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
41497 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41498 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41499 GIR_EraseFromParent, /*InsnID*/0,
41500 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41501 // GIR_Coverage, 5650,
41502 GIR_Done,
41503 // Label 2075: @111780
41504 GIM_Try, /*On fail goto*//*Label 2076*/ 111827, // Rule ID 2449 //
41505 GIM_CheckFeatures, GIFBS_HasNEON_HasVFP4,
41506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
41509 // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq,
41511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41515 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41516 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41517 GIR_EraseFromParent, /*InsnID*/0,
41518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41519 // GIR_Coverage, 2449,
41520 GIR_Done,
41521 // Label 2076: @111827
41522 GIM_Reject,
41523 // Label 2073: @111828
41524 GIM_Reject,
41525 // Label 2045: @111829
41526 GIM_Try, /*On fail goto*//*Label 2077*/ 111892, // Rule ID 2447 //
41527 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
41528 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
41529 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
41530 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
41531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
41532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
41533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
41534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
41535 // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41536 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
41537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
41538 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
41539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
41540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
41541 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41542 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41543 GIR_EraseFromParent, /*InsnID*/0,
41544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41545 // GIR_Coverage, 2447,
41546 GIR_Done,
41547 // Label 2077: @111892
41548 GIM_Reject,
41549 // Label 2046: @111893
41550 GIM_Reject,
41551 // Label 32: @111894
41552 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2081*/ 112059,
41553 /*GILLT_s16*//*Label 2078*/ 111903,
41554 /*GILLT_s32*//*Label 2079*/ 111955,
41555 /*GILLT_s64*//*Label 2080*/ 112007,
41556 // Label 2078: @111903
41557 GIM_Try, /*On fail goto*//*Label 2082*/ 111954, // Rule ID 634 //
41558 GIM_CheckFeatures, GIFBS_HasFullFP16,
41559 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
41560 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
41561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
41562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41564 // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVH,
41566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41569 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41570 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41571 GIR_EraseFromParent, /*InsnID*/0,
41572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41573 // GIR_Coverage, 634,
41574 GIR_Done,
41575 // Label 2082: @111954
41576 GIM_Reject,
41577 // Label 2079: @111955
41578 GIM_Try, /*On fail goto*//*Label 2083*/ 112006, // Rule ID 633 //
41579 GIM_CheckFeatures, GIFBS_HasVFP2,
41580 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41581 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
41582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41585 // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVS,
41587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
41589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
41590 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41591 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41592 GIR_EraseFromParent, /*InsnID*/0,
41593 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41594 // GIR_Coverage, 633,
41595 GIR_Done,
41596 // Label 2083: @112006
41597 GIM_Reject,
41598 // Label 2080: @112007
41599 GIM_Try, /*On fail goto*//*Label 2084*/ 112058, // Rule ID 632 //
41600 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
41601 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
41603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41606 // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41607 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVD,
41608 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
41610 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
41611 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41612 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41613 GIR_EraseFromParent, /*InsnID*/0,
41614 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41615 // GIR_Coverage, 632,
41616 GIR_Done,
41617 // Label 2084: @112058
41618 GIM_Reject,
41619 // Label 2081: @112059
41620 GIM_Reject,
41621 // Label 33: @112060
41622 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2092*/ 113376,
41623 /*GILLT_s16*//*Label 2085*/ 112078,
41624 /*GILLT_s32*//*Label 2086*/ 112407,
41625 /*GILLT_s64*//*Label 2087*/ 112887,
41626 /*GILLT_v2s32*//*Label 2088*/ 113216, 0, 0,
41627 /*GILLT_v4s16*//*Label 2089*/ 113256,
41628 /*GILLT_v4s32*//*Label 2090*/ 113296, 0, 0, 0,
41629 /*GILLT_v8s16*//*Label 2091*/ 113336,
41630 // Label 2085: @112078
41631 GIM_Try, /*On fail goto*//*Label 2093*/ 112406,
41632 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
41633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
41634 GIM_Try, /*On fail goto*//*Label 2094*/ 112169, // Rule ID 2367 //
41635 GIM_CheckFeatures, GIFBS_HasFullFP16,
41636 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41637 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41638 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41639 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
41640 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
41641 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
41642 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41643 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
41644 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41645 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41646 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
41647 GIM_CheckIsSafeToFold, /*InsnID*/1,
41648 GIM_CheckIsSafeToFold, /*InsnID*/2,
41649 // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
41651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41652 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
41653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
41654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
41655 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41656 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41657 GIR_EraseFromParent, /*InsnID*/0,
41658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41659 // GIR_Coverage, 2367,
41660 GIR_Done,
41661 // Label 2094: @112169
41662 GIM_Try, /*On fail goto*//*Label 2095*/ 112250, // Rule ID 5594 //
41663 GIM_CheckFeatures, GIFBS_HasFullFP16,
41664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41665 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41666 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41667 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
41668 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
41669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41670 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
41671 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41672 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
41673 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41674 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
41675 GIM_CheckIsSafeToFold, /*InsnID*/1,
41676 GIM_CheckIsSafeToFold, /*InsnID*/2,
41677 // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSH,
41679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
41681 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
41682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
41683 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41684 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41685 GIR_EraseFromParent, /*InsnID*/0,
41686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41687 // GIR_Coverage, 5594,
41688 GIR_Done,
41689 // Label 2095: @112250
41690 GIM_Try, /*On fail goto*//*Label 2096*/ 112318, // Rule ID 2356 //
41691 GIM_CheckFeatures, GIFBS_HasFullFP16,
41692 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41693 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41694 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41695 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
41696 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
41697 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41698 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41699 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::HPRRegClassID,
41700 GIM_CheckIsSafeToFold, /*InsnID*/1,
41701 // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAH,
41703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
41705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
41707 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41708 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41709 GIR_EraseFromParent, /*InsnID*/0,
41710 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41711 // GIR_Coverage, 2356,
41712 GIR_Done,
41713 // Label 2096: @112318
41714 GIM_Try, /*On fail goto*//*Label 2097*/ 112374, // Rule ID 640 //
41715 GIM_CheckFeatures, GIFBS_HasFullFP16,
41716 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41717 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41718 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41719 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
41720 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41721 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
41722 GIM_CheckIsSafeToFold, /*InsnID*/1,
41723 // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41724 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULH,
41725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
41728 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41729 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41730 GIR_EraseFromParent, /*InsnID*/0,
41731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41732 // GIR_Coverage, 640,
41733 GIR_Done,
41734 // Label 2097: @112374
41735 GIM_Try, /*On fail goto*//*Label 2098*/ 112405, // Rule ID 678 //
41736 GIM_CheckFeatures, GIFBS_HasFullFP16,
41737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
41738 // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
41739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGH,
41740 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41742 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41743 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41744 GIR_EraseFromParent, /*InsnID*/0,
41745 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41746 // GIR_Coverage, 678,
41747 GIR_Done,
41748 // Label 2098: @112405
41749 GIM_Reject,
41750 // Label 2093: @112406
41751 GIM_Reject,
41752 // Label 2086: @112407
41753 GIM_Try, /*On fail goto*//*Label 2099*/ 112886,
41754 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
41755 GIM_Try, /*On fail goto*//*Label 2100*/ 112498, // Rule ID 2366 //
41756 GIM_CheckFeatures, GIFBS_HasVFP4,
41757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41758 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41759 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41760 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41761 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41762 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41763 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
41764 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41765 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
41766 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41767 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41768 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
41769 GIM_CheckIsSafeToFold, /*InsnID*/1,
41770 GIM_CheckIsSafeToFold, /*InsnID*/2,
41771 // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41772 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
41773 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
41775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
41776 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
41777 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41778 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41779 GIR_EraseFromParent, /*InsnID*/0,
41780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41781 // GIR_Coverage, 2366,
41782 GIR_Done,
41783 // Label 2100: @112498
41784 GIM_Try, /*On fail goto*//*Label 2101*/ 112583, // Rule ID 5593 //
41785 GIM_CheckFeatures, GIFBS_HasVFP4,
41786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41787 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41788 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41789 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41790 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41791 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41792 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41793 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
41794 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41795 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
41796 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41797 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
41798 GIM_CheckIsSafeToFold, /*InsnID*/1,
41799 GIM_CheckIsSafeToFold, /*InsnID*/2,
41800 // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41801 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
41802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
41804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
41805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
41806 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41807 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41808 GIR_EraseFromParent, /*InsnID*/0,
41809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41810 // GIR_Coverage, 5593,
41811 GIR_Done,
41812 // Label 2101: @112583
41813 GIM_Try, /*On fail goto*//*Label 2102*/ 112655, // Rule ID 2355 //
41814 GIM_CheckFeatures, GIFBS_HasVFP4,
41815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41817 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41818 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41819 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41820 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
41821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41822 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41823 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
41824 GIM_CheckIsSafeToFold, /*InsnID*/1,
41825 // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
41827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
41829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
41831 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41832 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41833 GIR_EraseFromParent, /*InsnID*/0,
41834 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41835 // GIR_Coverage, 2355,
41836 GIR_Done,
41837 // Label 2102: @112655
41838 GIM_Try, /*On fail goto*//*Label 2103*/ 112715, // Rule ID 639 //
41839 GIM_CheckFeatures, GIFBS_HasVFP2,
41840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41841 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41842 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
41843 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41844 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41845 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41846 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
41847 GIM_CheckIsSafeToFold, /*InsnID*/1,
41848 // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
41850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
41852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
41853 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41854 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41855 GIR_EraseFromParent, /*InsnID*/0,
41856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41857 // GIR_Coverage, 639,
41858 GIR_Done,
41859 // Label 2103: @112715
41860 GIM_Try, /*On fail goto*//*Label 2104*/ 112750, // Rule ID 677 //
41861 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
41862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
41863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41864 // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
41865 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGS,
41866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
41867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
41868 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41869 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41870 GIR_EraseFromParent, /*InsnID*/0,
41871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41872 // GIR_Coverage, 677,
41873 GIR_Done,
41874 // Label 2104: @112750
41875 GIM_Try, /*On fail goto*//*Label 2105*/ 112885, // Rule ID 2620 //
41876 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
41877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
41878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
41879 // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41880 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41881 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41882 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41883 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41884 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41885 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
41886 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
41887 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41888 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
41889 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
41890 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
41891 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
41892 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
41893 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
41894 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
41895 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41896 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
41897 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
41898 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
41899 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
41900 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VNEGfd,
41901 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
41902 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
41903 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
41904 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41905 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41906 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
41907 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
41908 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
41909 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
41911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
41912 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
41913 GIR_EraseFromParent, /*InsnID*/0,
41914 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
41915 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
41916 // GIR_Coverage, 2620,
41917 GIR_Done,
41918 // Label 2105: @112885
41919 GIM_Reject,
41920 // Label 2099: @112886
41921 GIM_Reject,
41922 // Label 2087: @112887
41923 GIM_Try, /*On fail goto*//*Label 2106*/ 113215,
41924 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
41925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
41926 GIM_Try, /*On fail goto*//*Label 2107*/ 112978, // Rule ID 2365 //
41927 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41928 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41929 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41930 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41931 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41932 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41933 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
41934 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41935 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
41936 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41937 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41938 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41939 GIM_CheckIsSafeToFold, /*InsnID*/1,
41940 GIM_CheckIsSafeToFold, /*InsnID*/2,
41941 // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
41943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
41945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
41946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
41947 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41948 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41949 GIR_EraseFromParent, /*InsnID*/0,
41950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41951 // GIR_Coverage, 2365,
41952 GIR_Done,
41953 // Label 2107: @112978
41954 GIM_Try, /*On fail goto*//*Label 2108*/ 113059, // Rule ID 5592 //
41955 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41956 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41957 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41958 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41959 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41960 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41961 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41962 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
41963 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
41964 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
41965 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41966 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41967 GIM_CheckIsSafeToFold, /*InsnID*/1,
41968 GIM_CheckIsSafeToFold, /*InsnID*/2,
41969 // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
41971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
41973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
41974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
41975 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
41976 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
41977 GIR_EraseFromParent, /*InsnID*/0,
41978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
41979 // GIR_Coverage, 5592,
41980 GIR_Done,
41981 // Label 2108: @113059
41982 GIM_Try, /*On fail goto*//*Label 2109*/ 113127, // Rule ID 2354 //
41983 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
41984 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41985 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
41986 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41987 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
41988 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
41989 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
41990 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
41991 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
41992 GIM_CheckIsSafeToFold, /*InsnID*/1,
41993 // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
41995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
41996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
41997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
41998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
41999 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42000 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42001 GIR_EraseFromParent, /*InsnID*/0,
42002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42003 // GIR_Coverage, 2354,
42004 GIR_Done,
42005 // Label 2109: @113127
42006 GIM_Try, /*On fail goto*//*Label 2110*/ 113183, // Rule ID 638 //
42007 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42008 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42009 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
42010 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42011 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
42012 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42013 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
42014 GIM_CheckIsSafeToFold, /*InsnID*/1,
42015 // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42016 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
42017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
42020 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42021 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42022 GIR_EraseFromParent, /*InsnID*/0,
42023 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42024 // GIR_Coverage, 638,
42025 GIR_Done,
42026 // Label 2110: @113183
42027 GIM_Try, /*On fail goto*//*Label 2111*/ 113214, // Rule ID 676 //
42028 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42030 // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
42031 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGD,
42032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42034 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42035 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42036 GIR_EraseFromParent, /*InsnID*/0,
42037 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42038 // GIR_Coverage, 676,
42039 GIR_Done,
42040 // Label 2111: @113214
42041 GIM_Reject,
42042 // Label 2106: @113215
42043 GIM_Reject,
42044 // Label 2088: @113216
42045 GIM_Try, /*On fail goto*//*Label 2112*/ 113255, // Rule ID 1546 //
42046 GIM_CheckFeatures, GIFBS_HasNEON,
42047 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
42048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42050 // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
42051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGfd,
42052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42054 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42055 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42056 GIR_EraseFromParent, /*InsnID*/0,
42057 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42058 // GIR_Coverage, 1546,
42059 GIR_Done,
42060 // Label 2112: @113255
42061 GIM_Reject,
42062 // Label 2089: @113256
42063 GIM_Try, /*On fail goto*//*Label 2113*/ 113295, // Rule ID 1548 //
42064 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42065 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
42066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42068 // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
42069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhd,
42070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42072 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42073 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42074 GIR_EraseFromParent, /*InsnID*/0,
42075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42076 // GIR_Coverage, 1548,
42077 GIR_Done,
42078 // Label 2113: @113295
42079 GIM_Reject,
42080 // Label 2090: @113296
42081 GIM_Try, /*On fail goto*//*Label 2114*/ 113335, // Rule ID 1547 //
42082 GIM_CheckFeatures, GIFBS_HasNEON,
42083 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
42084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42086 // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
42087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGf32q,
42088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42090 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42091 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42092 GIR_EraseFromParent, /*InsnID*/0,
42093 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42094 // GIR_Coverage, 1547,
42095 GIR_Done,
42096 // Label 2114: @113335
42097 GIM_Reject,
42098 // Label 2091: @113336
42099 GIM_Try, /*On fail goto*//*Label 2115*/ 113375, // Rule ID 1549 //
42100 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42101 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42104 // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
42105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhq,
42106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42107 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42108 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42109 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42110 GIR_EraseFromParent, /*InsnID*/0,
42111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42112 // GIR_Coverage, 1549,
42113 GIR_Done,
42114 // Label 2115: @113375
42115 GIM_Reject,
42116 // Label 2092: @113376
42117 GIM_Reject,
42118 // Label 34: @113377
42119 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2118*/ 113536,
42120 /*GILLT_s32*//*Label 2116*/ 113385,
42121 /*GILLT_s64*//*Label 2117*/ 113441,
42122 // Label 2116: @113385
42123 GIM_Try, /*On fail goto*//*Label 2119*/ 113440, // Rule ID 2264 //
42124 GIM_CheckFeatures, GIFBS_HasFP16,
42125 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42128 // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
42129 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42130 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
42131 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42132 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42133 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42134 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHS,
42135 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42136 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42137 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42138 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42139 GIR_EraseFromParent, /*InsnID*/0,
42140 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42141 // GIR_Coverage, 2264,
42142 GIR_Done,
42143 // Label 2119: @113440
42144 GIM_Reject,
42145 // Label 2117: @113441
42146 GIM_Try, /*On fail goto*//*Label 2120*/ 113480, // Rule ID 674 //
42147 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42148 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42151 // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
42152 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTDS,
42153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42155 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42156 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42157 GIR_EraseFromParent, /*InsnID*/0,
42158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42159 // GIR_Coverage, 674,
42160 GIR_Done,
42161 // Label 2120: @113480
42162 GIM_Try, /*On fail goto*//*Label 2121*/ 113535, // Rule ID 2274 //
42163 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42164 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42167 // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
42168 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42169 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
42170 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42171 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42172 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHD,
42174 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
42175 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42176 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42177 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42178 GIR_EraseFromParent, /*InsnID*/0,
42179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42180 // GIR_Coverage, 2274,
42181 GIR_Done,
42182 // Label 2121: @113535
42183 GIM_Reject,
42184 // Label 2118: @113536
42185 GIM_Reject,
42186 // Label 35: @113537
42187 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 2124*/ 113700,
42188 /*GILLT_s16*//*Label 2122*/ 113545,
42189 /*GILLT_s32*//*Label 2123*/ 113660,
42190 // Label 2122: @113545
42191 GIM_Try, /*On fail goto*//*Label 2125*/ 113602, // Rule ID 2266 //
42192 GIM_CheckFeatures, GIFBS_HasFP16,
42193 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
42195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42196 // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
42197 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42198 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBSH,
42199 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42200 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
42201 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42202 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42203 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42204 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42206 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42207 GIR_EraseFromParent, /*InsnID*/0,
42208 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
42209 // GIR_Coverage, 2266,
42210 GIR_Done,
42211 // Label 2125: @113602
42212 GIM_Try, /*On fail goto*//*Label 2126*/ 113659, // Rule ID 2276 //
42213 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42214 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
42216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42217 // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
42218 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42219 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBDH,
42220 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42221 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42222 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42223 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42224 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42226 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42227 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42228 GIR_EraseFromParent, /*InsnID*/0,
42229 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
42230 // GIR_Coverage, 2276,
42231 GIR_Done,
42232 // Label 2126: @113659
42233 GIM_Reject,
42234 // Label 2123: @113660
42235 GIM_Try, /*On fail goto*//*Label 2127*/ 113699, // Rule ID 675 //
42236 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42237 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
42239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42240 // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
42241 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTSD,
42242 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
42243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
42244 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42245 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42246 GIR_EraseFromParent, /*InsnID*/0,
42247 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42248 // GIR_Coverage, 675,
42249 GIR_Done,
42250 // Label 2127: @113699
42251 GIM_Reject,
42252 // Label 2124: @113700
42253 GIM_Reject,
42254 // Label 36: @113701
42255 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 2135*/ 114922,
42256 /*GILLT_s32*//*Label 2128*/ 113718, 0,
42257 /*GILLT_v2s32*//*Label 2129*/ 114564, 0,
42258 /*GILLT_v4s1*//*Label 2130*/ 114604,
42259 /*GILLT_v4s16*//*Label 2131*/ 114651,
42260 /*GILLT_v4s32*//*Label 2132*/ 114691, 0,
42261 /*GILLT_v8s1*//*Label 2133*/ 114783, 0,
42262 /*GILLT_v8s16*//*Label 2134*/ 114830,
42263 // Label 2128: @113718
42264 GIM_Try, /*On fail goto*//*Label 2136*/ 113781, // Rule ID 2284 //
42265 GIM_CheckFeatures, GIFBS_HasFullFP16,
42266 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42268 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42269 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
42270 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42271 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42272 GIM_CheckIsSafeToFold, /*InsnID*/1,
42273 // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42274 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42275 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSH,
42276 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42277 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42278 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42279 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42281 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42282 GIR_EraseFromParent, /*InsnID*/0,
42283 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42284 // GIR_Coverage, 2284,
42285 GIR_Done,
42286 // Label 2136: @113781
42287 GIM_Try, /*On fail goto*//*Label 2137*/ 113844, // Rule ID 2286 //
42288 GIM_CheckFeatures, GIFBS_HasFPARMv8,
42289 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42291 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42292 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
42293 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42294 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42295 GIM_CheckIsSafeToFold, /*InsnID*/1,
42296 // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42297 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42298 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSS,
42299 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42300 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42301 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42302 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42304 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42305 GIR_EraseFromParent, /*InsnID*/0,
42306 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42307 // GIR_Coverage, 2286,
42308 GIR_Done,
42309 // Label 2137: @113844
42310 GIM_Try, /*On fail goto*//*Label 2138*/ 113907, // Rule ID 2288 //
42311 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42312 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42314 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42315 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
42316 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42317 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42318 GIM_CheckIsSafeToFold, /*InsnID*/1,
42319 // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42321 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPSD,
42322 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42323 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42324 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42325 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42327 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42328 GIR_EraseFromParent, /*InsnID*/0,
42329 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42330 // GIR_Coverage, 2288,
42331 GIR_Done,
42332 // Label 2138: @113907
42333 GIM_Try, /*On fail goto*//*Label 2139*/ 113970, // Rule ID 2290 //
42334 GIM_CheckFeatures, GIFBS_HasFullFP16,
42335 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42337 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42338 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
42339 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42340 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42341 GIM_CheckIsSafeToFold, /*InsnID*/1,
42342 // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42343 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42344 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSH,
42345 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42346 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42347 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42350 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42351 GIR_EraseFromParent, /*InsnID*/0,
42352 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42353 // GIR_Coverage, 2290,
42354 GIR_Done,
42355 // Label 2139: @113970
42356 GIM_Try, /*On fail goto*//*Label 2140*/ 114033, // Rule ID 2292 //
42357 GIM_CheckFeatures, GIFBS_HasFPARMv8,
42358 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42360 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42361 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
42362 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42363 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42364 GIM_CheckIsSafeToFold, /*InsnID*/1,
42365 // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42366 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42367 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSS,
42368 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42369 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42370 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42373 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42374 GIR_EraseFromParent, /*InsnID*/0,
42375 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42376 // GIR_Coverage, 2292,
42377 GIR_Done,
42378 // Label 2140: @114033
42379 GIM_Try, /*On fail goto*//*Label 2141*/ 114096, // Rule ID 2294 //
42380 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42381 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42383 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42384 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
42385 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42386 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42387 GIM_CheckIsSafeToFold, /*InsnID*/1,
42388 // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42389 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42390 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMSD,
42391 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42392 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42393 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42396 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42397 GIR_EraseFromParent, /*InsnID*/0,
42398 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42399 // GIR_Coverage, 2294,
42400 GIR_Done,
42401 // Label 2141: @114096
42402 GIM_Try, /*On fail goto*//*Label 2142*/ 114159, // Rule ID 2278 //
42403 GIM_CheckFeatures, GIFBS_HasFullFP16,
42404 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42406 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42407 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
42408 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42409 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42410 GIM_CheckIsSafeToFold, /*InsnID*/1,
42411 // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42412 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42413 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASH,
42414 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42415 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42416 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42419 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42420 GIR_EraseFromParent, /*InsnID*/0,
42421 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42422 // GIR_Coverage, 2278,
42423 GIR_Done,
42424 // Label 2142: @114159
42425 GIM_Try, /*On fail goto*//*Label 2143*/ 114222, // Rule ID 2280 //
42426 GIM_CheckFeatures, GIFBS_HasFPARMv8,
42427 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42429 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42430 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
42431 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42432 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42433 GIM_CheckIsSafeToFold, /*InsnID*/1,
42434 // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42435 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42436 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASS,
42437 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42438 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42439 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42440 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42442 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42443 GIR_EraseFromParent, /*InsnID*/0,
42444 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42445 // GIR_Coverage, 2280,
42446 GIR_Done,
42447 // Label 2143: @114222
42448 GIM_Try, /*On fail goto*//*Label 2144*/ 114285, // Rule ID 2282 //
42449 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42450 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42452 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42453 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
42454 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42455 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42456 GIM_CheckIsSafeToFold, /*InsnID*/1,
42457 // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42458 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42459 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTASD,
42460 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42461 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42462 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42465 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42466 GIR_EraseFromParent, /*InsnID*/0,
42467 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42468 // GIR_Coverage, 2282,
42469 GIR_Done,
42470 // Label 2144: @114285
42471 GIM_Try, /*On fail goto*//*Label 2145*/ 114342, // Rule ID 2315 //
42472 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42473 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42476 // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42477 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42478 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZD,
42479 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42480 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42481 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42482 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42483 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42484 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42486 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42487 GIR_EraseFromParent, /*InsnID*/0,
42488 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42489 // GIR_Coverage, 2315,
42490 GIR_Done,
42491 // Label 2145: @114342
42492 GIM_Try, /*On fail goto*//*Label 2146*/ 114399, // Rule ID 2317 //
42493 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
42494 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42497 // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42498 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42499 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZS,
42500 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42501 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42502 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42503 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42504 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42505 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42506 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42507 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42508 GIR_EraseFromParent, /*InsnID*/0,
42509 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42510 // GIR_Coverage, 2317,
42511 GIR_Done,
42512 // Label 2146: @114399
42513 GIM_Try, /*On fail goto*//*Label 2147*/ 114456, // Rule ID 2319 //
42514 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
42515 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42518 // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42519 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42520 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZH,
42521 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42522 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42523 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42524 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42525 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42528 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42529 GIR_EraseFromParent, /*InsnID*/0,
42530 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42531 // GIR_Coverage, 2319,
42532 GIR_Done,
42533 // Label 2147: @114456
42534 GIM_Try, /*On fail goto*//*Label 2148*/ 114563, // Rule ID 2625 //
42535 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
42536 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42539 // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
42540 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42541 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
42542 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42543 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
42544 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
42545 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42546 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
42547 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
42548 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
42549 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
42550 GIR_AddImm, /*InsnID*/2, /*Imm*/17,
42551 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
42552 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
42553 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
42554 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTf2sd,
42555 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42556 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
42557 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42558 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42559 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42560 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42562 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
42563 GIR_EraseFromParent, /*InsnID*/0,
42564 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
42565 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
42566 // GIR_Coverage, 2625,
42567 GIR_Done,
42568 // Label 2148: @114563
42569 GIM_Reject,
42570 // Label 2129: @114564
42571 GIM_Try, /*On fail goto*//*Label 2149*/ 114603, // Rule ID 1620 //
42572 GIM_CheckFeatures, GIFBS_HasNEON,
42573 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
42574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42576 // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
42577 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sd,
42578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42580 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42581 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42582 GIR_EraseFromParent, /*InsnID*/0,
42583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42584 // GIR_Coverage, 1620,
42585 GIR_Done,
42586 // Label 2149: @114603
42587 GIM_Reject,
42588 // Label 2130: @114604
42589 GIM_Try, /*On fail goto*//*Label 2150*/ 114650, // Rule ID 4980 //
42590 GIM_CheckFeatures, GIFBS_HasMVEFloat,
42591 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
42592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
42593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
42594 // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
42595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
42596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
42597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
42598 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
42599 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
42600 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
42601 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42602 GIR_EraseFromParent, /*InsnID*/0,
42603 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42604 // GIR_Coverage, 4980,
42605 GIR_Done,
42606 // Label 2150: @114650
42607 GIM_Reject,
42608 // Label 2131: @114651
42609 GIM_Try, /*On fail goto*//*Label 2151*/ 114690, // Rule ID 1628 //
42610 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42611 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
42612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
42613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42614 // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
42615 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sd,
42616 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42618 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42619 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42620 GIR_EraseFromParent, /*InsnID*/0,
42621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42622 // GIR_Coverage, 1628,
42623 GIR_Done,
42624 // Label 2151: @114690
42625 GIM_Reject,
42626 // Label 2132: @114691
42627 GIM_Try, /*On fail goto*//*Label 2152*/ 114782,
42628 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
42629 GIM_Try, /*On fail goto*//*Label 2153*/ 114732, // Rule ID 1624 //
42630 GIM_CheckFeatures, GIFBS_HasNEON,
42631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42633 // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
42634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sq,
42635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42637 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42638 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42639 GIR_EraseFromParent, /*InsnID*/0,
42640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42641 // GIR_Coverage, 1624,
42642 GIR_Done,
42643 // Label 2153: @114732
42644 GIM_Try, /*On fail goto*//*Label 2154*/ 114781, // Rule ID 4040 //
42645 GIM_CheckFeatures, GIFBS_HasMVEFloat,
42646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
42647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
42648 // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
42649 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42650 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
42651 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
42652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs32f32z,
42653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
42654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
42655 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
42656 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42657 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42658 GIR_EraseFromParent, /*InsnID*/0,
42659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42660 // GIR_Coverage, 4040,
42661 GIR_Done,
42662 // Label 2154: @114781
42663 GIM_Reject,
42664 // Label 2152: @114782
42665 GIM_Reject,
42666 // Label 2133: @114783
42667 GIM_Try, /*On fail goto*//*Label 2155*/ 114829, // Rule ID 4981 //
42668 GIM_CheckFeatures, GIFBS_HasMVEFloat,
42669 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
42671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
42672 // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
42673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
42674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
42675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
42676 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
42677 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
42678 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
42679 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42680 GIR_EraseFromParent, /*InsnID*/0,
42681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42682 // GIR_Coverage, 4981,
42683 GIR_Done,
42684 // Label 2155: @114829
42685 GIM_Reject,
42686 // Label 2134: @114830
42687 GIM_Try, /*On fail goto*//*Label 2156*/ 114921,
42688 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
42689 GIM_Try, /*On fail goto*//*Label 2157*/ 114871, // Rule ID 1632 //
42690 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
42691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
42692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
42693 // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
42694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sq,
42695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
42696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
42697 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
42698 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42699 GIR_EraseFromParent, /*InsnID*/0,
42700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42701 // GIR_Coverage, 1632,
42702 GIR_Done,
42703 // Label 2157: @114871
42704 GIM_Try, /*On fail goto*//*Label 2158*/ 114920, // Rule ID 4036 //
42705 GIM_CheckFeatures, GIFBS_HasMVEFloat,
42706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
42707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
42708 // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
42709 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42710 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
42711 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
42712 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTs16f16z,
42713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
42714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
42715 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
42716 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42717 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42718 GIR_EraseFromParent, /*InsnID*/0,
42719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
42720 // GIR_Coverage, 4036,
42721 GIR_Done,
42722 // Label 2158: @114920
42723 GIM_Reject,
42724 // Label 2156: @114921
42725 GIM_Reject,
42726 // Label 2135: @114922
42727 GIM_Reject,
42728 // Label 37: @114923
42729 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 2166*/ 116144,
42730 /*GILLT_s32*//*Label 2159*/ 114940, 0,
42731 /*GILLT_v2s32*//*Label 2160*/ 115786, 0,
42732 /*GILLT_v4s1*//*Label 2161*/ 115826,
42733 /*GILLT_v4s16*//*Label 2162*/ 115873,
42734 /*GILLT_v4s32*//*Label 2163*/ 115913, 0,
42735 /*GILLT_v8s1*//*Label 2164*/ 116005, 0,
42736 /*GILLT_v8s16*//*Label 2165*/ 116052,
42737 // Label 2159: @114940
42738 GIM_Try, /*On fail goto*//*Label 2167*/ 115003, // Rule ID 2285 //
42739 GIM_CheckFeatures, GIFBS_HasFullFP16,
42740 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42743 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
42744 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42745 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42746 GIM_CheckIsSafeToFold, /*InsnID*/1,
42747 // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42748 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUH,
42750 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42751 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42752 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42753 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42755 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42756 GIR_EraseFromParent, /*InsnID*/0,
42757 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42758 // GIR_Coverage, 2285,
42759 GIR_Done,
42760 // Label 2167: @115003
42761 GIM_Try, /*On fail goto*//*Label 2168*/ 115066, // Rule ID 2287 //
42762 GIM_CheckFeatures, GIFBS_HasFPARMv8,
42763 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42765 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42766 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
42767 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42768 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42769 GIM_CheckIsSafeToFold, /*InsnID*/1,
42770 // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42771 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42772 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUS,
42773 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42774 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42775 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42776 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42777 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42778 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42779 GIR_EraseFromParent, /*InsnID*/0,
42780 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42781 // GIR_Coverage, 2287,
42782 GIR_Done,
42783 // Label 2168: @115066
42784 GIM_Try, /*On fail goto*//*Label 2169*/ 115129, // Rule ID 2289 //
42785 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42786 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42788 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42789 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FCEIL,
42790 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42791 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42792 GIM_CheckIsSafeToFold, /*InsnID*/1,
42793 // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42794 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42795 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTPUD,
42796 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42797 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42798 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42801 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42802 GIR_EraseFromParent, /*InsnID*/0,
42803 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42804 // GIR_Coverage, 2289,
42805 GIR_Done,
42806 // Label 2169: @115129
42807 GIM_Try, /*On fail goto*//*Label 2170*/ 115192, // Rule ID 2291 //
42808 GIM_CheckFeatures, GIFBS_HasFullFP16,
42809 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42811 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42812 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
42813 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42814 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42815 GIM_CheckIsSafeToFold, /*InsnID*/1,
42816 // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42817 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42818 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUH,
42819 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42820 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42821 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42823 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42824 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42825 GIR_EraseFromParent, /*InsnID*/0,
42826 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42827 // GIR_Coverage, 2291,
42828 GIR_Done,
42829 // Label 2170: @115192
42830 GIM_Try, /*On fail goto*//*Label 2171*/ 115255, // Rule ID 2293 //
42831 GIM_CheckFeatures, GIFBS_HasFPARMv8,
42832 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42834 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42835 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
42836 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42837 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42838 GIM_CheckIsSafeToFold, /*InsnID*/1,
42839 // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42840 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42841 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUS,
42842 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42843 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42844 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42845 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42847 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42848 GIR_EraseFromParent, /*InsnID*/0,
42849 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42850 // GIR_Coverage, 2293,
42851 GIR_Done,
42852 // Label 2171: @115255
42853 GIM_Try, /*On fail goto*//*Label 2172*/ 115318, // Rule ID 2295 //
42854 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42855 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42857 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42858 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FFLOOR,
42859 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42860 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42861 GIM_CheckIsSafeToFold, /*InsnID*/1,
42862 // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42863 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42864 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTMUD,
42865 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42866 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42867 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42870 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42871 GIR_EraseFromParent, /*InsnID*/0,
42872 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42873 // GIR_Coverage, 2295,
42874 GIR_Done,
42875 // Label 2172: @115318
42876 GIM_Try, /*On fail goto*//*Label 2173*/ 115381, // Rule ID 2279 //
42877 GIM_CheckFeatures, GIFBS_HasFullFP16,
42878 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42880 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42881 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
42882 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42883 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42884 GIM_CheckIsSafeToFold, /*InsnID*/1,
42885 // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42886 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42887 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUH,
42888 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42889 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42890 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42891 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42892 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42893 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42894 GIR_EraseFromParent, /*InsnID*/0,
42895 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42896 // GIR_Coverage, 2279,
42897 GIR_Done,
42898 // Label 2173: @115381
42899 GIM_Try, /*On fail goto*//*Label 2174*/ 115444, // Rule ID 2281 //
42900 GIM_CheckFeatures, GIFBS_HasFPARMv8,
42901 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42903 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42904 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
42905 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42906 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42907 GIM_CheckIsSafeToFold, /*InsnID*/1,
42908 // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42909 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42910 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUS,
42911 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42912 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42913 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42916 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42917 GIR_EraseFromParent, /*InsnID*/0,
42918 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42919 // GIR_Coverage, 2281,
42920 GIR_Done,
42921 // Label 2174: @115444
42922 GIM_Try, /*On fail goto*//*Label 2175*/ 115507, // Rule ID 2283 //
42923 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
42924 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42926 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42927 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_ROUND,
42928 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42929 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42930 GIM_CheckIsSafeToFold, /*InsnID*/1,
42931 // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42932 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42933 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTAUD,
42934 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42935 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
42936 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42939 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42940 GIR_EraseFromParent, /*InsnID*/0,
42941 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42942 // GIR_Coverage, 2283,
42943 GIR_Done,
42944 // Label 2175: @115507
42945 GIM_Try, /*On fail goto*//*Label 2176*/ 115564, // Rule ID 2320 //
42946 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
42947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
42948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
42950 // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42951 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42952 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZD,
42953 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42954 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42955 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42956 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42957 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42958 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42960 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42961 GIR_EraseFromParent, /*InsnID*/0,
42962 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42963 // GIR_Coverage, 2320,
42964 GIR_Done,
42965 // Label 2176: @115564
42966 GIM_Try, /*On fail goto*//*Label 2177*/ 115621, // Rule ID 2322 //
42967 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
42968 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
42969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
42971 // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42972 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42973 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZS,
42974 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42975 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42976 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42977 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42978 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
42980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
42981 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
42982 GIR_EraseFromParent, /*InsnID*/0,
42983 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
42984 // GIR_Coverage, 2322,
42985 GIR_Done,
42986 // Label 2177: @115621
42987 GIM_Try, /*On fail goto*//*Label 2178*/ 115678, // Rule ID 2324 //
42988 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
42989 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
42990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
42991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
42992 // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42993 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42994 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZH,
42995 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
42996 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42997 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
42998 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
42999 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43002 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43003 GIR_EraseFromParent, /*InsnID*/0,
43004 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::GPRRegClassID,
43005 // GIR_Coverage, 2324,
43006 GIR_Done,
43007 // Label 2178: @115678
43008 GIM_Try, /*On fail goto*//*Label 2179*/ 115785, // Rule ID 2626 //
43009 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
43010 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43011 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43013 // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
43014 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43015 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
43016 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43017 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43018 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
43019 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43020 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
43021 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43022 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
43023 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
43024 GIR_AddImm, /*InsnID*/2, /*Imm*/17,
43025 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
43026 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
43027 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
43028 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTf2ud,
43029 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43030 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43031 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43032 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43033 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43036 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
43037 GIR_EraseFromParent, /*InsnID*/0,
43038 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
43039 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
43040 // GIR_Coverage, 2626,
43041 GIR_Done,
43042 // Label 2179: @115785
43043 GIM_Reject,
43044 // Label 2160: @115786
43045 GIM_Try, /*On fail goto*//*Label 2180*/ 115825, // Rule ID 1621 //
43046 GIM_CheckFeatures, GIFBS_HasNEON,
43047 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43050 // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
43051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2ud,
43052 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43054 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43055 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43056 GIR_EraseFromParent, /*InsnID*/0,
43057 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43058 // GIR_Coverage, 1621,
43059 GIR_Done,
43060 // Label 2180: @115825
43061 GIM_Reject,
43062 // Label 2161: @115826
43063 GIM_Try, /*On fail goto*//*Label 2181*/ 115872, // Rule ID 4978 //
43064 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43065 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43066 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
43067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43068 // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
43069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf32r,
43070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
43071 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
43072 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
43073 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
43074 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43075 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43076 GIR_EraseFromParent, /*InsnID*/0,
43077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43078 // GIR_Coverage, 4978,
43079 GIR_Done,
43080 // Label 2181: @115872
43081 GIM_Reject,
43082 // Label 2162: @115873
43083 GIM_Try, /*On fail goto*//*Label 2182*/ 115912, // Rule ID 1629 //
43084 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43085 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43088 // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
43089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2ud,
43090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43092 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43093 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43094 GIR_EraseFromParent, /*InsnID*/0,
43095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43096 // GIR_Coverage, 1629,
43097 GIR_Done,
43098 // Label 2182: @115912
43099 GIM_Reject,
43100 // Label 2163: @115913
43101 GIM_Try, /*On fail goto*//*Label 2183*/ 116004,
43102 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43103 GIM_Try, /*On fail goto*//*Label 2184*/ 115954, // Rule ID 1625 //
43104 GIM_CheckFeatures, GIFBS_HasNEON,
43105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43107 // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
43108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2uq,
43109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43111 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43112 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43113 GIR_EraseFromParent, /*InsnID*/0,
43114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43115 // GIR_Coverage, 1625,
43116 GIR_Done,
43117 // Label 2184: @115954
43118 GIM_Try, /*On fail goto*//*Label 2185*/ 116003, // Rule ID 4042 //
43119 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43122 // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
43123 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43124 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43125 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu32f32z,
43127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43129 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43130 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43131 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43132 GIR_EraseFromParent, /*InsnID*/0,
43133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43134 // GIR_Coverage, 4042,
43135 GIR_Done,
43136 // Label 2185: @116003
43137 GIM_Reject,
43138 // Label 2183: @116004
43139 GIM_Reject,
43140 // Label 2164: @116005
43141 GIM_Try, /*On fail goto*//*Label 2186*/ 116051, // Rule ID 4979 //
43142 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::VCCRRegClassID,
43145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43146 // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
43147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCMPf16r,
43148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // P0
43149 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // v1
43150 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
43151 GIR_AddImm, /*InsnID*/0, /*Imm*/1,
43152 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43153 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43154 GIR_EraseFromParent, /*InsnID*/0,
43155 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43156 // GIR_Coverage, 4979,
43157 GIR_Done,
43158 // Label 2186: @116051
43159 GIM_Reject,
43160 // Label 2165: @116052
43161 GIM_Try, /*On fail goto*//*Label 2187*/ 116143,
43162 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43163 GIM_Try, /*On fail goto*//*Label 2188*/ 116093, // Rule ID 1633 //
43164 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43167 // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
43168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2uq,
43169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43171 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43172 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43173 GIR_EraseFromParent, /*InsnID*/0,
43174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43175 // GIR_Coverage, 1633,
43176 GIR_Done,
43177 // Label 2188: @116093
43178 GIM_Try, /*On fail goto*//*Label 2189*/ 116142, // Rule ID 4038 //
43179 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43182 // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
43183 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43184 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43185 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTu16f16z,
43187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43189 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43190 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43191 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43192 GIR_EraseFromParent, /*InsnID*/0,
43193 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43194 // GIR_Coverage, 4038,
43195 GIR_Done,
43196 // Label 2189: @116142
43197 GIM_Reject,
43198 // Label 2187: @116143
43199 GIM_Reject,
43200 // Label 2166: @116144
43201 GIM_Reject,
43202 // Label 38: @116145
43203 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2197*/ 116717,
43204 /*GILLT_s16*//*Label 2190*/ 116163,
43205 /*GILLT_s32*//*Label 2191*/ 116219,
43206 /*GILLT_s64*//*Label 2192*/ 116397,
43207 /*GILLT_v2s32*//*Label 2193*/ 116453, 0, 0,
43208 /*GILLT_v4s16*//*Label 2194*/ 116493,
43209 /*GILLT_v4s32*//*Label 2195*/ 116533, 0, 0, 0,
43210 /*GILLT_v8s16*//*Label 2196*/ 116625,
43211 // Label 2190: @116163
43212 GIM_Try, /*On fail goto*//*Label 2198*/ 116218, // Rule ID 2309 //
43213 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43214 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
43216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43217 // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
43218 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43219 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43220 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43221 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43222 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOH,
43224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43225 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43226 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43227 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43228 GIR_EraseFromParent, /*InsnID*/0,
43229 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43230 // GIR_Coverage, 2309,
43231 GIR_Done,
43232 // Label 2198: @116218
43233 GIM_Reject,
43234 // Label 2191: @116219
43235 GIM_Try, /*On fail goto*//*Label 2199*/ 116396,
43236 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43237 GIM_Try, /*On fail goto*//*Label 2200*/ 116276, // Rule ID 2307 //
43238 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43241 // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
43242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43244 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43245 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43246 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOS,
43248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43249 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43250 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43251 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43252 GIR_EraseFromParent, /*InsnID*/0,
43253 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43254 // GIR_Coverage, 2307,
43255 GIR_Done,
43256 // Label 2200: @116276
43257 GIM_Try, /*On fail goto*//*Label 2201*/ 116395, // Rule ID 2627 //
43258 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
43259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43261 // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
43262 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43263 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
43264 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43265 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
43266 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
43267 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
43268 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
43269 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43270 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43271 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
43272 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43273 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
43274 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43275 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
43276 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/3, /*TempRegFlags*/0,
43277 GIR_AddImm, /*InsnID*/2, /*Imm*/17,
43278 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
43279 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
43280 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
43281 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTs2fd,
43282 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43283 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43284 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43285 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43286 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43289 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
43290 GIR_EraseFromParent, /*InsnID*/0,
43291 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
43292 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
43293 // GIR_Coverage, 2627,
43294 GIR_Done,
43295 // Label 2201: @116395
43296 GIM_Reject,
43297 // Label 2199: @116396
43298 GIM_Reject,
43299 // Label 2192: @116397
43300 GIM_Try, /*On fail goto*//*Label 2202*/ 116452, // Rule ID 2305 //
43301 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43302 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43305 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
43306 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43307 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43308 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43309 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43310 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOD,
43312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43313 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43314 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43315 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43316 GIR_EraseFromParent, /*InsnID*/0,
43317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43318 // GIR_Coverage, 2305,
43319 GIR_Done,
43320 // Label 2202: @116452
43321 GIM_Reject,
43322 // Label 2193: @116453
43323 GIM_Try, /*On fail goto*//*Label 2203*/ 116492, // Rule ID 1622 //
43324 GIM_CheckFeatures, GIFBS_HasNEON,
43325 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43328 // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
43329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fd,
43330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43332 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43333 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43334 GIR_EraseFromParent, /*InsnID*/0,
43335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43336 // GIR_Coverage, 1622,
43337 GIR_Done,
43338 // Label 2203: @116492
43339 GIM_Reject,
43340 // Label 2194: @116493
43341 GIM_Try, /*On fail goto*//*Label 2204*/ 116532, // Rule ID 1630 //
43342 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43343 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43346 // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
43347 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hd,
43348 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43350 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43351 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43352 GIR_EraseFromParent, /*InsnID*/0,
43353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43354 // GIR_Coverage, 1630,
43355 GIR_Done,
43356 // Label 2204: @116532
43357 GIM_Reject,
43358 // Label 2195: @116533
43359 GIM_Try, /*On fail goto*//*Label 2205*/ 116624,
43360 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43361 GIM_Try, /*On fail goto*//*Label 2206*/ 116574, // Rule ID 1626 //
43362 GIM_CheckFeatures, GIFBS_HasNEON,
43363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43365 // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
43366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fq,
43367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43369 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43370 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43371 GIR_EraseFromParent, /*InsnID*/0,
43372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43373 // GIR_Coverage, 1626,
43374 GIR_Done,
43375 // Label 2206: @116574
43376 GIM_Try, /*On fail goto*//*Label 2207*/ 116623, // Rule ID 4048 //
43377 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43380 // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
43381 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43382 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43383 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32s32n,
43385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43387 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43388 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43389 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43390 GIR_EraseFromParent, /*InsnID*/0,
43391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43392 // GIR_Coverage, 4048,
43393 GIR_Done,
43394 // Label 2207: @116623
43395 GIM_Reject,
43396 // Label 2205: @116624
43397 GIM_Reject,
43398 // Label 2196: @116625
43399 GIM_Try, /*On fail goto*//*Label 2208*/ 116716,
43400 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43401 GIM_Try, /*On fail goto*//*Label 2209*/ 116666, // Rule ID 1634 //
43402 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43405 // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
43406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hq,
43407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43409 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43410 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43411 GIR_EraseFromParent, /*InsnID*/0,
43412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43413 // GIR_Coverage, 1634,
43414 GIR_Done,
43415 // Label 2209: @116666
43416 GIM_Try, /*On fail goto*//*Label 2210*/ 116715, // Rule ID 4044 //
43417 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43420 // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
43421 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43423 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43424 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16s16n,
43425 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43426 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43427 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43428 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43429 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43430 GIR_EraseFromParent, /*InsnID*/0,
43431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43432 // GIR_Coverage, 4044,
43433 GIR_Done,
43434 // Label 2210: @116715
43435 GIM_Reject,
43436 // Label 2208: @116716
43437 GIM_Reject,
43438 // Label 2197: @116717
43439 GIM_Reject,
43440 // Label 39: @116718
43441 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2218*/ 117290,
43442 /*GILLT_s16*//*Label 2211*/ 116736,
43443 /*GILLT_s32*//*Label 2212*/ 116792,
43444 /*GILLT_s64*//*Label 2213*/ 116970,
43445 /*GILLT_v2s32*//*Label 2214*/ 117026, 0, 0,
43446 /*GILLT_v4s16*//*Label 2215*/ 117066,
43447 /*GILLT_v4s32*//*Label 2216*/ 117106, 0, 0, 0,
43448 /*GILLT_v8s16*//*Label 2217*/ 117198,
43449 // Label 2211: @116736
43450 GIM_Try, /*On fail goto*//*Label 2219*/ 116791, // Rule ID 2314 //
43451 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43452 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
43454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43455 // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
43456 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43457 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43458 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43459 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43460 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOH,
43462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43463 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43464 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43465 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43466 GIR_EraseFromParent, /*InsnID*/0,
43467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43468 // GIR_Coverage, 2314,
43469 GIR_Done,
43470 // Label 2219: @116791
43471 GIM_Reject,
43472 // Label 2212: @116792
43473 GIM_Try, /*On fail goto*//*Label 2220*/ 116969,
43474 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43475 GIM_Try, /*On fail goto*//*Label 2221*/ 116849, // Rule ID 2312 //
43476 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43479 // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
43480 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43481 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43482 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43483 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43484 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOS,
43486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43487 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43488 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43489 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43490 GIR_EraseFromParent, /*InsnID*/0,
43491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43492 // GIR_Coverage, 2312,
43493 GIR_Done,
43494 // Label 2221: @116849
43495 GIM_Try, /*On fail goto*//*Label 2222*/ 116968, // Rule ID 2628 //
43496 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
43497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43499 // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
43500 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43501 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
43502 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43503 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
43504 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
43505 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
43506 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
43507 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43508 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43509 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
43510 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
43511 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::INSERT_SUBREG,
43512 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43513 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
43514 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/3, /*TempRegFlags*/0,
43515 GIR_AddImm, /*InsnID*/2, /*Imm*/17,
43516 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, ARM::DPR_VFP2RegClassID,
43517 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, ARM::DPR_VFP2RegClassID,
43518 GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, ARM::SPRRegClassID,
43519 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTu2fd,
43520 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43521 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43522 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
43523 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43524 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43527 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
43528 GIR_EraseFromParent, /*InsnID*/0,
43529 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
43530 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
43531 // GIR_Coverage, 2628,
43532 GIR_Done,
43533 // Label 2222: @116968
43534 GIM_Reject,
43535 // Label 2220: @116969
43536 GIM_Reject,
43537 // Label 2213: @116970
43538 GIM_Try, /*On fail goto*//*Label 2223*/ 117025, // Rule ID 2310 //
43539 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43540 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
43543 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
43544 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43545 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43546 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43547 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
43548 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43549 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOD,
43550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43551 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43552 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43553 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43554 GIR_EraseFromParent, /*InsnID*/0,
43555 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43556 // GIR_Coverage, 2310,
43557 GIR_Done,
43558 // Label 2223: @117025
43559 GIM_Reject,
43560 // Label 2214: @117026
43561 GIM_Try, /*On fail goto*//*Label 2224*/ 117065, // Rule ID 1623 //
43562 GIM_CheckFeatures, GIFBS_HasNEON,
43563 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43566 // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
43567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fd,
43568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43570 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43571 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43572 GIR_EraseFromParent, /*InsnID*/0,
43573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43574 // GIR_Coverage, 1623,
43575 GIR_Done,
43576 // Label 2224: @117065
43577 GIM_Reject,
43578 // Label 2215: @117066
43579 GIM_Try, /*On fail goto*//*Label 2225*/ 117105, // Rule ID 1631 //
43580 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43581 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43584 // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
43585 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hd,
43586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43588 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43589 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43590 GIR_EraseFromParent, /*InsnID*/0,
43591 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43592 // GIR_Coverage, 1631,
43593 GIR_Done,
43594 // Label 2225: @117105
43595 GIM_Reject,
43596 // Label 2216: @117106
43597 GIM_Try, /*On fail goto*//*Label 2226*/ 117197,
43598 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43599 GIM_Try, /*On fail goto*//*Label 2227*/ 117147, // Rule ID 1627 //
43600 GIM_CheckFeatures, GIFBS_HasNEON,
43601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43603 // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
43604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fq,
43605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43607 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43608 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43609 GIR_EraseFromParent, /*InsnID*/0,
43610 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43611 // GIR_Coverage, 1627,
43612 GIR_Done,
43613 // Label 2227: @117147
43614 GIM_Try, /*On fail goto*//*Label 2228*/ 117196, // Rule ID 4050 //
43615 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43618 // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
43619 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43620 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43621 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf32u32n,
43623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43625 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43626 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43627 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43628 GIR_EraseFromParent, /*InsnID*/0,
43629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43630 // GIR_Coverage, 4050,
43631 GIR_Done,
43632 // Label 2228: @117196
43633 GIM_Reject,
43634 // Label 2226: @117197
43635 GIM_Reject,
43636 // Label 2217: @117198
43637 GIM_Try, /*On fail goto*//*Label 2229*/ 117289,
43638 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43639 GIM_Try, /*On fail goto*//*Label 2230*/ 117239, // Rule ID 1635 //
43640 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43643 // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
43644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hq,
43645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43647 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43648 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43649 GIR_EraseFromParent, /*InsnID*/0,
43650 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43651 // GIR_Coverage, 1635,
43652 GIR_Done,
43653 // Label 2230: @117239
43654 GIM_Try, /*On fail goto*//*Label 2231*/ 117288, // Rule ID 4046 //
43655 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43658 // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
43659 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43660 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43661 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCVTf16u16n,
43663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
43665 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43666 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43667 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43668 GIR_EraseFromParent, /*InsnID*/0,
43669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43670 // GIR_Coverage, 4046,
43671 GIR_Done,
43672 // Label 2231: @117288
43673 GIM_Reject,
43674 // Label 2229: @117289
43675 GIM_Reject,
43676 // Label 2218: @117290
43677 GIM_Reject,
43678 // Label 40: @117291
43679 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2239*/ 117881,
43680 /*GILLT_s16*//*Label 2232*/ 117309,
43681 /*GILLT_s32*//*Label 2233*/ 117349,
43682 /*GILLT_s64*//*Label 2234*/ 117527,
43683 /*GILLT_v2s32*//*Label 2235*/ 117567, 0, 0,
43684 /*GILLT_v4s16*//*Label 2236*/ 117607,
43685 /*GILLT_v4s32*//*Label 2237*/ 117647, 0, 0, 0,
43686 /*GILLT_v8s16*//*Label 2238*/ 117764,
43687 // Label 2232: @117309
43688 GIM_Try, /*On fail goto*//*Label 2240*/ 117348, // Rule ID 667 //
43689 GIM_CheckFeatures, GIFBS_HasFullFP16,
43690 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
43692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43693 // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
43694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSH,
43695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43697 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43698 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43699 GIR_EraseFromParent, /*InsnID*/0,
43700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43701 // GIR_Coverage, 667,
43702 GIR_Done,
43703 // Label 2240: @117348
43704 GIM_Reject,
43705 // Label 2233: @117349
43706 GIM_Try, /*On fail goto*//*Label 2241*/ 117526,
43707 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43708 GIM_Try, /*On fail goto*//*Label 2242*/ 117390, // Rule ID 666 //
43709 GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
43710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43712 // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
43713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSS,
43714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
43715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43716 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43717 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43718 GIR_EraseFromParent, /*InsnID*/0,
43719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43720 // GIR_Coverage, 666,
43721 GIR_Done,
43722 // Label 2242: @117390
43723 GIM_Try, /*On fail goto*//*Label 2243*/ 117525, // Rule ID 2619 //
43724 GIM_CheckFeatures, GIFBS_HasNEON_UseNEONForFP,
43725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPR_VFP2RegClassID,
43726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43727 // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43728 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43729 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43730 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43731 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43732 GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43733 GIR_BuildMI, /*InsnID*/5, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43734 GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/RegState::Define,
43735 GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43736 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
43737 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
43738 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/4, /*TempRegFlags*/0,
43739 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
43740 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::INSERT_SUBREG,
43741 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
43742 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
43743 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43744 GIR_AddImm, /*InsnID*/3, /*Imm*/17,
43745 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, ARM::DPR_VFP2RegClassID,
43746 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, ARM::DPR_VFP2RegClassID,
43747 GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, ARM::SPRRegClassID,
43748 GIR_BuildMI, /*InsnID*/2, /*Opcode*/ARM::VABSfd,
43749 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
43750 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
43751 GIR_AddImm, /*InsnID*/2, /*Imm*/14,
43752 GIR_AddRegister, /*InsnID*/2, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43753 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43754 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
43755 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
43756 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
43757 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
43759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
43760 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, ARM::ssub_0,
43761 GIR_EraseFromParent, /*InsnID*/0,
43762 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::SPRRegClassID,
43763 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, ARM::DPR_VFP2RegClassID,
43764 // GIR_Coverage, 2619,
43765 GIR_Done,
43766 // Label 2243: @117525
43767 GIM_Reject,
43768 // Label 2241: @117526
43769 GIM_Reject,
43770 // Label 2234: @117527
43771 GIM_Try, /*On fail goto*//*Label 2244*/ 117566, // Rule ID 665 //
43772 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
43773 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43776 // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
43777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSD,
43778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
43779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
43780 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43781 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43782 GIR_EraseFromParent, /*InsnID*/0,
43783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43784 // GIR_Coverage, 665,
43785 GIR_Done,
43786 // Label 2244: @117566
43787 GIM_Reject,
43788 // Label 2235: @117567
43789 GIM_Try, /*On fail goto*//*Label 2245*/ 117606, // Rule ID 1530 //
43790 GIM_CheckFeatures, GIFBS_HasNEON,
43791 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43794 // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
43795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfd,
43796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43797 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43798 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43799 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43800 GIR_EraseFromParent, /*InsnID*/0,
43801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43802 // GIR_Coverage, 1530,
43803 GIR_Done,
43804 // Label 2245: @117606
43805 GIM_Reject,
43806 // Label 2236: @117607
43807 GIM_Try, /*On fail goto*//*Label 2246*/ 117646, // Rule ID 1532 //
43808 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43809 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43812 // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
43813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShd,
43814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43816 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43817 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43818 GIR_EraseFromParent, /*InsnID*/0,
43819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43820 // GIR_Coverage, 1532,
43821 GIR_Done,
43822 // Label 2246: @117646
43823 GIM_Reject,
43824 // Label 2237: @117647
43825 GIM_Try, /*On fail goto*//*Label 2247*/ 117763,
43826 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
43827 GIM_Try, /*On fail goto*//*Label 2248*/ 117727, // Rule ID 3987 //
43828 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43830 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43831 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
43832 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43833 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
43834 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43835 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
43836 GIM_CheckIsSafeToFold, /*InsnID*/1,
43837 // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
43838 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43839 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43840 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf32,
43842 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43843 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
43844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
43845 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43846 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43847 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43848 GIR_EraseFromParent, /*InsnID*/0,
43849 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43850 // GIR_Coverage, 3987,
43851 GIR_Done,
43852 // Label 2248: @117727
43853 GIM_Try, /*On fail goto*//*Label 2249*/ 117762, // Rule ID 1531 //
43854 GIM_CheckFeatures, GIFBS_HasNEON,
43855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43857 // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
43858 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSfq,
43859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43861 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43862 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43863 GIR_EraseFromParent, /*InsnID*/0,
43864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43865 // GIR_Coverage, 1531,
43866 GIR_Done,
43867 // Label 2249: @117762
43868 GIM_Reject,
43869 // Label 2247: @117763
43870 GIM_Reject,
43871 // Label 2238: @117764
43872 GIM_Try, /*On fail goto*//*Label 2250*/ 117880,
43873 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
43874 GIM_Try, /*On fail goto*//*Label 2251*/ 117844, // Rule ID 3986 //
43875 GIM_CheckFeatures, GIFBS_HasMVEFloat,
43876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
43877 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43878 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
43879 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
43880 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
43881 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
43882 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
43883 GIM_CheckIsSafeToFold, /*InsnID*/1,
43884 // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
43885 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43886 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
43887 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
43888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VABDf16,
43889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
43890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
43891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
43892 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
43893 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43894 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
43895 GIR_EraseFromParent, /*InsnID*/0,
43896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43897 // GIR_Coverage, 3986,
43898 GIR_Done,
43899 // Label 2251: @117844
43900 GIM_Try, /*On fail goto*//*Label 2252*/ 117879, // Rule ID 1533 //
43901 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
43902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
43903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
43904 // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
43905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABShq,
43906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
43907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
43908 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
43909 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
43910 GIR_EraseFromParent, /*InsnID*/0,
43911 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43912 // GIR_Coverage, 1533,
43913 GIR_Done,
43914 // Label 2252: @117879
43915 GIM_Reject,
43916 // Label 2250: @117880
43917 GIM_Reject,
43918 // Label 2239: @117881
43919 GIM_Reject,
43920 // Label 41: @117882
43921 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2260*/ 118384,
43922 /*GILLT_s16*//*Label 2253*/ 117900,
43923 /*GILLT_s32*//*Label 2254*/ 117932,
43924 /*GILLT_s64*//*Label 2255*/ 117964,
43925 /*GILLT_v2s32*//*Label 2256*/ 117996, 0, 0,
43926 /*GILLT_v4s16*//*Label 2257*/ 118028,
43927 /*GILLT_v4s32*//*Label 2258*/ 118060, 0, 0, 0,
43928 /*GILLT_v8s16*//*Label 2259*/ 118222,
43929 // Label 2253: @117900
43930 GIM_Try, /*On fail goto*//*Label 2261*/ 117931, // Rule ID 656 //
43931 GIM_CheckFeatures, GIFBS_HasFullFP16,
43932 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
43933 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
43934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
43935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
43936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
43937 // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43938 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMH,
43939 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43940 // GIR_Coverage, 656,
43941 GIR_Done,
43942 // Label 2261: @117931
43943 GIM_Reject,
43944 // Label 2254: @117932
43945 GIM_Try, /*On fail goto*//*Label 2262*/ 117963, // Rule ID 657 //
43946 GIM_CheckFeatures, GIFBS_HasFPARMv8,
43947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
43948 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
43949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
43950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
43951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
43952 // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43953 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMS,
43954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43955 // GIR_Coverage, 657,
43956 GIR_Done,
43957 // Label 2262: @117963
43958 GIM_Reject,
43959 // Label 2255: @117964
43960 GIM_Try, /*On fail goto*//*Label 2263*/ 117995, // Rule ID 658 //
43961 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
43962 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
43963 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
43964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
43967 // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43968 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMINNMD,
43969 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43970 // GIR_Coverage, 658,
43971 GIR_Done,
43972 // Label 2263: @117995
43973 GIM_Reject,
43974 // Label 2256: @117996
43975 GIM_Try, /*On fail goto*//*Label 2264*/ 118027, // Rule ID 1249 //
43976 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
43977 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
43978 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
43979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
43982 // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43983 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDf,
43984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
43985 // GIR_Coverage, 1249,
43986 GIR_Done,
43987 // Label 2264: @118027
43988 GIM_Reject,
43989 // Label 2257: @118028
43990 GIM_Try, /*On fail goto*//*Label 2265*/ 118059, // Rule ID 1251 //
43991 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
43992 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
43993 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
43994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
43995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
43996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
43997 // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43998 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNDh,
43999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44000 // GIR_Coverage, 1251,
44001 GIR_Done,
44002 // Label 2265: @118059
44003 GIM_Reject,
44004 // Label 2258: @118060
44005 GIM_Try, /*On fail goto*//*Label 2266*/ 118221,
44006 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44007 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
44008 GIM_Try, /*On fail goto*//*Label 2267*/ 118140, // Rule ID 4064 //
44009 GIM_CheckFeatures, GIFBS_HasMVEInt,
44010 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
44011 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44012 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
44013 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44014 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44015 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
44016 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
44017 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
44018 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44019 GIM_CheckIsSafeToFold, /*InsnID*/1,
44020 GIM_CheckIsSafeToFold, /*InsnID*/2,
44021 // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
44022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMAf32,
44023 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
44026 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44027 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44028 GIR_EraseFromParent, /*InsnID*/0,
44029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44030 // GIR_Coverage, 4064,
44031 GIR_Done,
44032 // Label 2267: @118140
44033 GIM_Try, /*On fail goto*//*Label 2268*/ 118163, // Rule ID 1250 //
44034 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
44035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44038 // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
44039 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQf,
44040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44041 // GIR_Coverage, 1250,
44042 GIR_Done,
44043 // Label 2268: @118163
44044 GIM_Try, /*On fail goto*//*Label 2269*/ 118220, // Rule ID 3282 //
44045 GIM_CheckFeatures, GIFBS_HasMVEFloat,
44046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44049 // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
44050 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44051 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44052 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf32,
44054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44057 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44058 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44059 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44060 GIR_EraseFromParent, /*InsnID*/0,
44061 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44062 // GIR_Coverage, 3282,
44063 GIR_Done,
44064 // Label 2269: @118220
44065 GIM_Reject,
44066 // Label 2266: @118221
44067 GIM_Reject,
44068 // Label 2259: @118222
44069 GIM_Try, /*On fail goto*//*Label 2270*/ 118383,
44070 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44071 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
44072 GIM_Try, /*On fail goto*//*Label 2271*/ 118302, // Rule ID 4066 //
44073 GIM_CheckFeatures, GIFBS_HasMVEInt,
44074 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
44075 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44076 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
44077 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44078 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44079 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
44080 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
44081 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
44082 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44083 GIM_CheckIsSafeToFold, /*InsnID*/1,
44084 GIM_CheckIsSafeToFold, /*InsnID*/2,
44085 // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
44086 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMAf16,
44087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
44090 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44091 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44092 GIR_EraseFromParent, /*InsnID*/0,
44093 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44094 // GIR_Coverage, 4066,
44095 GIR_Done,
44096 // Label 2271: @118302
44097 GIM_Try, /*On fail goto*//*Label 2272*/ 118325, // Rule ID 1252 //
44098 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
44099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44102 // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
44103 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMINNMNQh,
44104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44105 // GIR_Coverage, 1252,
44106 GIR_Done,
44107 // Label 2272: @118325
44108 GIM_Try, /*On fail goto*//*Label 2273*/ 118382, // Rule ID 3285 //
44109 GIM_CheckFeatures, GIFBS_HasMVEFloat,
44110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44113 // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
44114 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44115 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44116 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINNMf16,
44118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44121 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44122 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44123 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44124 GIR_EraseFromParent, /*InsnID*/0,
44125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44126 // GIR_Coverage, 3285,
44127 GIR_Done,
44128 // Label 2273: @118382
44129 GIM_Reject,
44130 // Label 2270: @118383
44131 GIM_Reject,
44132 // Label 2260: @118384
44133 GIM_Reject,
44134 // Label 42: @118385
44135 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2281*/ 118887,
44136 /*GILLT_s16*//*Label 2274*/ 118403,
44137 /*GILLT_s32*//*Label 2275*/ 118435,
44138 /*GILLT_s64*//*Label 2276*/ 118467,
44139 /*GILLT_v2s32*//*Label 2277*/ 118499, 0, 0,
44140 /*GILLT_v4s16*//*Label 2278*/ 118531,
44141 /*GILLT_v4s32*//*Label 2279*/ 118563, 0, 0, 0,
44142 /*GILLT_v8s16*//*Label 2280*/ 118725,
44143 // Label 2274: @118403
44144 GIM_Try, /*On fail goto*//*Label 2282*/ 118434, // Rule ID 653 //
44145 GIM_CheckFeatures, GIFBS_HasFullFP16,
44146 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
44147 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
44148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
44149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
44150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
44151 // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
44152 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMH,
44153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44154 // GIR_Coverage, 653,
44155 GIR_Done,
44156 // Label 2282: @118434
44157 GIM_Reject,
44158 // Label 2275: @118435
44159 GIM_Try, /*On fail goto*//*Label 2283*/ 118466, // Rule ID 654 //
44160 GIM_CheckFeatures, GIFBS_HasFPARMv8,
44161 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
44162 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
44163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
44164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
44165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
44166 // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
44167 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMS,
44168 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44169 // GIR_Coverage, 654,
44170 GIR_Done,
44171 // Label 2283: @118466
44172 GIM_Reject,
44173 // Label 2276: @118467
44174 GIM_Try, /*On fail goto*//*Label 2284*/ 118498, // Rule ID 655 //
44175 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
44176 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
44177 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
44178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44181 // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
44182 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VFP_VMAXNMD,
44183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44184 // GIR_Coverage, 655,
44185 GIR_Done,
44186 // Label 2284: @118498
44187 GIM_Reject,
44188 // Label 2277: @118499
44189 GIM_Try, /*On fail goto*//*Label 2285*/ 118530, // Rule ID 1229 //
44190 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
44191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44192 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
44193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44196 // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
44197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDf,
44198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44199 // GIR_Coverage, 1229,
44200 GIR_Done,
44201 // Label 2285: @118530
44202 GIM_Reject,
44203 // Label 2278: @118531
44204 GIM_Try, /*On fail goto*//*Label 2286*/ 118562, // Rule ID 1231 //
44205 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
44206 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44207 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
44208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44211 // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
44212 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNDh,
44213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44214 // GIR_Coverage, 1231,
44215 GIR_Done,
44216 // Label 2286: @118562
44217 GIM_Reject,
44218 // Label 2279: @118563
44219 GIM_Try, /*On fail goto*//*Label 2287*/ 118724,
44220 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44221 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
44222 GIM_Try, /*On fail goto*//*Label 2288*/ 118643, // Rule ID 4060 //
44223 GIM_CheckFeatures, GIFBS_HasMVEInt,
44224 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
44225 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44226 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
44227 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44228 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44229 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
44230 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
44231 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
44232 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44233 GIM_CheckIsSafeToFold, /*InsnID*/1,
44234 GIM_CheckIsSafeToFold, /*InsnID*/2,
44235 // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
44236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMAf32,
44237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
44240 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44241 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44242 GIR_EraseFromParent, /*InsnID*/0,
44243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44244 // GIR_Coverage, 4060,
44245 GIR_Done,
44246 // Label 2288: @118643
44247 GIM_Try, /*On fail goto*//*Label 2289*/ 118666, // Rule ID 1230 //
44248 GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
44249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44252 // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
44253 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQf,
44254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44255 // GIR_Coverage, 1230,
44256 GIR_Done,
44257 // Label 2289: @118666
44258 GIM_Try, /*On fail goto*//*Label 2290*/ 118723, // Rule ID 3024 //
44259 GIM_CheckFeatures, GIFBS_HasMVEFloat,
44260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44263 // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
44264 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44265 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44266 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf32,
44268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44271 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44272 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44273 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44274 GIR_EraseFromParent, /*InsnID*/0,
44275 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44276 // GIR_Coverage, 3024,
44277 GIR_Done,
44278 // Label 2290: @118723
44279 GIM_Reject,
44280 // Label 2287: @118724
44281 GIM_Reject,
44282 // Label 2280: @118725
44283 GIM_Try, /*On fail goto*//*Label 2291*/ 118886,
44284 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44285 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
44286 GIM_Try, /*On fail goto*//*Label 2292*/ 118805, // Rule ID 4062 //
44287 GIM_CheckFeatures, GIFBS_HasMVEInt,
44288 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/1, /*OtherOpIdx*/1,
44289 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44290 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FABS,
44291 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44292 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44293 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
44294 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FABS,
44295 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
44296 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44297 GIM_CheckIsSafeToFold, /*InsnID*/1,
44298 GIM_CheckIsSafeToFold, /*InsnID*/2,
44299 // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
44300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMAf16,
44301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
44303 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
44304 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44305 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44306 GIR_EraseFromParent, /*InsnID*/0,
44307 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44308 // GIR_Coverage, 4062,
44309 GIR_Done,
44310 // Label 2292: @118805
44311 GIM_Try, /*On fail goto*//*Label 2293*/ 118828, // Rule ID 1232 //
44312 GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
44313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44316 // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
44317 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::NEON_VMAXNMNQh,
44318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44319 // GIR_Coverage, 1232,
44320 GIR_Done,
44321 // Label 2293: @118828
44322 GIM_Try, /*On fail goto*//*Label 2294*/ 118885, // Rule ID 3279 //
44323 GIM_CheckFeatures, GIFBS_HasMVEFloat,
44324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44327 // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
44328 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44329 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44330 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXNMf16,
44332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44335 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44336 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44337 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44338 GIR_EraseFromParent, /*InsnID*/0,
44339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44340 // GIR_Coverage, 3279,
44341 GIR_Done,
44342 // Label 2294: @118885
44343 GIM_Reject,
44344 // Label 2291: @118886
44345 GIM_Reject,
44346 // Label 2281: @118887
44347 GIM_Reject,
44348 // Label 43: @118888
44349 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2301*/ 119398,
44350 /*GILLT_v2s32*//*Label 2295*/ 118906, 0, 0,
44351 /*GILLT_v4s16*//*Label 2296*/ 118958,
44352 /*GILLT_v4s32*//*Label 2297*/ 119010, 0, 0,
44353 /*GILLT_v8s8*//*Label 2298*/ 119122,
44354 /*GILLT_v8s16*//*Label 2299*/ 119174, 0, 0,
44355 /*GILLT_v16s8*//*Label 2300*/ 119286,
44356 // Label 2295: @118906
44357 GIM_Try, /*On fail goto*//*Label 2302*/ 118957, // Rule ID 1234 //
44358 GIM_CheckFeatures, GIFBS_HasNEON,
44359 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44360 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
44361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44364 // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv2i32,
44366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44367 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44369 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44370 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44371 GIR_EraseFromParent, /*InsnID*/0,
44372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44373 // GIR_Coverage, 1234,
44374 GIR_Done,
44375 // Label 2302: @118957
44376 GIM_Reject,
44377 // Label 2296: @118958
44378 GIM_Try, /*On fail goto*//*Label 2303*/ 119009, // Rule ID 1233 //
44379 GIM_CheckFeatures, GIFBS_HasNEON,
44380 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44381 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
44382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44385 // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i16,
44387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44390 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44391 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44392 GIR_EraseFromParent, /*InsnID*/0,
44393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44394 // GIR_Coverage, 1233,
44395 GIR_Done,
44396 // Label 2303: @119009
44397 GIM_Reject,
44398 // Label 2297: @119010
44399 GIM_Try, /*On fail goto*//*Label 2304*/ 119121,
44400 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44401 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
44402 GIM_Try, /*On fail goto*//*Label 2305*/ 119063, // Rule ID 1236 //
44403 GIM_CheckFeatures, GIFBS_HasNEON,
44404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44407 // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv4i32,
44409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44412 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44413 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44414 GIR_EraseFromParent, /*InsnID*/0,
44415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44416 // GIR_Coverage, 1236,
44417 GIR_Done,
44418 // Label 2305: @119063
44419 GIM_Try, /*On fail goto*//*Label 2306*/ 119120, // Rule ID 3294 //
44420 GIM_CheckFeatures, GIFBS_HasMVEInt,
44421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44424 // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44425 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44426 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44427 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs32,
44429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44432 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44433 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44434 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44435 GIR_EraseFromParent, /*InsnID*/0,
44436 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44437 // GIR_Coverage, 3294,
44438 GIR_Done,
44439 // Label 2306: @119120
44440 GIM_Reject,
44441 // Label 2304: @119121
44442 GIM_Reject,
44443 // Label 2298: @119122
44444 GIM_Try, /*On fail goto*//*Label 2307*/ 119173, // Rule ID 1237 //
44445 GIM_CheckFeatures, GIFBS_HasNEON,
44446 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
44447 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
44448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44451 // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i8,
44453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44456 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44457 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44458 GIR_EraseFromParent, /*InsnID*/0,
44459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44460 // GIR_Coverage, 1237,
44461 GIR_Done,
44462 // Label 2307: @119173
44463 GIM_Reject,
44464 // Label 2299: @119174
44465 GIM_Try, /*On fail goto*//*Label 2308*/ 119285,
44466 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44467 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
44468 GIM_Try, /*On fail goto*//*Label 2309*/ 119227, // Rule ID 1235 //
44469 GIM_CheckFeatures, GIFBS_HasNEON,
44470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44473 // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv8i16,
44475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44478 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44479 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44480 GIR_EraseFromParent, /*InsnID*/0,
44481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44482 // GIR_Coverage, 1235,
44483 GIR_Done,
44484 // Label 2309: @119227
44485 GIM_Try, /*On fail goto*//*Label 2310*/ 119284, // Rule ID 3291 //
44486 GIM_CheckFeatures, GIFBS_HasMVEInt,
44487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44490 // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44491 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44492 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44493 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs16,
44495 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44496 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44497 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44498 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44499 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44500 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44501 GIR_EraseFromParent, /*InsnID*/0,
44502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44503 // GIR_Coverage, 3291,
44504 GIR_Done,
44505 // Label 2310: @119284
44506 GIM_Reject,
44507 // Label 2308: @119285
44508 GIM_Reject,
44509 // Label 2300: @119286
44510 GIM_Try, /*On fail goto*//*Label 2311*/ 119397,
44511 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
44512 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
44513 GIM_Try, /*On fail goto*//*Label 2312*/ 119339, // Rule ID 1238 //
44514 GIM_CheckFeatures, GIFBS_HasNEON,
44515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44518 // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44519 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINsv16i8,
44520 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44523 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44524 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44525 GIR_EraseFromParent, /*InsnID*/0,
44526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44527 // GIR_Coverage, 1238,
44528 GIR_Done,
44529 // Label 2312: @119339
44530 GIM_Try, /*On fail goto*//*Label 2313*/ 119396, // Rule ID 3288 //
44531 GIM_CheckFeatures, GIFBS_HasMVEInt,
44532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44535 // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44536 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINs8,
44540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44543 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44544 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44545 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44546 GIR_EraseFromParent, /*InsnID*/0,
44547 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44548 // GIR_Coverage, 3288,
44549 GIR_Done,
44550 // Label 2313: @119396
44551 GIM_Reject,
44552 // Label 2311: @119397
44553 GIM_Reject,
44554 // Label 2301: @119398
44555 GIM_Reject,
44556 // Label 44: @119399
44557 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2320*/ 119909,
44558 /*GILLT_v2s32*//*Label 2314*/ 119417, 0, 0,
44559 /*GILLT_v4s16*//*Label 2315*/ 119469,
44560 /*GILLT_v4s32*//*Label 2316*/ 119521, 0, 0,
44561 /*GILLT_v8s8*//*Label 2317*/ 119633,
44562 /*GILLT_v8s16*//*Label 2318*/ 119685, 0, 0,
44563 /*GILLT_v16s8*//*Label 2319*/ 119797,
44564 // Label 2314: @119417
44565 GIM_Try, /*On fail goto*//*Label 2321*/ 119468, // Rule ID 1214 //
44566 GIM_CheckFeatures, GIFBS_HasNEON,
44567 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44568 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
44569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44572 // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44573 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv2i32,
44574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44575 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44576 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44577 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44578 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44579 GIR_EraseFromParent, /*InsnID*/0,
44580 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44581 // GIR_Coverage, 1214,
44582 GIR_Done,
44583 // Label 2321: @119468
44584 GIM_Reject,
44585 // Label 2315: @119469
44586 GIM_Try, /*On fail goto*//*Label 2322*/ 119520, // Rule ID 1213 //
44587 GIM_CheckFeatures, GIFBS_HasNEON,
44588 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44589 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
44590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44593 // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i16,
44595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44598 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44599 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44600 GIR_EraseFromParent, /*InsnID*/0,
44601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44602 // GIR_Coverage, 1213,
44603 GIR_Done,
44604 // Label 2322: @119520
44605 GIM_Reject,
44606 // Label 2316: @119521
44607 GIM_Try, /*On fail goto*//*Label 2323*/ 119632,
44608 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44609 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
44610 GIM_Try, /*On fail goto*//*Label 2324*/ 119574, // Rule ID 1216 //
44611 GIM_CheckFeatures, GIFBS_HasNEON,
44612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44615 // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv4i32,
44617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44620 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44621 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44622 GIR_EraseFromParent, /*InsnID*/0,
44623 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44624 // GIR_Coverage, 1216,
44625 GIR_Done,
44626 // Label 2324: @119574
44627 GIM_Try, /*On fail goto*//*Label 2325*/ 119631, // Rule ID 3312 //
44628 GIM_CheckFeatures, GIFBS_HasMVEInt,
44629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44632 // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44633 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44634 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44635 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs32,
44637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44639 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44640 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44641 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44642 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44643 GIR_EraseFromParent, /*InsnID*/0,
44644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44645 // GIR_Coverage, 3312,
44646 GIR_Done,
44647 // Label 2325: @119631
44648 GIM_Reject,
44649 // Label 2323: @119632
44650 GIM_Reject,
44651 // Label 2317: @119633
44652 GIM_Try, /*On fail goto*//*Label 2326*/ 119684, // Rule ID 1217 //
44653 GIM_CheckFeatures, GIFBS_HasNEON,
44654 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
44655 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
44656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44659 // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i8,
44661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44664 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44665 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44666 GIR_EraseFromParent, /*InsnID*/0,
44667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44668 // GIR_Coverage, 1217,
44669 GIR_Done,
44670 // Label 2326: @119684
44671 GIM_Reject,
44672 // Label 2318: @119685
44673 GIM_Try, /*On fail goto*//*Label 2327*/ 119796,
44674 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44675 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
44676 GIM_Try, /*On fail goto*//*Label 2328*/ 119738, // Rule ID 1215 //
44677 GIM_CheckFeatures, GIFBS_HasNEON,
44678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44681 // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv8i16,
44683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44686 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44687 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44688 GIR_EraseFromParent, /*InsnID*/0,
44689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44690 // GIR_Coverage, 1215,
44691 GIR_Done,
44692 // Label 2328: @119738
44693 GIM_Try, /*On fail goto*//*Label 2329*/ 119795, // Rule ID 3309 //
44694 GIM_CheckFeatures, GIFBS_HasMVEInt,
44695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44698 // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44699 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44700 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs16,
44703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44706 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44707 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44708 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44709 GIR_EraseFromParent, /*InsnID*/0,
44710 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44711 // GIR_Coverage, 3309,
44712 GIR_Done,
44713 // Label 2329: @119795
44714 GIM_Reject,
44715 // Label 2327: @119796
44716 GIM_Reject,
44717 // Label 2319: @119797
44718 GIM_Try, /*On fail goto*//*Label 2330*/ 119908,
44719 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
44720 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
44721 GIM_Try, /*On fail goto*//*Label 2331*/ 119850, // Rule ID 1218 //
44722 GIM_CheckFeatures, GIFBS_HasNEON,
44723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44726 // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXsv16i8,
44728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44731 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44732 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44733 GIR_EraseFromParent, /*InsnID*/0,
44734 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44735 // GIR_Coverage, 1218,
44736 GIR_Done,
44737 // Label 2331: @119850
44738 GIM_Try, /*On fail goto*//*Label 2332*/ 119907, // Rule ID 3306 //
44739 GIM_CheckFeatures, GIFBS_HasMVEInt,
44740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44743 // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44744 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44745 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44746 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXs8,
44748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44751 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44752 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44753 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44754 GIR_EraseFromParent, /*InsnID*/0,
44755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44756 // GIR_Coverage, 3306,
44757 GIR_Done,
44758 // Label 2332: @119907
44759 GIM_Reject,
44760 // Label 2330: @119908
44761 GIM_Reject,
44762 // Label 2320: @119909
44763 GIM_Reject,
44764 // Label 45: @119910
44765 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2339*/ 120762,
44766 /*GILLT_v2s32*//*Label 2333*/ 119928, 0, 0,
44767 /*GILLT_v4s16*//*Label 2334*/ 119980,
44768 /*GILLT_v4s32*//*Label 2335*/ 120032, 0, 0,
44769 /*GILLT_v8s8*//*Label 2336*/ 120258,
44770 /*GILLT_v8s16*//*Label 2337*/ 120310, 0, 0,
44771 /*GILLT_v16s8*//*Label 2338*/ 120536,
44772 // Label 2333: @119928
44773 GIM_Try, /*On fail goto*//*Label 2340*/ 119979, // Rule ID 1240 //
44774 GIM_CheckFeatures, GIFBS_HasNEON,
44775 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
44776 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
44777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44780 // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44781 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv2i32,
44782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44785 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44786 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44787 GIR_EraseFromParent, /*InsnID*/0,
44788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44789 // GIR_Coverage, 1240,
44790 GIR_Done,
44791 // Label 2340: @119979
44792 GIM_Reject,
44793 // Label 2334: @119980
44794 GIM_Try, /*On fail goto*//*Label 2341*/ 120031, // Rule ID 1239 //
44795 GIM_CheckFeatures, GIFBS_HasNEON,
44796 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
44797 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
44798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44801 // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i16,
44803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44806 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44807 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44808 GIR_EraseFromParent, /*InsnID*/0,
44809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44810 // GIR_Coverage, 1239,
44811 GIR_Done,
44812 // Label 2341: @120031
44813 GIM_Reject,
44814 // Label 2335: @120032
44815 GIM_Try, /*On fail goto*//*Label 2342*/ 120257,
44816 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
44817 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
44818 GIM_Try, /*On fail goto*//*Label 2343*/ 120099, // Rule ID 5826 //
44819 GIM_CheckFeatures, GIFBS_HasMVEInt,
44820 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
44821 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44822 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
44823 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44824 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44826 GIM_CheckIsSafeToFold, /*InsnID*/1,
44827 // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44828 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs32,
44829 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
44830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
44831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44832 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44833 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44834 GIR_EraseFromParent, /*InsnID*/0,
44835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44836 // GIR_Coverage, 5826,
44837 GIR_Done,
44838 // Label 2343: @120099
44839 GIM_Try, /*On fail goto*//*Label 2344*/ 120156, // Rule ID 3663 //
44840 GIM_CheckFeatures, GIFBS_HasMVEInt,
44841 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
44842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44843 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44844 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
44845 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44846 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44847 GIM_CheckIsSafeToFold, /*InsnID*/1,
44848 // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs32,
44850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
44851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
44852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44853 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44854 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44855 GIR_EraseFromParent, /*InsnID*/0,
44856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44857 // GIR_Coverage, 3663,
44858 GIR_Done,
44859 // Label 2344: @120156
44860 GIM_Try, /*On fail goto*//*Label 2345*/ 120199, // Rule ID 1242 //
44861 GIM_CheckFeatures, GIFBS_HasNEON,
44862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44865 // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44866 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv4i32,
44867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44870 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44871 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44872 GIR_EraseFromParent, /*InsnID*/0,
44873 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44874 // GIR_Coverage, 1242,
44875 GIR_Done,
44876 // Label 2345: @120199
44877 GIM_Try, /*On fail goto*//*Label 2346*/ 120256, // Rule ID 3303 //
44878 GIM_CheckFeatures, GIFBS_HasMVEInt,
44879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44882 // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44883 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44884 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44885 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44886 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu32,
44887 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44890 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44891 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44892 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
44893 GIR_EraseFromParent, /*InsnID*/0,
44894 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44895 // GIR_Coverage, 3303,
44896 GIR_Done,
44897 // Label 2346: @120256
44898 GIM_Reject,
44899 // Label 2342: @120257
44900 GIM_Reject,
44901 // Label 2336: @120258
44902 GIM_Try, /*On fail goto*//*Label 2347*/ 120309, // Rule ID 1243 //
44903 GIM_CheckFeatures, GIFBS_HasNEON,
44904 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
44905 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
44906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
44907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
44908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
44909 // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44910 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i8,
44911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44912 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44914 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44915 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44916 GIR_EraseFromParent, /*InsnID*/0,
44917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44918 // GIR_Coverage, 1243,
44919 GIR_Done,
44920 // Label 2347: @120309
44921 GIM_Reject,
44922 // Label 2337: @120310
44923 GIM_Try, /*On fail goto*//*Label 2348*/ 120535,
44924 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
44925 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
44926 GIM_Try, /*On fail goto*//*Label 2349*/ 120377, // Rule ID 5825 //
44927 GIM_CheckFeatures, GIFBS_HasMVEInt,
44928 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
44929 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44930 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
44931 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44932 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44934 GIM_CheckIsSafeToFold, /*InsnID*/1,
44935 // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs16,
44937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
44938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
44939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44940 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44941 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44942 GIR_EraseFromParent, /*InsnID*/0,
44943 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44944 // GIR_Coverage, 5825,
44945 GIR_Done,
44946 // Label 2349: @120377
44947 GIM_Try, /*On fail goto*//*Label 2350*/ 120434, // Rule ID 3661 //
44948 GIM_CheckFeatures, GIFBS_HasMVEInt,
44949 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
44950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44951 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44952 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
44953 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44954 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44955 GIM_CheckIsSafeToFold, /*InsnID*/1,
44956 // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44957 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs16,
44958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
44959 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
44960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44961 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44962 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44963 GIR_EraseFromParent, /*InsnID*/0,
44964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44965 // GIR_Coverage, 3661,
44966 GIR_Done,
44967 // Label 2350: @120434
44968 GIM_Try, /*On fail goto*//*Label 2351*/ 120477, // Rule ID 1241 //
44969 GIM_CheckFeatures, GIFBS_HasNEON,
44970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
44971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
44972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
44973 // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv8i16,
44975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
44976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
44977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
44978 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
44979 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
44980 GIR_EraseFromParent, /*InsnID*/0,
44981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
44982 // GIR_Coverage, 1241,
44983 GIR_Done,
44984 // Label 2351: @120477
44985 GIM_Try, /*On fail goto*//*Label 2352*/ 120534, // Rule ID 3300 //
44986 GIM_CheckFeatures, GIFBS_HasMVEInt,
44987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
44988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
44989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
44990 // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44991 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44992 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
44993 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
44994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu16,
44995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
44996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
44997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
44998 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
44999 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45000 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45001 GIR_EraseFromParent, /*InsnID*/0,
45002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45003 // GIR_Coverage, 3300,
45004 GIR_Done,
45005 // Label 2352: @120534
45006 GIM_Reject,
45007 // Label 2348: @120535
45008 GIM_Reject,
45009 // Label 2338: @120536
45010 GIM_Try, /*On fail goto*//*Label 2353*/ 120761,
45011 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
45012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
45013 GIM_Try, /*On fail goto*//*Label 2354*/ 120603, // Rule ID 5824 //
45014 GIM_CheckFeatures, GIFBS_HasMVEInt,
45015 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
45016 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45017 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45018 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
45019 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45021 GIM_CheckIsSafeToFold, /*InsnID*/1,
45022 // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
45023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs8,
45024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45027 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45028 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45029 GIR_EraseFromParent, /*InsnID*/0,
45030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45031 // GIR_Coverage, 5824,
45032 GIR_Done,
45033 // Label 2354: @120603
45034 GIM_Try, /*On fail goto*//*Label 2355*/ 120660, // Rule ID 3659 //
45035 GIM_CheckFeatures, GIFBS_HasMVEInt,
45036 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
45037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45038 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45039 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45040 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
45041 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45042 GIM_CheckIsSafeToFold, /*InsnID*/1,
45043 // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
45044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINAs8,
45045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45048 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45049 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45050 GIR_EraseFromParent, /*InsnID*/0,
45051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45052 // GIR_Coverage, 3659,
45053 GIR_Done,
45054 // Label 2355: @120660
45055 GIM_Try, /*On fail goto*//*Label 2356*/ 120703, // Rule ID 1244 //
45056 GIM_CheckFeatures, GIFBS_HasNEON,
45057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45060 // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
45061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMINuv16i8,
45062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45065 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45066 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45067 GIR_EraseFromParent, /*InsnID*/0,
45068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45069 // GIR_Coverage, 1244,
45070 GIR_Done,
45071 // Label 2356: @120703
45072 GIM_Try, /*On fail goto*//*Label 2357*/ 120760, // Rule ID 3297 //
45073 GIM_CheckFeatures, GIFBS_HasMVEInt,
45074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45077 // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
45078 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45079 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45080 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMINu8,
45082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45084 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45085 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45086 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45087 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45088 GIR_EraseFromParent, /*InsnID*/0,
45089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45090 // GIR_Coverage, 3297,
45091 GIR_Done,
45092 // Label 2357: @120760
45093 GIM_Reject,
45094 // Label 2353: @120761
45095 GIM_Reject,
45096 // Label 2339: @120762
45097 GIM_Reject,
45098 // Label 46: @120763
45099 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2364*/ 121615,
45100 /*GILLT_v2s32*//*Label 2358*/ 120781, 0, 0,
45101 /*GILLT_v4s16*//*Label 2359*/ 120833,
45102 /*GILLT_v4s32*//*Label 2360*/ 120885, 0, 0,
45103 /*GILLT_v8s8*//*Label 2361*/ 121111,
45104 /*GILLT_v8s16*//*Label 2362*/ 121163, 0, 0,
45105 /*GILLT_v16s8*//*Label 2363*/ 121389,
45106 // Label 2358: @120781
45107 GIM_Try, /*On fail goto*//*Label 2365*/ 120832, // Rule ID 1220 //
45108 GIM_CheckFeatures, GIFBS_HasNEON,
45109 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45110 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
45111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45114 // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
45115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv2i32,
45116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45119 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45120 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45121 GIR_EraseFromParent, /*InsnID*/0,
45122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45123 // GIR_Coverage, 1220,
45124 GIR_Done,
45125 // Label 2365: @120832
45126 GIM_Reject,
45127 // Label 2359: @120833
45128 GIM_Try, /*On fail goto*//*Label 2366*/ 120884, // Rule ID 1219 //
45129 GIM_CheckFeatures, GIFBS_HasNEON,
45130 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45131 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
45132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45135 // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
45136 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i16,
45137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45138 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45140 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45141 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45142 GIR_EraseFromParent, /*InsnID*/0,
45143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45144 // GIR_Coverage, 1219,
45145 GIR_Done,
45146 // Label 2366: @120884
45147 GIM_Reject,
45148 // Label 2360: @120885
45149 GIM_Try, /*On fail goto*//*Label 2367*/ 121110,
45150 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45151 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
45152 GIM_Try, /*On fail goto*//*Label 2368*/ 120952, // Rule ID 5829 //
45153 GIM_CheckFeatures, GIFBS_HasMVEInt,
45154 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
45155 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45156 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45157 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45158 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45160 GIM_CheckIsSafeToFold, /*InsnID*/1,
45161 // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
45162 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs32,
45163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45166 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45167 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45168 GIR_EraseFromParent, /*InsnID*/0,
45169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45170 // GIR_Coverage, 5829,
45171 GIR_Done,
45172 // Label 2368: @120952
45173 GIM_Try, /*On fail goto*//*Label 2369*/ 121009, // Rule ID 3669 //
45174 GIM_CheckFeatures, GIFBS_HasMVEInt,
45175 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
45176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45177 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45178 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45179 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45180 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45181 GIM_CheckIsSafeToFold, /*InsnID*/1,
45182 // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
45183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs32,
45184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45186 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45187 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45188 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45189 GIR_EraseFromParent, /*InsnID*/0,
45190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45191 // GIR_Coverage, 3669,
45192 GIR_Done,
45193 // Label 2369: @121009
45194 GIM_Try, /*On fail goto*//*Label 2370*/ 121052, // Rule ID 1222 //
45195 GIM_CheckFeatures, GIFBS_HasNEON,
45196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45199 // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
45200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv4i32,
45201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45202 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45203 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45204 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45205 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45206 GIR_EraseFromParent, /*InsnID*/0,
45207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45208 // GIR_Coverage, 1222,
45209 GIR_Done,
45210 // Label 2370: @121052
45211 GIM_Try, /*On fail goto*//*Label 2371*/ 121109, // Rule ID 3321 //
45212 GIM_CheckFeatures, GIFBS_HasMVEInt,
45213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45216 // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
45217 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45218 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45219 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45220 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu32,
45221 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45222 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45224 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45225 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45226 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45227 GIR_EraseFromParent, /*InsnID*/0,
45228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45229 // GIR_Coverage, 3321,
45230 GIR_Done,
45231 // Label 2371: @121109
45232 GIM_Reject,
45233 // Label 2367: @121110
45234 GIM_Reject,
45235 // Label 2361: @121111
45236 GIM_Try, /*On fail goto*//*Label 2372*/ 121162, // Rule ID 1223 //
45237 GIM_CheckFeatures, GIFBS_HasNEON,
45238 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
45239 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
45240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
45243 // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
45244 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i8,
45245 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45248 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45249 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45250 GIR_EraseFromParent, /*InsnID*/0,
45251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45252 // GIR_Coverage, 1223,
45253 GIR_Done,
45254 // Label 2372: @121162
45255 GIM_Reject,
45256 // Label 2362: @121163
45257 GIM_Try, /*On fail goto*//*Label 2373*/ 121388,
45258 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45259 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
45260 GIM_Try, /*On fail goto*//*Label 2374*/ 121230, // Rule ID 5828 //
45261 GIM_CheckFeatures, GIFBS_HasMVEInt,
45262 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
45263 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45264 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45265 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45266 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45268 GIM_CheckIsSafeToFold, /*InsnID*/1,
45269 // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
45270 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs16,
45271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45274 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45275 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45276 GIR_EraseFromParent, /*InsnID*/0,
45277 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45278 // GIR_Coverage, 5828,
45279 GIR_Done,
45280 // Label 2374: @121230
45281 GIM_Try, /*On fail goto*//*Label 2375*/ 121287, // Rule ID 3667 //
45282 GIM_CheckFeatures, GIFBS_HasMVEInt,
45283 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
45284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45285 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45286 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45287 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45288 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45289 GIM_CheckIsSafeToFold, /*InsnID*/1,
45290 // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
45291 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs16,
45292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45295 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45296 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45297 GIR_EraseFromParent, /*InsnID*/0,
45298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45299 // GIR_Coverage, 3667,
45300 GIR_Done,
45301 // Label 2375: @121287
45302 GIM_Try, /*On fail goto*//*Label 2376*/ 121330, // Rule ID 1221 //
45303 GIM_CheckFeatures, GIFBS_HasNEON,
45304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45307 // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
45308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv8i16,
45309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45312 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45313 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45314 GIR_EraseFromParent, /*InsnID*/0,
45315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45316 // GIR_Coverage, 1221,
45317 GIR_Done,
45318 // Label 2376: @121330
45319 GIM_Try, /*On fail goto*//*Label 2377*/ 121387, // Rule ID 3318 //
45320 GIM_CheckFeatures, GIFBS_HasMVEInt,
45321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45324 // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
45325 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45326 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45327 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu16,
45329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45332 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45333 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45334 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45335 GIR_EraseFromParent, /*InsnID*/0,
45336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45337 // GIR_Coverage, 3318,
45338 GIR_Done,
45339 // Label 2377: @121387
45340 GIM_Reject,
45341 // Label 2373: @121388
45342 GIM_Reject,
45343 // Label 2363: @121389
45344 GIM_Try, /*On fail goto*//*Label 2378*/ 121614,
45345 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
45346 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
45347 GIM_Try, /*On fail goto*//*Label 2379*/ 121456, // Rule ID 5827 //
45348 GIM_CheckFeatures, GIFBS_HasMVEInt,
45349 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
45350 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45351 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45352 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
45353 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45355 GIM_CheckIsSafeToFold, /*InsnID*/1,
45356 // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
45357 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs8,
45358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qd
45360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45361 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45362 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45363 GIR_EraseFromParent, /*InsnID*/0,
45364 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45365 // GIR_Coverage, 5827,
45366 GIR_Done,
45367 // Label 2379: @121456
45368 GIM_Try, /*On fail goto*//*Label 2380*/ 121513, // Rule ID 3665 //
45369 GIM_CheckFeatures, GIFBS_HasMVEInt,
45370 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
45371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45372 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45373 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ABS,
45374 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
45375 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45376 GIM_CheckIsSafeToFold, /*InsnID*/1,
45377 // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
45378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXAs8,
45379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qd
45381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45382 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45383 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45384 GIR_EraseFromParent, /*InsnID*/0,
45385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45386 // GIR_Coverage, 3665,
45387 GIR_Done,
45388 // Label 2380: @121513
45389 GIM_Try, /*On fail goto*//*Label 2381*/ 121556, // Rule ID 1224 //
45390 GIM_CheckFeatures, GIFBS_HasNEON,
45391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
45394 // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
45395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMAXuv16i8,
45396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
45398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
45399 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45400 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45401 GIR_EraseFromParent, /*InsnID*/0,
45402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45403 // GIR_Coverage, 1224,
45404 GIR_Done,
45405 // Label 2381: @121556
45406 GIM_Try, /*On fail goto*//*Label 2382*/ 121613, // Rule ID 3315 //
45407 GIM_CheckFeatures, GIFBS_HasMVEInt,
45408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::MQPRRegClassID,
45411 // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
45412 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45413 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45414 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VMAXu8,
45416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Qm
45418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Qn
45419 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45420 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45421 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45422 GIR_EraseFromParent, /*InsnID*/0,
45423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45424 // GIR_Coverage, 3315,
45425 GIR_Done,
45426 // Label 2382: @121613
45427 GIM_Reject,
45428 // Label 2378: @121614
45429 GIM_Reject,
45430 // Label 2364: @121615
45431 GIM_Reject,
45432 // Label 47: @121616
45433 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 15, /*)*//*default:*//*Label 2389*/ 122044,
45434 /*GILLT_v2s32*//*Label 2383*/ 121634, 0, 0,
45435 /*GILLT_v4s16*//*Label 2384*/ 121674,
45436 /*GILLT_v4s32*//*Label 2385*/ 121714, 0, 0,
45437 /*GILLT_v8s8*//*Label 2386*/ 121839,
45438 /*GILLT_v8s16*//*Label 2387*/ 121879, 0, 0,
45439 /*GILLT_v16s8*//*Label 2388*/ 122004,
45440 // Label 2383: @121634
45441 GIM_Try, /*On fail goto*//*Label 2390*/ 121673, // Rule ID 1526 //
45442 GIM_CheckFeatures, GIFBS_HasNEON,
45443 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45446 // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv2i32,
45448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45450 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45451 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45452 GIR_EraseFromParent, /*InsnID*/0,
45453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45454 // GIR_Coverage, 1526,
45455 GIR_Done,
45456 // Label 2390: @121673
45457 GIM_Reject,
45458 // Label 2384: @121674
45459 GIM_Try, /*On fail goto*//*Label 2391*/ 121713, // Rule ID 1525 //
45460 GIM_CheckFeatures, GIFBS_HasNEON,
45461 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45464 // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45465 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv4i16,
45466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45468 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45469 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45470 GIR_EraseFromParent, /*InsnID*/0,
45471 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45472 // GIR_Coverage, 1525,
45473 GIR_Done,
45474 // Label 2391: @121713
45475 GIM_Reject,
45476 // Label 2385: @121714
45477 GIM_Try, /*On fail goto*//*Label 2392*/ 121838,
45478 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45480 GIM_Try, /*On fail goto*//*Label 2393*/ 121806, // Rule ID 2488 //
45481 GIM_CheckFeatures, GIFBS_HasNEON,
45482 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45483 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
45484 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45485 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
45486 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
45487 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
45488 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
45489 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45490 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
45491 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
45492 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
45493 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45494 GIM_CheckIsSafeToFold, /*InsnID*/1,
45495 GIM_CheckIsSafeToFold, /*InsnID*/2,
45496 GIM_CheckIsSafeToFold, /*InsnID*/3,
45497 // (abs:{ *:[v4i32] } (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opB))) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
45498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
45499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
45501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
45502 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45503 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45504 GIR_EraseFromParent, /*InsnID*/0,
45505 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45506 // GIR_Coverage, 2488,
45507 GIR_Done,
45508 // Label 2393: @121806
45509 GIM_Try, /*On fail goto*//*Label 2394*/ 121837, // Rule ID 1529 //
45510 GIM_CheckFeatures, GIFBS_HasNEON,
45511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45512 // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45513 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv4i32,
45514 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45515 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45516 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45517 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45518 GIR_EraseFromParent, /*InsnID*/0,
45519 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45520 // GIR_Coverage, 1529,
45521 GIR_Done,
45522 // Label 2394: @121837
45523 GIM_Reject,
45524 // Label 2392: @121838
45525 GIM_Reject,
45526 // Label 2386: @121839
45527 GIM_Try, /*On fail goto*//*Label 2395*/ 121878, // Rule ID 1524 //
45528 GIM_CheckFeatures, GIFBS_HasNEON,
45529 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
45530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45532 // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv8i8,
45534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45536 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45537 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45538 GIR_EraseFromParent, /*InsnID*/0,
45539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45540 // GIR_Coverage, 1524,
45541 GIR_Done,
45542 // Label 2395: @121878
45543 GIM_Reject,
45544 // Label 2387: @121879
45545 GIM_Try, /*On fail goto*//*Label 2396*/ 122003,
45546 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45548 GIM_Try, /*On fail goto*//*Label 2397*/ 121971, // Rule ID 2487 //
45549 GIM_CheckFeatures, GIFBS_HasNEON,
45550 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45551 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
45552 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45553 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
45554 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
45555 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
45556 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
45557 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45558 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
45559 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT,
45560 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s8,
45561 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45562 GIM_CheckIsSafeToFold, /*InsnID*/1,
45563 GIM_CheckIsSafeToFold, /*InsnID*/2,
45564 GIM_CheckIsSafeToFold, /*InsnID*/3,
45565 // (abs:{ *:[v8i16] } (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opB))) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
45566 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
45567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45568 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // opA
45569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // opB
45570 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45571 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45572 GIR_EraseFromParent, /*InsnID*/0,
45573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45574 // GIR_Coverage, 2487,
45575 GIR_Done,
45576 // Label 2397: @121971
45577 GIM_Try, /*On fail goto*//*Label 2398*/ 122002, // Rule ID 1528 //
45578 GIM_CheckFeatures, GIFBS_HasNEON,
45579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45580 // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv8i16,
45582 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45583 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45584 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45585 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45586 GIR_EraseFromParent, /*InsnID*/0,
45587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45588 // GIR_Coverage, 1528,
45589 GIR_Done,
45590 // Label 2398: @122002
45591 GIM_Reject,
45592 // Label 2396: @122003
45593 GIM_Reject,
45594 // Label 2388: @122004
45595 GIM_Try, /*On fail goto*//*Label 2399*/ 122043, // Rule ID 1527 //
45596 GIM_CheckFeatures, GIFBS_HasNEON,
45597 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
45598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45600 // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABSv16i8,
45602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45604 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45605 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45606 GIR_EraseFromParent, /*InsnID*/0,
45607 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45608 // GIR_Coverage, 1527,
45609 GIR_Done,
45610 // Label 2399: @122043
45611 GIM_Reject,
45612 // Label 2389: @122044
45613 GIM_Reject,
45614 // Label 48: @122045
45615 GIM_Try, /*On fail goto*//*Label 2400*/ 122108,
45616 GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
45617 GIM_Try, /*On fail goto*//*Label 2401*/ 122061, // Rule ID 32 //
45618 GIM_CheckFeatures, GIFBS_IsARM,
45619 // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target)
45620 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::B,
45621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45622 // GIR_Coverage, 32,
45623 GIR_Done,
45624 // Label 2401: @122061
45625 GIM_Try, /*On fail goto*//*Label 2402*/ 122084, // Rule ID 290 //
45626 GIM_CheckFeatures, GIFBS_IsThumb_IsThumb1Only,
45627 // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target)
45628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tB,
45629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
45630 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45631 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45632 GIR_EraseFromParent, /*InsnID*/0,
45633 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45634 // GIR_Coverage, 290,
45635 GIR_Done,
45636 // Label 2402: @122084
45637 GIM_Try, /*On fail goto*//*Label 2403*/ 122107, // Rule ID 593 //
45638 GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
45639 // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target)
45640 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2B,
45641 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
45642 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45643 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45644 GIR_EraseFromParent, /*InsnID*/0,
45645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45646 // GIR_Coverage, 593,
45647 GIR_Done,
45648 // Label 2403: @122107
45649 GIM_Reject,
45650 // Label 2400: @122108
45651 GIM_Reject,
45652 // Label 49: @122109
45653 GIM_Try, /*On fail goto*//*Label 2404*/ 122189, // Rule ID 2542 //
45654 GIM_CheckFeatures, GIFBS_HasBF16_HasNEON,
45655 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
45656 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45657 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
45658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
45659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45660 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45661 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
45662 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm_odd,
45663 // MIs[1] Operand 1
45664 // No operand predicates
45665 GIM_CheckIsSafeToFold, /*InsnID*/1,
45666 // (extractelt:{ *:[bf16] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm_odd>>:$lane) => (COPY_TO_REGCLASS:{ *:[bf16] } (VGETLNu16:{ *:[i32] } DPR:{ *:[v4bf16] }:$src, (imm:{ *:[i32] }):$lane), HPR:{ *:[i32] })
45667 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45668 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VGETLNu16,
45669 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
45670 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
45671 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // lane
45672 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
45673 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45674 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
45676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
45677 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45678 GIR_EraseFromParent, /*InsnID*/0,
45679 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, ARM::HPRRegClassID,
45680 // GIR_Coverage, 2542,
45681 GIR_Done,
45682 // Label 2404: @122189
45683 GIM_Reject,
45684 // Label 50: @122190
45685 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2412*/ 122684,
45686 /*GILLT_s32*//*Label 2405*/ 122210, 0,
45687 /*GILLT_v2s32*//*Label 2406*/ 122288, 0, 0,
45688 /*GILLT_v4s16*//*Label 2407*/ 122328,
45689 /*GILLT_v4s32*//*Label 2408*/ 122368, 0, 0,
45690 /*GILLT_v8s8*//*Label 2409*/ 122460,
45691 /*GILLT_v8s16*//*Label 2410*/ 122500, 0, 0,
45692 /*GILLT_v16s8*//*Label 2411*/ 122592,
45693 // Label 2405: @122210
45694 GIM_Try, /*On fail goto*//*Label 2413*/ 122287,
45695 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45696 GIM_Try, /*On fail goto*//*Label 2414*/ 122251, // Rule ID 197 //
45697 GIM_CheckFeatures, GIFBS_HasV5T_IsARM,
45698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
45699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
45700 // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45701 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLZ,
45702 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
45703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
45704 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45705 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45706 GIR_EraseFromParent, /*InsnID*/0,
45707 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45708 // GIR_Coverage, 197,
45709 GIR_Done,
45710 // Label 2414: @122251
45711 GIM_Try, /*On fail goto*//*Label 2415*/ 122286, // Rule ID 541 //
45712 GIM_CheckFeatures, GIFBS_IsThumb2,
45713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
45714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
45715 // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLZ,
45717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
45718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
45719 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45720 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45721 GIR_EraseFromParent, /*InsnID*/0,
45722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45723 // GIR_Coverage, 541,
45724 GIR_Done,
45725 // Label 2415: @122286
45726 GIM_Reject,
45727 // Label 2413: @122287
45728 GIM_Reject,
45729 // Label 2406: @122288
45730 GIM_Try, /*On fail goto*//*Label 2416*/ 122327, // Rule ID 1564 //
45731 GIM_CheckFeatures, GIFBS_HasNEON,
45732 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
45733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45735 // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45736 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv2i32,
45737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45738 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45739 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45740 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45741 GIR_EraseFromParent, /*InsnID*/0,
45742 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45743 // GIR_Coverage, 1564,
45744 GIR_Done,
45745 // Label 2416: @122327
45746 GIM_Reject,
45747 // Label 2407: @122328
45748 GIM_Try, /*On fail goto*//*Label 2417*/ 122367, // Rule ID 1563 //
45749 GIM_CheckFeatures, GIFBS_HasNEON,
45750 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
45751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45753 // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i16,
45755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45757 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45758 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45759 GIR_EraseFromParent, /*InsnID*/0,
45760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45761 // GIR_Coverage, 1563,
45762 GIR_Done,
45763 // Label 2417: @122367
45764 GIM_Reject,
45765 // Label 2408: @122368
45766 GIM_Try, /*On fail goto*//*Label 2418*/ 122459,
45767 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
45768 GIM_Try, /*On fail goto*//*Label 2419*/ 122409, // Rule ID 1567 //
45769 GIM_CheckFeatures, GIFBS_HasNEON,
45770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45772 // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv4i32,
45774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45776 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45777 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45778 GIR_EraseFromParent, /*InsnID*/0,
45779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45780 // GIR_Coverage, 1567,
45781 GIR_Done,
45782 // Label 2419: @122409
45783 GIM_Try, /*On fail goto*//*Label 2420*/ 122458, // Rule ID 3624 //
45784 GIM_CheckFeatures, GIFBS_HasMVEInt,
45785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45787 // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
45788 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45789 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45790 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45791 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs32,
45792 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
45794 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45795 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45796 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45797 GIR_EraseFromParent, /*InsnID*/0,
45798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45799 // GIR_Coverage, 3624,
45800 GIR_Done,
45801 // Label 2420: @122458
45802 GIM_Reject,
45803 // Label 2418: @122459
45804 GIM_Reject,
45805 // Label 2409: @122460
45806 GIM_Try, /*On fail goto*//*Label 2421*/ 122499, // Rule ID 1562 //
45807 GIM_CheckFeatures, GIFBS_HasNEON,
45808 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
45809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45811 // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i8,
45813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45815 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45816 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45817 GIR_EraseFromParent, /*InsnID*/0,
45818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45819 // GIR_Coverage, 1562,
45820 GIR_Done,
45821 // Label 2421: @122499
45822 GIM_Reject,
45823 // Label 2410: @122500
45824 GIM_Try, /*On fail goto*//*Label 2422*/ 122591,
45825 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
45826 GIM_Try, /*On fail goto*//*Label 2423*/ 122541, // Rule ID 1566 //
45827 GIM_CheckFeatures, GIFBS_HasNEON,
45828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45830 // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45831 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv8i16,
45832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45834 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45835 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45836 GIR_EraseFromParent, /*InsnID*/0,
45837 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45838 // GIR_Coverage, 1566,
45839 GIR_Done,
45840 // Label 2423: @122541
45841 GIM_Try, /*On fail goto*//*Label 2424*/ 122590, // Rule ID 3622 //
45842 GIM_CheckFeatures, GIFBS_HasMVEInt,
45843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45845 // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
45846 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45847 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45848 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs16,
45850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
45852 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45853 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45854 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45855 GIR_EraseFromParent, /*InsnID*/0,
45856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45857 // GIR_Coverage, 3622,
45858 GIR_Done,
45859 // Label 2424: @122590
45860 GIM_Reject,
45861 // Label 2422: @122591
45862 GIM_Reject,
45863 // Label 2411: @122592
45864 GIM_Try, /*On fail goto*//*Label 2425*/ 122683,
45865 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
45866 GIM_Try, /*On fail goto*//*Label 2426*/ 122633, // Rule ID 1565 //
45867 GIM_CheckFeatures, GIFBS_HasNEON,
45868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45870 // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLZv16i8,
45872 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45874 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45875 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45876 GIR_EraseFromParent, /*InsnID*/0,
45877 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45878 // GIR_Coverage, 1565,
45879 GIR_Done,
45880 // Label 2426: @122633
45881 GIM_Try, /*On fail goto*//*Label 2427*/ 122682, // Rule ID 3620 //
45882 GIM_CheckFeatures, GIFBS_HasMVEInt,
45883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
45884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
45885 // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
45886 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45887 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
45888 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
45889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VCLZs8,
45890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
45891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
45892 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
45893 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45894 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
45895 GIR_EraseFromParent, /*InsnID*/0,
45896 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45897 // GIR_Coverage, 3620,
45898 GIR_Done,
45899 // Label 2427: @122682
45900 GIM_Reject,
45901 // Label 2425: @122683
45902 GIM_Reject,
45903 // Label 2412: @122684
45904 GIM_Reject,
45905 // Label 51: @122685
45906 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/10, 15, /*)*//*default:*//*Label 2430*/ 122776,
45907 /*GILLT_v8s8*//*Label 2428*/ 122696, 0, 0, 0,
45908 /*GILLT_v16s8*//*Label 2429*/ 122736,
45909 // Label 2428: @122696
45910 GIM_Try, /*On fail goto*//*Label 2431*/ 122735, // Rule ID 1568 //
45911 GIM_CheckFeatures, GIFBS_HasNEON,
45912 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
45913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
45914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
45915 // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTd,
45917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45919 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45920 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45921 GIR_EraseFromParent, /*InsnID*/0,
45922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45923 // GIR_Coverage, 1568,
45924 GIR_Done,
45925 // Label 2431: @122735
45926 GIM_Reject,
45927 // Label 2429: @122736
45928 GIM_Try, /*On fail goto*//*Label 2432*/ 122775, // Rule ID 1569 //
45929 GIM_CheckFeatures, GIFBS_HasNEON,
45930 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
45931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
45932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
45933 // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCNTq,
45935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
45936 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
45937 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45938 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45939 GIR_EraseFromParent, /*InsnID*/0,
45940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45941 // GIR_Coverage, 1569,
45942 GIR_Done,
45943 // Label 2432: @122775
45944 GIM_Reject,
45945 // Label 2430: @122776
45946 GIM_Reject,
45947 // Label 52: @122777
45948 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 12, /*)*//*default:*//*Label 2436*/ 123015,
45949 /*GILLT_s32*//*Label 2433*/ 122794, 0, 0, 0, 0, 0,
45950 /*GILLT_v4s32*//*Label 2434*/ 122907, 0, 0, 0,
45951 /*GILLT_v8s16*//*Label 2435*/ 122961,
45952 // Label 2433: @122794
45953 GIM_Try, /*On fail goto*//*Label 2437*/ 122906,
45954 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
45955 GIM_Try, /*On fail goto*//*Label 2438*/ 122835, // Rule ID 199 //
45956 GIM_CheckFeatures, GIFBS_HasV6_IsARM,
45957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
45958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
45959 // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45960 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV,
45961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
45962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
45963 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45964 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45965 GIR_EraseFromParent, /*InsnID*/0,
45966 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45967 // GIR_Coverage, 199,
45968 GIR_Done,
45969 // Label 2438: @122835
45970 GIM_Try, /*On fail goto*//*Label 2439*/ 122870, // Rule ID 333 //
45971 GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
45972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
45973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
45974 // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
45975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV,
45976 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
45977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
45978 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45979 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45980 GIR_EraseFromParent, /*InsnID*/0,
45981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45982 // GIR_Coverage, 333,
45983 GIR_Done,
45984 // Label 2439: @122870
45985 GIM_Try, /*On fail goto*//*Label 2440*/ 122905, // Rule ID 543 //
45986 GIM_CheckFeatures, GIFBS_IsThumb2,
45987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
45988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
45989 // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV,
45991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
45992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
45993 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
45994 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
45995 GIR_EraseFromParent, /*InsnID*/0,
45996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
45997 // GIR_Coverage, 543,
45998 GIR_Done,
45999 // Label 2440: @122905
46000 GIM_Reject,
46001 // Label 2437: @122906
46002 GIM_Reject,
46003 // Label 2434: @122907
46004 GIM_Try, /*On fail goto*//*Label 2441*/ 122960, // Rule ID 3325 //
46005 GIM_CheckFeatures, GIFBS_HasMVEInt,
46006 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46009 // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
46010 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46011 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46012 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46013 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV32_8,
46014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
46016 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46017 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46018 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46019 GIR_EraseFromParent, /*InsnID*/0,
46020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46021 // GIR_Coverage, 3325,
46022 GIR_Done,
46023 // Label 2441: @122960
46024 GIM_Reject,
46025 // Label 2435: @122961
46026 GIM_Try, /*On fail goto*//*Label 2442*/ 123014, // Rule ID 3324 //
46027 GIM_CheckFeatures, GIFBS_HasMVEInt,
46028 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46031 // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
46032 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46033 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46034 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VREV16_8,
46036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
46038 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46039 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46040 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46041 GIR_EraseFromParent, /*InsnID*/0,
46042 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46043 // GIR_Coverage, 3324,
46044 GIR_Done,
46045 // Label 2442: @123014
46046 GIM_Reject,
46047 // Label 2436: @123015
46048 GIM_Reject,
46049 // Label 53: @123016
46050 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 15, /*)*//*default:*//*Label 2447*/ 123366,
46051 /*GILLT_s32*//*Label 2443*/ 123036, 0, 0, 0, 0, 0,
46052 /*GILLT_v4s32*//*Label 2444*/ 123114, 0, 0, 0,
46053 /*GILLT_v8s16*//*Label 2445*/ 123198, 0, 0,
46054 /*GILLT_v16s8*//*Label 2446*/ 123282,
46055 // Label 2443: @123036
46056 GIM_Try, /*On fail goto*//*Label 2448*/ 123113,
46057 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46058 GIM_Try, /*On fail goto*//*Label 2449*/ 123077, // Rule ID 198 //
46059 GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
46060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
46061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
46062 // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
46063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RBIT,
46064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
46065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
46066 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46067 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46068 GIR_EraseFromParent, /*InsnID*/0,
46069 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46070 // GIR_Coverage, 198,
46071 GIR_Done,
46072 // Label 2449: @123077
46073 GIM_Try, /*On fail goto*//*Label 2450*/ 123112, // Rule ID 542 //
46074 GIM_CheckFeatures, GIFBS_IsThumb2,
46075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
46076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
46077 // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
46078 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RBIT,
46079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
46080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
46081 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46082 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46083 GIR_EraseFromParent, /*InsnID*/0,
46084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46085 // GIR_Coverage, 542,
46086 GIR_Done,
46087 // Label 2450: @123112
46088 GIM_Reject,
46089 // Label 2448: @123113
46090 GIM_Reject,
46091 // Label 2444: @123114
46092 GIM_Try, /*On fail goto*//*Label 2451*/ 123197, // Rule ID 4638 //
46093 GIM_CheckFeatures, GIFBS_HasMVEInt,
46094 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46097 // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
46098 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46099 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
46100 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46101 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
46102 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
46103 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
46104 GIR_AddImm, /*InsnID*/1, /*Imm*/32,
46105 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
46106 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46107 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46108 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46109 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR32,
46110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
46112 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46113 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46114 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46115 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
46116 GIR_EraseFromParent, /*InsnID*/0,
46117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46118 // GIR_Coverage, 4638,
46119 GIR_Done,
46120 // Label 2451: @123197
46121 GIM_Reject,
46122 // Label 2445: @123198
46123 GIM_Try, /*On fail goto*//*Label 2452*/ 123281, // Rule ID 4639 //
46124 GIM_CheckFeatures, GIFBS_HasMVEInt,
46125 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46128 // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
46129 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46130 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
46131 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46132 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
46133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
46134 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
46135 GIR_AddImm, /*InsnID*/1, /*Imm*/16,
46136 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
46137 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46138 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46139 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46140 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR16,
46141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
46143 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46144 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46145 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46146 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
46147 GIR_EraseFromParent, /*InsnID*/0,
46148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46149 // GIR_Coverage, 4639,
46150 GIR_Done,
46151 // Label 2452: @123281
46152 GIM_Reject,
46153 // Label 2446: @123282
46154 GIM_Try, /*On fail goto*//*Label 2453*/ 123365, // Rule ID 4637 //
46155 GIM_CheckFeatures, GIFBS_HasMVEInt,
46156 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
46157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46159 // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
46160 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46161 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
46162 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46163 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/0,
46164 GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::t2MOVi,
46165 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
46166 GIR_AddImm, /*InsnID*/1, /*Imm*/8,
46167 GIR_AddImm, /*InsnID*/1, /*Imm*/14,
46168 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46169 GIR_AddRegister, /*InsnID*/1, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46170 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46171 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VBRSR8,
46172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46173 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val1
46174 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46175 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46176 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46177 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
46178 GIR_EraseFromParent, /*InsnID*/0,
46179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46180 // GIR_Coverage, 4637,
46181 GIR_Done,
46182 // Label 2453: @123365
46183 GIM_Reject,
46184 // Label 2447: @123366
46185 GIM_Reject,
46186 // Label 54: @123367
46187 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2459*/ 123565,
46188 /*GILLT_s16*//*Label 2454*/ 123385,
46189 /*GILLT_s32*//*Label 2455*/ 123409,
46190 /*GILLT_s64*//*Label 2456*/ 123433, 0, 0, 0, 0,
46191 /*GILLT_v4s32*//*Label 2457*/ 123457, 0, 0, 0,
46192 /*GILLT_v8s16*//*Label 2458*/ 123511,
46193 // Label 2454: @123385
46194 GIM_Try, /*On fail goto*//*Label 2460*/ 123408, // Rule ID 694 //
46195 GIM_CheckFeatures, GIFBS_HasFullFP16,
46196 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
46197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
46198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
46199 // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46200 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPH,
46201 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46202 // GIR_Coverage, 694,
46203 GIR_Done,
46204 // Label 2460: @123408
46205 GIM_Reject,
46206 // Label 2455: @123409
46207 GIM_Try, /*On fail goto*//*Label 2461*/ 123432, // Rule ID 695 //
46208 GIM_CheckFeatures, GIFBS_HasFPARMv8,
46209 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
46211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
46212 // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46213 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPS,
46214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46215 // GIR_Coverage, 695,
46216 GIR_Done,
46217 // Label 2461: @123432
46218 GIM_Reject,
46219 // Label 2456: @123433
46220 GIM_Try, /*On fail goto*//*Label 2462*/ 123456, // Rule ID 696 //
46221 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
46222 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
46223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46225 // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46226 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTPD,
46227 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46228 // GIR_Coverage, 696,
46229 GIR_Done,
46230 // Label 2462: @123456
46231 GIM_Reject,
46232 // Label 2457: @123457
46233 GIM_Try, /*On fail goto*//*Label 2463*/ 123510, // Rule ID 3940 //
46234 GIM_CheckFeatures, GIFBS_HasMVEFloat,
46235 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46238 // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46239 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46241 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32P,
46243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
46245 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46246 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46247 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46248 GIR_EraseFromParent, /*InsnID*/0,
46249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46250 // GIR_Coverage, 3940,
46251 GIR_Done,
46252 // Label 2463: @123510
46253 GIM_Reject,
46254 // Label 2458: @123511
46255 GIM_Try, /*On fail goto*//*Label 2464*/ 123564, // Rule ID 3928 //
46256 GIM_CheckFeatures, GIFBS_HasMVEFloat,
46257 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46260 // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46261 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46262 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46263 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46264 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16P,
46265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
46267 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46268 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46269 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46270 GIR_EraseFromParent, /*InsnID*/0,
46271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46272 // GIR_Coverage, 3928,
46273 GIR_Done,
46274 // Label 2464: @123564
46275 GIM_Reject,
46276 // Label 2459: @123565
46277 GIM_Reject,
46278 // Label 55: @123566
46279 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2468*/ 123695,
46280 /*GILLT_s16*//*Label 2465*/ 123575,
46281 /*GILLT_s32*//*Label 2466*/ 123615,
46282 /*GILLT_s64*//*Label 2467*/ 123655,
46283 // Label 2465: @123575
46284 GIM_Try, /*On fail goto*//*Label 2469*/ 123614, // Rule ID 702 //
46285 GIM_CheckFeatures, GIFBS_HasFullFP16,
46286 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
46287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
46288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
46289 // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTH,
46291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
46292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
46293 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46294 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46295 GIR_EraseFromParent, /*InsnID*/0,
46296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46297 // GIR_Coverage, 702,
46298 GIR_Done,
46299 // Label 2469: @123614
46300 GIM_Reject,
46301 // Label 2466: @123615
46302 GIM_Try, /*On fail goto*//*Label 2470*/ 123654, // Rule ID 701 //
46303 GIM_CheckFeatures, GIFBS_HasVFP2,
46304 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
46306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
46307 // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTS,
46309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
46310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
46311 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46312 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46313 GIR_EraseFromParent, /*InsnID*/0,
46314 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46315 // GIR_Coverage, 701,
46316 GIR_Done,
46317 // Label 2470: @123654
46318 GIM_Reject,
46319 // Label 2467: @123655
46320 GIM_Try, /*On fail goto*//*Label 2471*/ 123694, // Rule ID 700 //
46321 GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
46322 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
46323 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46325 // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSQRTD,
46327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
46328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
46329 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46330 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46331 GIR_EraseFromParent, /*InsnID*/0,
46332 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46333 // GIR_Coverage, 700,
46334 GIR_Done,
46335 // Label 2471: @123694
46336 GIM_Reject,
46337 // Label 2468: @123695
46338 GIM_Reject,
46339 // Label 56: @123696
46340 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2477*/ 123894,
46341 /*GILLT_s16*//*Label 2472*/ 123714,
46342 /*GILLT_s32*//*Label 2473*/ 123738,
46343 /*GILLT_s64*//*Label 2474*/ 123762, 0, 0, 0, 0,
46344 /*GILLT_v4s32*//*Label 2475*/ 123786, 0, 0, 0,
46345 /*GILLT_v8s16*//*Label 2476*/ 123840,
46346 // Label 2472: @123714
46347 GIM_Try, /*On fail goto*//*Label 2478*/ 123737, // Rule ID 697 //
46348 GIM_CheckFeatures, GIFBS_HasFullFP16,
46349 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
46350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
46351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
46352 // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46353 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMH,
46354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46355 // GIR_Coverage, 697,
46356 GIR_Done,
46357 // Label 2478: @123737
46358 GIM_Reject,
46359 // Label 2473: @123738
46360 GIM_Try, /*On fail goto*//*Label 2479*/ 123761, // Rule ID 698 //
46361 GIM_CheckFeatures, GIFBS_HasFPARMv8,
46362 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
46364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
46365 // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMS,
46367 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46368 // GIR_Coverage, 698,
46369 GIR_Done,
46370 // Label 2479: @123761
46371 GIM_Reject,
46372 // Label 2474: @123762
46373 GIM_Try, /*On fail goto*//*Label 2480*/ 123785, // Rule ID 699 //
46374 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
46375 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
46376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46378 // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46379 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::VRINTMD,
46380 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46381 // GIR_Coverage, 699,
46382 GIR_Done,
46383 // Label 2480: @123785
46384 GIM_Reject,
46385 // Label 2475: @123786
46386 GIM_Try, /*On fail goto*//*Label 2481*/ 123839, // Rule ID 3938 //
46387 GIM_CheckFeatures, GIFBS_HasMVEFloat,
46388 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46391 // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46392 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46393 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46394 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46395 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32M,
46396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
46398 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46399 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46400 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46401 GIR_EraseFromParent, /*InsnID*/0,
46402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46403 // GIR_Coverage, 3938,
46404 GIR_Done,
46405 // Label 2481: @123839
46406 GIM_Reject,
46407 // Label 2476: @123840
46408 GIM_Try, /*On fail goto*//*Label 2482*/ 123893, // Rule ID 3926 //
46409 GIM_CheckFeatures, GIFBS_HasMVEFloat,
46410 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46413 // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46414 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46415 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46416 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46417 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16M,
46418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
46420 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46421 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46422 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46423 GIR_EraseFromParent, /*InsnID*/0,
46424 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46425 // GIR_Coverage, 3926,
46426 GIR_Done,
46427 // Label 2482: @123893
46428 GIM_Reject,
46429 // Label 2477: @123894
46430 GIM_Reject,
46431 // Label 57: @123895
46432 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 12, /*)*//*default:*//*Label 2488*/ 124141,
46433 /*GILLT_s16*//*Label 2483*/ 123913,
46434 /*GILLT_s32*//*Label 2484*/ 123953,
46435 /*GILLT_s64*//*Label 2485*/ 123993, 0, 0, 0, 0,
46436 /*GILLT_v4s32*//*Label 2486*/ 124033, 0, 0, 0,
46437 /*GILLT_v8s16*//*Label 2487*/ 124087,
46438 // Label 2483: @123913
46439 GIM_Try, /*On fail goto*//*Label 2489*/ 123952, // Rule ID 685 //
46440 GIM_CheckFeatures, GIFBS_HasFullFP16,
46441 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
46442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
46443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
46444 // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXH,
46446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
46447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
46448 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46449 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46450 GIR_EraseFromParent, /*InsnID*/0,
46451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46452 // GIR_Coverage, 685,
46453 GIR_Done,
46454 // Label 2489: @123952
46455 GIM_Reject,
46456 // Label 2484: @123953
46457 GIM_Try, /*On fail goto*//*Label 2490*/ 123992, // Rule ID 686 //
46458 GIM_CheckFeatures, GIFBS_HasFPARMv8,
46459 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
46461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
46462 // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXS,
46464 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
46465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
46466 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46467 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46468 GIR_EraseFromParent, /*InsnID*/0,
46469 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46470 // GIR_Coverage, 686,
46471 GIR_Done,
46472 // Label 2490: @123992
46473 GIM_Reject,
46474 // Label 2485: @123993
46475 GIM_Try, /*On fail goto*//*Label 2491*/ 124032, // Rule ID 687 //
46476 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
46477 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
46478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46480 // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXD,
46482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
46483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
46484 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46485 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46486 GIR_EraseFromParent, /*InsnID*/0,
46487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46488 // GIR_Coverage, 687,
46489 GIR_Done,
46490 // Label 2491: @124032
46491 GIM_Reject,
46492 // Label 2486: @124033
46493 GIM_Try, /*On fail goto*//*Label 2492*/ 124086, // Rule ID 3932 //
46494 GIM_CheckFeatures, GIFBS_HasMVEFloat,
46495 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
46496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46498 // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46499 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46500 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46501 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf32X,
46503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
46505 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46506 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46507 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46508 GIR_EraseFromParent, /*InsnID*/0,
46509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46510 // GIR_Coverage, 3932,
46511 GIR_Done,
46512 // Label 2492: @124086
46513 GIM_Reject,
46514 // Label 2487: @124087
46515 GIM_Try, /*On fail goto*//*Label 2493*/ 124140, // Rule ID 3920 //
46516 GIM_CheckFeatures, GIFBS_HasMVEFloat,
46517 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
46518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::MQPRRegClassID,
46519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::MQPRRegClassID,
46520 // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46521 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46522 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
46523 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
46524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVE_VRINTf16X,
46525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Qd
46526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // val
46527 GIR_AddImm, /*InsnID*/0, /*Imm*/0,
46528 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46529 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
46530 GIR_EraseFromParent, /*InsnID*/0,
46531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46532 // GIR_Coverage, 3920,
46533 GIR_Done,
46534 // Label 2493: @124140
46535 GIM_Reject,
46536 // Label 2488: @124141
46537 GIM_Reject,
46538 // Label 58: @124142
46539 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 2497*/ 124271,
46540 /*GILLT_s16*//*Label 2494*/ 124151,
46541 /*GILLT_s32*//*Label 2495*/ 124191,
46542 /*GILLT_s64*//*Label 2496*/ 124231,
46543 // Label 2494: @124151
46544 GIM_Try, /*On fail goto*//*Label 2498*/ 124190, // Rule ID 682 //
46545 GIM_CheckFeatures, GIFBS_HasFullFP16,
46546 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
46547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
46548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
46549 // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRH,
46551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
46552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
46553 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46554 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46555 GIR_EraseFromParent, /*InsnID*/0,
46556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46557 // GIR_Coverage, 682,
46558 GIR_Done,
46559 // Label 2498: @124190
46560 GIM_Reject,
46561 // Label 2495: @124191
46562 GIM_Try, /*On fail goto*//*Label 2499*/ 124230, // Rule ID 683 //
46563 GIM_CheckFeatures, GIFBS_HasFPARMv8,
46564 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
46565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
46566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
46567 // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRS,
46569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
46570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
46571 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46572 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46573 GIR_EraseFromParent, /*InsnID*/0,
46574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46575 // GIR_Coverage, 683,
46576 GIR_Done,
46577 // Label 2499: @124230
46578 GIM_Reject,
46579 // Label 2496: @124231
46580 GIM_Try, /*On fail goto*//*Label 2500*/ 124270, // Rule ID 684 //
46581 GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
46582 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
46583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
46584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
46585 // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTRD,
46587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
46588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
46589 GIR_AddImm, /*InsnID*/0, /*Imm*/14,
46590 GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
46591 GIR_EraseFromParent, /*InsnID*/0,
46592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
46593 // GIR_Coverage, 684,
46594 GIR_Done,
46595 // Label 2500: @124270
46596 GIM_Reject,
46597 // Label 2497: @124271
46598 GIM_Reject,
46599 // Label 59: @124272
46600 GIM_Reject,
46601 };
46602 return MatchTable0;
46603}
46604#endif // ifdef GET_GLOBALISEL_IMPL
46605#ifdef GET_GLOBALISEL_PREDICATES_DECL
46606PredicateBitset AvailableModuleFeatures;
46607mutable PredicateBitset AvailableFunctionFeatures;
46608PredicateBitset getAvailableFeatures() const {
46609 return AvailableModuleFeatures | AvailableFunctionFeatures;
46610}
46611PredicateBitset
46612computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
46613PredicateBitset
46614computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
46615 const MachineFunction *MF) const;
46616void setupGeneratedPerFunctionState(MachineFunction &MF) override;
46617#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
46618#ifdef GET_GLOBALISEL_PREDICATES_INIT
46619AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
46620AvailableFunctionFeatures()
46621#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
46622